JPS5899867A - 並列処理方式 - Google Patents
並列処理方式Info
- Publication number
- JPS5899867A JPS5899867A JP19738881A JP19738881A JPS5899867A JP S5899867 A JPS5899867 A JP S5899867A JP 19738881 A JP19738881 A JP 19738881A JP 19738881 A JP19738881 A JP 19738881A JP S5899867 A JPS5899867 A JP S5899867A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- processors
- instruction
- memory
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 claims abstract description 56
- 230000006854 communication Effects 0.000 claims abstract description 23
- 238000004891 communication Methods 0.000 claims abstract description 23
- 238000003672 processing method Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000007175 bidirectional communication Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
- Advance Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19738881A JPS5899867A (ja) | 1981-12-08 | 1981-12-08 | 並列処理方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19738881A JPS5899867A (ja) | 1981-12-08 | 1981-12-08 | 並列処理方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5899867A true JPS5899867A (ja) | 1983-06-14 |
JPS6153754B2 JPS6153754B2 (enrdf_load_stackoverflow) | 1986-11-19 |
Family
ID=16373674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19738881A Granted JPS5899867A (ja) | 1981-12-08 | 1981-12-08 | 並列処理方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5899867A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01102644A (ja) * | 1987-09-30 | 1989-04-20 | Internatl Business Mach Corp <Ibm> | パイプライン式処理装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63231362A (ja) * | 1987-03-19 | 1988-09-27 | Ricoh Co Ltd | 複写機 |
JP4477805B2 (ja) * | 2001-04-18 | 2010-06-09 | パナソニック電工株式会社 | 情報処理装置 |
-
1981
- 1981-12-08 JP JP19738881A patent/JPS5899867A/ja active Granted
Non-Patent Citations (1)
Title |
---|
IEEE CATALOG=1978 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01102644A (ja) * | 1987-09-30 | 1989-04-20 | Internatl Business Mach Corp <Ibm> | パイプライン式処理装置 |
Also Published As
Publication number | Publication date |
---|---|
JPS6153754B2 (enrdf_load_stackoverflow) | 1986-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10564980B2 (en) | Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator | |
US10445098B2 (en) | Processors and methods for privileged configuration in a spatial array | |
US10515046B2 (en) | Processors, methods, and systems with a configurable spatial accelerator | |
KR100267091B1 (ko) | 비대칭싱글-칩이중멀티프로세서의정합및동기화 | |
US6581152B2 (en) | Methods and apparatus for instruction addressing in indirect VLIW processors | |
US5872987A (en) | Massively parallel computer including auxiliary vector processor | |
US8335812B2 (en) | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation | |
EP0455345B1 (en) | Programmable controller | |
US6128720A (en) | Distributed processing array with component processors performing customized interpretation of instructions | |
US5659785A (en) | Array processor communication architecture with broadcast processor instructions | |
EP0464494B1 (en) | A high performance pipelined emulator | |
US20180189063A1 (en) | Processors, methods, and systems with a configurable spatial accelerator | |
US20180189231A1 (en) | Processors, methods, and systems with a configurable spatial accelerator | |
WO2019194916A1 (en) | Apparatuses, methods, and systems for remote memory access in a configurable spatial accelerator | |
JPS61276032A (ja) | 情報処理装置 | |
EA004196B1 (ru) | Управляющий программный продукт и система обработки данных | |
JP2003005958A (ja) | データ処理装置およびその制御方法 | |
US7139899B2 (en) | Selected register decode values for pipeline stage register addressing | |
EP0295646A2 (en) | Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus | |
EP0521486B1 (en) | Hierarchical structure processor | |
JP3004108B2 (ja) | 情報処理装置 | |
JPS5899867A (ja) | 並列処理方式 | |
US20230359385A1 (en) | Quick clearing of registers | |
US6654870B1 (en) | Methods and apparatus for establishing port priority functions in a VLIW processor | |
JP2004503872A (ja) | 共同利用コンピュータシステム |