JPS5898931A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5898931A
JPS5898931A JP19918581A JP19918581A JPS5898931A JP S5898931 A JPS5898931 A JP S5898931A JP 19918581 A JP19918581 A JP 19918581A JP 19918581 A JP19918581 A JP 19918581A JP S5898931 A JPS5898931 A JP S5898931A
Authority
JP
Japan
Prior art keywords
thin film
pattern
resist
etching
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19918581A
Other languages
Japanese (ja)
Inventor
Kazuhiro Tanaka
和裕 田中
Tsuneo Yoshida
吉田 常夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19918581A priority Critical patent/JPS5898931A/en
Publication of JPS5898931A publication Critical patent/JPS5898931A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/09Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094Multilayer resist systems, e.g. planarising layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a minute pattern readily, by forming a resist pattern on a heat resisting resin layer on a substrate by dry development, thereafter performing etching, thereby making all the processes dry. CONSTITUTION:A thin metal film 2 is formed on the glass substrate 1, and a polyimide resin is applied thereon as the heat resisting resin layer 6. Then an SiO2 thin film 7 is formed. A resist 3 is further applied. Then, with the resist pattern 4 as a mask, the SiO2 thin film 7 is etched. Thereafter, with a pattern 10 of the thin film 7 as a mask, the resin 6 is etched in the plasma in O2 gas. In this method, the pattern, which is very sharp and has a very large aspect ratio, can be obtained. Therefore, the etching of the thin chromium film 2 can be performed readily, and the sharp edges can be obtained.

Description

【発明の詳細な説明】 この発明は、基板上に形成されたレジスト膜をエツチン
グする工程をもった半導体装置の製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that includes a step of etching a resist film formed on a substrate.

集積回路などの半導体装置を製造する場合、一般にフォ
トリングラフィ技術によりパターン形式%式% 近年、この種装置の集積度が高くなるOK伴い、7オト
リソグラフイ技術の重要性が増し、低欠陥化、自動化、
省力化などの技術開発が盛んになってき九、とくにドラ
イ技術をリングラフィ工程全体に適用する試みは低欠陥
化、自動化、省力化には有効であシ、種々の分野で研究
・開発がなされつつある。たとえばマスク製造工程にお
いては、エツチング工程におけるドライ化が実用化され
ている一方、現像工程では未だ溶液による現像方法が広
く使用されてお夛、全工程でのドライ化はまだ実用化さ
れていないのが現状である。
When manufacturing semiconductor devices such as integrated circuits, photolithography technology is generally used to form patterns. ,Automation,
Technological development for labor-saving and other purposes has become active9, and attempts to apply dry technology to the entire phosphorography process are effective in reducing defects, automation, and labor-saving, and research and development are being carried out in various fields. It's coming. For example, in the mask manufacturing process, while dry etching has been put into practical use in the etching process, solution development is still widely used in the developing process, and drying in all processes has not yet been put into practical use. is the current situation.

以下、従来のマスク製造方法を第1図(勾〜(7)を参
照しつつ説明する。
Hereinafter, a conventional mask manufacturing method will be explained with reference to FIG.

まず、第1図(4)に示すようK、ガラス基板(1)K
金属薄膜、九とえば金属クロム薄膜(りを被着させ、さ
らKその上に電子ビーム用しジスF、たとえばポリメチ
ルメタクリレ−) (PMMム)(3)を約5000人
の厚さに被着し、170℃で20分間プリベークを行な
う、つぎに第1図C)に示すように電子ビームを9X1
0  c/dのドーズ量にて所望のパターンに対応して
照射する。さらにメチルイソブチルケトン(MIBK)
 (8)に対してインプロパツール(HFム)10割合
の溶液を用意し、この溶液を用いて現像を行ない、第1
図(C)のようなレジストパターン(4)を作成する。
First, as shown in Fig. 1 (4), K, the glass substrate (1)
A thin metal film, such as a metal chromium thin film (9) is deposited, and then a film (3) for electron beam use is deposited to a thickness of about 5,000 mm. Deposit and pre-bake at 170°C for 20 minutes, then apply an electron beam to a 9X1
Irradiation is performed at a dose of 0 c/d in accordance with the desired pattern. Furthermore, methyl isobutyl ketone (MIBK)
Prepare a solution of Improper Tool (HF) at a ratio of 10 to (8), perform development using this solution, and
A resist pattern (4) as shown in Figure (C) is created.

ついで、リンス・乾燥後、第1図ψ)に示すようにレジ
ストパターン(4)をマ′スクとして金属薄!14(2
)をエツチング処理する。しかる後、第1図(狗に示す
ようにレジストパターン(4)を除去すれば所望の金属
薄膜パターン(5)が得られる。一般に電子ビーム露光
用レジス[3)a耐プラズマ性、つtb分解性が悪いた
め、薬液によるエツチング、つまりウェットエツチング
で処理する。
Then, after rinsing and drying, the resist pattern (4) is used as a mask to form a thin metal film as shown in Figure 1 ψ). 14 (2
) is etched. After that, the desired metal thin film pattern (5) is obtained by removing the resist pattern (4) as shown in Figure 1 (dog). Generally, the resist pattern (3) for electron beam exposure has a plasma resistance, and tb decomposition. Because of its poor properties, it is treated with chemical etching, or wet etching.

以上のように、従来のマスク製造方法の現像シよびエツ
チングはウェット処理であシ、溶液中の異物の介在は免
れ得ることはできず、低欠陥化の妨げとなっている。ま
た自動化、省力化も困難であシ、排液処理にも問題があ
る。さらにウェットエツチングではサイドエッチ量が多
く、寸法制御が困難で微細パターンが得にくいなどの欠
点があった・ この発明は以上のような従来のものの欠点を除去するた
めになされ九本ので、基板上の耐熱性樹脂層上にレジス
トパターンをドライ瑣像により形成した後、エツチング
することによシ、全工程をドライ化でき、微細パターン
も容易に形成できる半導体装置の製造方法を提供するこ
とを目的としている。
As described above, development and etching in the conventional mask manufacturing method are wet processes, and the presence of foreign matter in the solution cannot be avoided, which hinders the reduction in defects. Furthermore, automation and labor saving are difficult, and there are also problems with wastewater treatment. Furthermore, wet etching has disadvantages such as a large amount of side etching, making it difficult to control dimensions and making it difficult to obtain fine patterns. The purpose of the present invention is to provide a method for manufacturing a semiconductor device in which the entire process can be made dry by forming a resist pattern on a heat-resistant resin layer using a dry image and then etching it, and in which fine patterns can also be easily formed. It is said that

以下、この発明〇一実施例を図について説明する。Embodiments of this invention will be described below with reference to the drawings.

第2図(5)〜(G)はこの発明に係る半導体装置の製
造方法を工程順に示すものである。
FIGS. 2(5) to 2(G) show the method of manufacturing a semiconductor device according to the present invention in the order of steps.

まず、第2図CA)K示すようK、ガラス基板(1)上
に金属薄膜、九とえは金属クロム薄111(2)を形成
させる。その上に耐熱性樹脂層(6)としてポリイミド
樹脂、たとえば電気絶縁性コーティング剤5P510(
東し社製:商品名)を゛約6000人の厚さに塗布する
。これの塗布後、約80℃で30分間窒素雰囲気中でベ
ーキングを行なう、つぎに酸化シリコン薄膜(8i0*
) (7)をプラズマデポジションにて約800人の厚
さに形成する。さらにレジスト(3)としてIFMR(
富士薬品社製:商品名)を約5000人の厚さく塗布し
、約140℃で30分間窒素雰囲気中でベーキングを行
なう。
First, as shown in FIG. 2 (CA), a metal thin film, eg, metal chromium thin film 111 (2), is formed on a glass substrate (1). On top of that, a heat-resistant resin layer (6) is made of polyimide resin, such as electrically insulating coating agent 5P510 (
Apply Toshisha Co., Ltd. (trade name) to a thickness of about 6,000 people. After coating this, baking is performed in a nitrogen atmosphere at approximately 80°C for 30 minutes, and then a silicon oxide thin film (8i0*
) (7) is formed to a thickness of approximately 800 mm by plasma deposition. Furthermore, as a resist (3), IFMR (
Fuji Yakuhin Co., Ltd. (trade name) was applied to a thickness of about 5,000 people, and baked at about 140° C. for 30 minutes in a nitrogen atmosphere.

−)i!’K、弊2図gQK示すようにレジスト(3)
K電子ビームを選択的に照射して所望のパターンを形成
する。電子ビームのドーズ量は6X1G−’c/dとす
る。電子ビーム照射後、照射部のパターン部の凹凸を表
面荒さ針で測定したところ、約600人の凹状の段差が
認められた。つぎに、このものをプラズマ中で現像し友
、現像条件はウェットエアI Torr中で出カフ0W
にて行ない約60分で現像が完了した。’!II像後の
レジストパターン(4)の膜厚を表面荒さ針で測定した
ところ約2000人の凸状のパターン(4)が得られた
(第2図(C))。このレジストパターン(4)ヲマス
クとし、プラズマ中でCHF、のガス雰囲気で8i0.
薄膜(7)を第2図(D)のようにエツチングしたとこ
ろ、約10分でエツチングが完了した。
-)i! 'K, resist as shown in Figure 2gQK (3)
A desired pattern is formed by selectively irradiating the K electron beam. The dose of the electron beam is 6X1G-'c/d. After electron beam irradiation, the unevenness of the patterned portion of the irradiated area was measured using a surface roughness needle, and approximately 600 concave steps were observed. Next, develop this material in plasma.The development conditions are wet air I Torr and output cap 0W.
The development was completed in about 60 minutes. '! When the film thickness of the resist pattern (4) after the II image was measured with a surface roughness needle, a convex pattern (4) of about 2000 was obtained (FIG. 2(C)). This resist pattern (4) was used as a mask, and 8i0.
When the thin film (7) was etched as shown in FIG. 2(D), the etching was completed in about 10 minutes.

つぎに、こOS i Os (7)のパターン&(Iを
マスクとして、第2図(2)のように耐熱性樹脂(6)
をエツチングした。エツチングの条件は300Wの出力
にてOsガス中のプラズマで行なった。このようにして
得られ九パターンは非常にシャープでしかもアスペクト
比が極めて大きいパターンが得られるため、第2図(1
’)K示すクロム薄111(2)のエツチングも容易に
シャープなエツジが得られ九、クロム薄膜(2)のエツ
チングについても、プラズマ中で約170Wの出力で0
−2 TorrOcclsガス中で行なった。最後に、
耐熱性樹脂(6)および8i0.(7)のパターンを除
去すれば、第2図(G)に示すクロムパターンが得られ
る。
Next, using the OS i Os (7) pattern & (I as a mask, heat-resistant resin (6) is
etched. Etching was performed using plasma in Os gas at an output of 300 W. The nine patterns obtained in this way are very sharp and have an extremely large aspect ratio.
') Etching of chromium thin film 111 (2) shown in K shows a sharp edge can be easily obtained.
-2 TorrOccls gas. lastly,
Heat-resistant resin (6) and 8i0. If pattern (7) is removed, the chrome pattern shown in FIG. 2(G) is obtained.

以上のような方法によれば、マスク製作工程において、
ウェット処理がなくなシ、全てドライ化が可能となるう
え、低欠陥化、省力化、自動化、微細パターン化が期待
できる。
According to the above method, in the mask manufacturing process,
There is no need for wet processing, and everything can be done dry, with the promise of fewer defects, labor savings, automation, and fine patterning.

また、従来、ドライエツチングが不可能であった電子ビ
ーム用レジストも容易にドライエツチングが可能となり
、寸法精度を向上させることができる。さらに、得られ
たレジスト儂は第2図(D)のように耐熱性樹脂(6)
によって高いアスペクト比をもっているため、従来クエ
ハ工程で不可能であり九ドライエツチングも容易に導入
できる。
Further, it is now possible to easily dry-etch the electron beam resist, which has hitherto been impossible to dry-etch, and the dimensional accuracy can be improved. Furthermore, the obtained resist layer is coated with heat-resistant resin (6) as shown in Figure 2 (D).
Since it has a high aspect ratio, dry etching, which is impossible with conventional wafer processes, can be easily introduced.

なお、上記実施例ではガラス基板上にクロム薄11(2
)を形成したものにりいて述べたが、り四ム薄膜以外の
ものでもよく、また基板(1)もガラス基板以外のもの
でもよい。
In addition, in the above embodiment, a chromium thin film 11 (2
), however, other materials may be used, and the substrate (1) may also be other than a glass substrate.

また、上記実施例では、レジスト(3)としてFMRを
例に述べたが他の残膜率の高いレジストでも同様の効果
を奏する。また放射線として電子ビームを例にして述べ
たが、X線やイオンビームでも同様の効果を奏する。耐
熱性樹脂層(6)としては、BP510を例に挙げ九が
、P工Q(日立化成社製:商品名) 、PYLAL工N
 (Dv Font社製:商品名)、Hエーロ00(日
立化成社製:商品名)等でも同様の効果を奏する。
Further, in the above embodiments, FMR was used as the resist (3), but other resists having a high residual film ratio can also produce similar effects. Furthermore, although an electron beam has been described as an example of radiation, similar effects can be achieved with X-rays or ion beams. As the heat-resistant resin layer (6), BP510 is taken as an example.
(manufactured by Dv Font Co., Ltd.: trade name), H Aero 00 (manufactured by Hitachi Chemical Co., Ltd.: trade name), etc. have similar effects.

膜上のように、この発明は基板上の金属薄膜に所定パタ
ーンを形成するにあたシ、金属薄膜上に耐熱性樹脂層、
酸化シリコン薄膜およびレジストを順次形成したのち、
レジストパターンをドライ現偉で形成し、ついでエツチ
ングすることにより、全工程のドライ化が可能となり、
信頼性も高まるうえ、微細パターンも容易に形成できる
効果がある。
In order to form a predetermined pattern on a metal thin film on a substrate, this invention includes a heat-resistant resin layer on the metal thin film,
After sequentially forming a silicon oxide thin film and a resist,
By forming the resist pattern using a dry pattern and then etching it, the entire process can be made dry.
This has the effect of increasing reliability and making it easier to form fine patterns.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の製造方法を工程順に示す断
面図、第2図はこの発明の一実施例による半導体装置の
製造方法を工程順に示す断面図である。 (1)・・・基板、(2)・・・金属薄膜、(3)・・
・電子ビーム露光用レジスト、(4)・・・レジストパ
ターン、(5)・・・所望の金属薄膜パターン、(6)
・・・耐熱性樹脂層、(7)・・・酸化シリコン薄膜。 なお、図中同一符号はそれぞれ同一もしくは相当部分を
示す。 代理人 葛野信−(外1名) 第1図 第2図 手続補正書(fl) 1’> +i’l’ Ii’ b官殿 1、・It fiの表示    特願昭56−1991
85  号2゜発明の名称 半導体装置の製造方法 3、補正をする者 事件との関係   特許出願人 6゜補正の対象 (1)  明細書をつぎのとおり訂正する。
FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps, and FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. (1)...Substrate, (2)...Metal thin film, (3)...
-Resist for electron beam exposure, (4)...Resist pattern, (5)...Desired metal thin film pattern, (6)
...Heat-resistant resin layer, (7)...Silicon oxide thin film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Procedural amendment (fl) 1'>+i'l'Ii' b Government building 1, ・It fi indication Patent application 1987-1991
85 No. 2゜ Title of the invention Method for manufacturing a semiconductor device 3 Relationship with the case of the person making the amendment Patent applicant 6゜ Subject of amendment (1) The description is amended as follows.

Claims (1)

【特許請求の範囲】[Claims] (1)、基板上に形成され丸金属薄膜に所定のパターン
を形成するにあたシ、上記金属薄膜上に耐熱性樹脂層お
よび酸化シリコン薄膜を順次形成した後、この酸化シリ
コン薄膜上にレジスト膜を被着し、ついでレジス)#に
選択的に放射線を照射するとともに該レジスト膜をプラ
ズマ中で現像してレジスF パターンを形成し、しかる
後該レジストパターンをマスクとして上記酸化シリコン
薄膜をエツチングし、さらに耐熱性樹脂層をプラズマ中
でエツチングすることを特徴とする半導体装置の製造方
法。
(1) To form a predetermined pattern on a round metal thin film formed on a substrate, a heat-resistant resin layer and a silicon oxide thin film are sequentially formed on the metal thin film, and then a resist is applied on this silicon oxide thin film. A film is deposited, and then the resist # is selectively irradiated with radiation and the resist film is developed in plasma to form a resist F pattern, and then the silicon oxide thin film is etched using the resist pattern as a mask. A method of manufacturing a semiconductor device, further comprising etching the heat-resistant resin layer in plasma.
JP19918581A 1981-12-08 1981-12-08 Manufacture of semiconductor device Pending JPS5898931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19918581A JPS5898931A (en) 1981-12-08 1981-12-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19918581A JPS5898931A (en) 1981-12-08 1981-12-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5898931A true JPS5898931A (en) 1983-06-13

Family

ID=16403546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19918581A Pending JPS5898931A (en) 1981-12-08 1981-12-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5898931A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052026A (en) * 1983-08-31 1985-03-23 Fujitsu Ltd Formation of fine pattern
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052026A (en) * 1983-08-31 1985-03-23 Fujitsu Ltd Formation of fine pattern
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device

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