JPS6052026A - Formation of fine pattern - Google Patents

Formation of fine pattern

Info

Publication number
JPS6052026A
JPS6052026A JP15956083A JP15956083A JPS6052026A JP S6052026 A JPS6052026 A JP S6052026A JP 15956083 A JP15956083 A JP 15956083A JP 15956083 A JP15956083 A JP 15956083A JP S6052026 A JPS6052026 A JP S6052026A
Authority
JP
Japan
Prior art keywords
layer
substrate
etching
polymer layer
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15956083A
Other languages
Japanese (ja)
Inventor
Yuichiro Yagishita
祐一郎 柳下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15956083A priority Critical patent/JPS6052026A/en
Publication of JPS6052026A publication Critical patent/JPS6052026A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To form a fine pattern with high accuracy by shaping a polymer layer flattening a stepped section, an intermediate layer, which has ashing resistance better than the polymer layer and can see through the surface of a substrate, and a resist layer on the substrate coated with a thin-film is succession and etching them. CONSTITUTION:A conductor layer 3 is formed on a substrate 1, the surface thereof has stepped sections, through a sputtering method, etc., and a polymer layer 8 flattening the stepped sections is formed on the substrate. A substance, which is degenerated by the irradiation of shortwave ultraviolet rays and the speed of ashing thereof is increased, is used as a material for the polymer layer 8, an intermediate layer 9 consisting of SiO2, which has ashing resistance better than the polymer layer 8 and can see through the surface of the substrate, is shaped on the layer 8, and a mask pattern composed of a photo-resist layer 10 is formed. The resist layer 10 and the intermediate layer 9 are etched and windows are bored, shortwave ultraviolet rays are projected to the whole surface of the substrate, and the window sections are etched by reactive ions, thus forming a thin-film pattern.

Description

【発明の詳細な説明】 (a> 発明の技術分野 本発明は顕著な段差を伴う基板上への微細パターンの形
成方法に関する。 − (b)技術の背景 IC,LSIなど半導体素子の集積度は益々大きくなり
、そわと共に半導体素子は小型化され、従って電極パタ
ーン幅、導体パターン幅も微少化すると共に多層配#構
成をとるため基板の凹凸が増加し半導体素子形成は高度
な技術を必要としている。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a method for forming a fine pattern on a substrate with significant steps. - (b) Background of the technology The degree of integration of semiconductor devices such as ICs and LSIs is Semiconductor devices are getting smaller and larger, and as a result, electrode pattern widths and conductor pattern widths are also getting smaller. At the same time, due to the multilayer structure, the unevenness of the substrate is increasing, and the formation of semiconductor devices requires advanced technology. .

本発明は顕著な段差を伴う基板−Fへ微細パターンを形
成する方法の改良に関するものである。
The present invention relates to an improvement in a method of forming a fine pattern on a substrate-F with a significant step difference.

(cl 従来技術上問題点 基板上に導体或は絶縁物からなる微細パターンを形成す
る方法として薄膜形成技術と写真蝕刻技術(ホトリソグ
ラフィ)(+−が用いられている。
(cl) Problems in the Prior Art Thin film formation technology and photolithography (+-) are used as methods for forming fine patterns made of conductors or insulators on substrates.

すなわち真空蒸着、スパッタリングなどにより金属材料
、非金属材料、絶縁材料などからなる薄膜を形成し、こ
の上にホトレジストを被覆しこれにマスクパターンを投
影露光するか密着露光するかしてホトレジストを選択的
に感光せしめ現像液に対して爵解変の差異を生じさせる
That is, a thin film made of metal, non-metal, insulating material, etc. is formed by vacuum evaporation, sputtering, etc., and then a photoresist is coated on top of the thin film, and a mask pattern is projected onto the thin film or contact exposure is performed to selectively expose the photoresist. It is exposed to light and causes a difference in its resolution with respect to the developer.

こ\でホトレジストには光照射部が現1i1&Nに対し
て可溶となるポジタイプと不溶となるネガクイプとがあ
る0 次に現像処理により部分的に窓あけされた部分に化学エ
ツチング或はドライエツチングを施すことにより基鈑上
の薄膜がエツチングされ、その後マスクして用いたホト
レジストを溶解除去することにより薄膜よりなる微細パ
ターンが形成されるO第1図は凹凸のある基板lの上に
導体パターン2を形成する場合の実施例で、この場合の
基板1はシリコン(Sl)ウェハ上に多層構造をとって
形成された基板面を示している0 すなわち導体としては多結晶シリコン(以後ボ1181
)、アルミニウム(以後AA)などが、また絶縁層とし
ては2酸化硅素(以後Sinりなどの材料が用いられ、
絶縁層を拒て\多層配線が行われること\導体抵抗を減
らすためにポリ81層の厚さとして0.4〜0.5〔μ
m〕がとられていることから、これらの導体パターンが
交叉する位置では顕著な段差をもつ凹凸を生じている。
There are two types of photoresists: positive type, in which the light irradiated area becomes soluble in the present 1i1&N, and negative type, in which the light irradiated area becomes insoluble.Next, chemical etching or dry etching is applied to the areas partially opened by the development process. The thin film on the substrate is etched by etching, and the photoresist used as a mask is then dissolved and removed to form a fine pattern made of the thin film. In this example, the substrate 1 in this case is a substrate surface formed with a multilayer structure on a silicon (Sl) wafer.
), aluminum (hereinafter referred to as AA), and materials such as silicon dioxide (hereinafter referred to as SIN) are used as the insulating layer.
The thickness of the poly 81 layer should be 0.4 to 0.5 [μ] to reduce the conductor resistance and avoid the insulation layer.
m], the positions where these conductor patterns intersect have unevenness with significant steps.

第1図はこのよろな凹凸のある基板1の上にポリSi或
はAZよりなる導体パターン2を形成する場合で囚は断
面図また(B)はパターン形成後の導体パターン2の平
面図である。こ\で従来のよろにf−KWj3の上にホ
トレジスト層(この場合ポジタイプとする)4をスピン
コード法により形成し、同図(4)で示すような段差の
ある部分に直ダして同図(B)に示すような細線パター
ンを形成する場合、露光により感光するホトレジスト層
4の厚さは基@1の突出部5と平坦部6では顕著に異る
ために導体パターン2にくびわ7を生じてしまう。
Figure 1 shows a case where a conductor pattern 2 made of poly-Si or AZ is formed on a substrate 1 with various unevenness, and the figure shows a cross-sectional view, and (B) shows a plan view of the conductor pattern 2 after pattern formation. be. Now, as in the conventional method, a photoresist layer (positive type in this case) 4 is formed on the f-KWj 3 by the spin code method, and it is directly applied to the step part as shown in Figure (4). When forming a thin line pattern as shown in FIG. 7 will occur.

すなわち本実施例の櫂1合はポジレジストであるから露
光部が分解して現像液に対し易溶性となるト がこの露光処理は現像残りが起きないようレジ犬2膜厚
の厚い平坦部6を基準として露光部が充分に感光される
条件で行われる。
In other words, since the paddle 1 in this embodiment is a positive resist, the exposed area decomposes and becomes easily soluble in the developer, but in this exposure process, the resist 2 thick flat area 6 is used to prevent the development from remaining. The exposure is carried out under conditions such that the exposed area is sufficiently exposed.

然しこの条件は基板の突出部5のホトレジスト層4にお
いては感光過度であり、基板面からの反射などによりマ
スク部までも部分的に感光するため導体パターン2にく
びれ7を生ずるこさになる。
However, under this condition, the photoresist layer 4 on the protruding portion 5 of the substrate is overexposed, and even the mask portion is partially exposed due to reflection from the substrate surface, resulting in the formation of a constriction 7 in the conductor pattern 2.

このくびれ7の形成は従来のようにパターン幅が3〔μ
m〕程度の導体パターンに対しては影響は少いがパター
ン幅が1〔μm〕となる今後の微細パターンに対しては
影響が大きい0 さてか\る顕著な段差を伴う基板面への微細パターンの
形成法きしては3層構造をとるドライエツチング法が提
案されている0 第2図(A)〜(ト)はこれによるパターン形成方法を
示すもので、基板lの上に導体層3をスパッタ法などで
形成した後ポリマー層8を厚めに形成して基板の段差に
よる凹凸を無くする同図(A)。
The constriction 7 is formed with a pattern width of 3 [μ] as in the conventional method.
This has little effect on conductor patterns with a pattern width of 1 [μm], but it will have a large effect on future fine patterns with pattern widths of 1 [μm]. A dry etching method that takes a three-layer structure has been proposed as a pattern forming method. Figures 2 (A) to (G) show a pattern forming method using this method. 3 is formed by a sputtering method or the like, and then a polymer layer 8 is formed thicker to eliminate unevenness caused by steps on the substrate.

こ\でポリマーは基mtの凹凸を無くするもので感光性
をもつことは必要条件ではなく透明な高分子であれば何
れでもよい0この理由は基板1とのマスク合わせの点で
有利なためである0本実施例においてはポリマー層8の
塗布厚として2.5〜3〔μm)をとったが、これによ
り基板面の凹凸による段差が0.5〜1(μm〕存在し
ていてもポリマー層8の表面は平坦化する同図(A)。
Here, the polymer is used to eliminate the unevenness of the base mt, and it is not necessary to have photosensitivity, and any transparent polymer may be used.The reason for this is that it is advantageous in terms of mask alignment with the substrate 1. 0 In this example, the coating thickness of the polymer layer 8 was set at 2.5 to 3 [μm], but this means that even if there is a step difference of 0.5 to 1 (μm) due to unevenness on the substrate surface, The surface of the polymer layer 8 is planarized in the same figure (A).

次にこの上にスパッタ処理などにより中間層9を約t 
o o o〔にの厚さに形成する同図(Bl。
Next, an intermediate layer 9 of approximately t
The same figure (Bl.

この中間層9はアッシング(灰化)処理を行う際のマス
クとして作用するもので、この必要条件は反射率の少い
材料からなることおよびマスク合わせを容易にするため
薄く形成することが好ましET)Q すなわち基板1の表面を目視し得る状態でマスクの位置
合わせを行うには導体層3よりも反射率の少い材料で形
成する必要があり、また後で行うアッシング処理に際し
て耐蝕性のあるものでなければならない。この条件を満
す材料さして導体層3がポリStからなる場合には51
02が、またAiからなる場合には81或は5insが
中間層9の使用材料として適当である。
This intermediate layer 9 acts as a mask when performing ashing (ashing) processing, and the necessary conditions for this are that it be made of a material with low reflectance and that it be formed thinly to facilitate mask alignment. ET)Q In other words, in order to align the mask while the surface of the substrate 1 is visible, it is necessary to form the conductor layer 3 with a material that has a lower reflectance than the conductor layer 3, and it is necessary to use a material that is corrosion resistant during the ashing process that will be performed later. It has to be something. When the conductor layer 3 is made of polySt, the material that satisfies this condition is 51
If 02 is also made of Ai, 81 or 5ins is suitable as the material used for the intermediate layer 9.

次にこの上にホトレジスト層10からなるマスクを形成
し同図(Cl、 リアクティブイオンエツチングなどの
異方性ドライエツチングを施すことにより、中間11j
9をエツチングし同図01更にポリマー層8と導体層3
.!−を選択的にエツチングして微細パターンが形成さ
れる同図■)。このように3層庫造をとるドライエツチ
ング法をとる場合は垂直方向にエツチングが進行する異
方性エツチングを使用するため導体パターンのくびれな
どの発生はないが、ポリマー層8が厚いためエツチング
に時間を要し、またサイドエツチングが起り易い0(d
) 発明の目的 本発明の目的は顕著な段差をもつ基板上に微細パターン
を形成する場合にパターンにサイドエツチングを生ぜず
またエツチング速度の大きなパターン形成法を提供する
ことを目的とする。
Next, a mask made of a photoresist layer 10 is formed on this layer, and anisotropic dry etching such as Cl, reactive ion etching is applied to the intermediate layer 11j.
9 is etched, and the same figure 01 is further etched with polymer layer 8 and conductor layer 3.
.. ! (2) in the same figure in which a fine pattern is formed by selectively etching -. When using a dry etching method with a three-layer structure like this, anisotropic etching is used in which etching progresses in the vertical direction, so there is no constriction of the conductor pattern, but since the polymer layer 8 is thick, etching is difficult. 0(d), which takes time and tends to cause side etching.
OBJECTS OF THE INVENTION It is an object of the present invention to provide a pattern forming method that does not cause side etching of the pattern and has a high etching speed when forming a fine pattern on a substrate having a significant step difference.

(e) 発明の構成 本発明の目的は、表面に段差を伴う基板上に薄膜よりな
る微細パターンを形成する際薄膜を被覆した基板上に段
差を平坦化するポリマー層、該ポリマー層よりも耐アツ
シング性が優れ且つ基板面を透視可能な中間層、レジス
ト層と11m次形成し、レジスト層および中間層を選択
エツチングして微細パターン形成部を除き窓開を行った
後基板全面に短波長の紫外線を照射し次にリアクティブ
イオンエツチングを行い、該窓開は部を薄膜部までエツ
チングして薄膜パターンを形成する方法をとることによ
り達成することができる〇 本発明はポリマー層8の材料として短波長の紫外線照射
により変質してアッシング速度(灰化速度)の高くなる
ものを用い、第2図0)で示した中間層9のエツチング
後に基板全面に紫外線照射を行い、その後従来と同様に
リアクティブイオンエツチングを行うことによりエツチ
ング速度が犬で月つ精度の高いパターン形成を行うもの
である。
(e) Structure of the Invention An object of the present invention is to provide a polymer layer that flattens the steps on a substrate coated with a thin film when forming a fine pattern made of a thin film on a substrate with steps on the surface, and a polymer layer that is more durable than the polymer layer. An intermediate layer and a resist layer, which have excellent ashing properties and can be seen through the substrate surface, are formed in 11 m order, and the resist layer and intermediate layer are selectively etched to remove the fine pattern forming area and a window is opened. This can be achieved by irradiating ultraviolet rays and then performing reactive ion etching to form a thin film pattern by etching the part to the thin film part. After etching the intermediate layer 9 shown in Fig. 2 (0), the entire surface of the substrate is irradiated with ultraviolet rays, using a material that changes in quality when exposed to short-wavelength ultraviolet irradiation and has a high ashing rate (ashing rate). By performing reactive ion etching, a highly accurate pattern can be formed with an extremely fast etching speed.

発明者は通常のポジレジストは勿論ポリイミドなどのポ
リマー層についても紫外線特に短波長の紫外線(Dee
p Ultra Violet Ray波長220〜3
00(nm))を照射するとりアクティブイオンエツチ
ング法によるアッシング速度が顕著に増加することを見
出した。
The inventor discovered that not only ordinary positive resists but also polymer layers such as polyimide can be treated with ultraviolet rays, especially short wavelength ultraviolet rays (Dee
p Ultra Violet Ray wavelength 220~3
It has been found that the ashing rate by active ion etching method increases significantly when irradiated with 00 (nm)).

すなわちポジレジストの場合と同様に紫外線照射により
高分子を構成するラジカルの脱離などが進行し安定な構
造より不安定な構造へと変質する0才た本発明に関連し
て使用されるリアクティブイオンエツチングはスパッタ
エツチングさも呼ばれるもので、平行平板型の電極の一
方で13.56(MHz)の高周板電源と結合したカソ
ードの上に被エツチング処理物を置き、陰極降下電圧に
よりガスプラズマ内の正イオンがカソード上の被エツチ
ング処理物に衝撃してスパッタエツチングが行われるも
ので電極面と直角方向に非等方エツチングが進行する特
徴がある0 以後実施例について本発明を説明する。
In other words, similar to the case of positive resists, UV irradiation causes the desorption of radicals constituting the polymer, resulting in a change from a stable structure to an unstable structure. Ion etching is also called sputter etching, and the object to be etched is placed on a cathode that is connected to a 13.56 (MHz) high-frequency plate power supply on one side of parallel plate electrodes, and the material to be etched is placed in a gas plasma using a cathode drop voltage. Sputter etching is carried out by the impact of positive ions on the object to be etched on the cathode, and the present invention is characterized in that anisotropic etching progresses in a direction perpendicular to the electrode surface.The present invention will now be described with reference to Examples.

第2図(へのポリマーrf#8としては市販のポジレジ
スト(OFPR−800)を厚さ2.5〜3(/1rn
)に形成し、この上に設ける中間層9として厚さ約10
00IAlのSin、層を形成し、この上にホトレジス
ト層10からなるマスクパターンを形成し第2図(Oで
示す構造とする0 次にCHFIガスを媒質としてリアクティブイオンエツ
チングを行い第2図0で示す構造とする0こ\までは従
来の方法と違わない0 次に波長220(nm)で照度10 (mw/(m” 
)の紫外線を30〔秒〕〜1〔分〕に互ってポリマー層
8を照射後酸素(0バガスを媒質としてリアクティブイ
オンエツチングを行い、第2図(ト)で示す状態にまで
エツチングする。
As polymer rf #8 in Figure 2, a commercially available positive resist (OFPR-800) was used with a thickness of 2.5 to 3 (/1rn).
) with a thickness of approximately 10 mm as the intermediate layer 9 provided thereon.
A layer of Sin of 00IAl is formed, and a mask pattern consisting of a photoresist layer 10 is formed on this to create a structure shown in FIG. The structure shown is the same as the conventional method up to 0. Next, the wavelength is 220 (nm) and the illuminance is 10 (mw/(m)
) After irradiating the polymer layer 8 with ultraviolet rays of 30 [seconds] to 1 [minute] alternately, reactive ion etching is performed using oxygen (zero bagasse) as a medium, and etching is performed to the state shown in Figure 2 (G). .

こ\でO,ガスを媒質としてポリマーをドライエツチン
グする場合はポリマーの主鎖が炭素からできているため
適状の条件下では安定なポリマーも0.ガスプラズマ中
では容易に主鎖が分断され炭酸ガス(COx)と水蒸気
(Ht O)となって気化するためアッシング(灰化)
と云われるが、本発明に係る紫外線照射を施したポリマ
ーは照射部に変質が生じているためエツチング速度が6
000〜8000(A/分〕と従来の4000〜50.
00(A/分)と較べてはるかに大きくまた紫外線は基
板面と直角に照射されポリマー8が明瞭な境界を作って
変質しているのでリアクティブイオンエツチングの直進
性と相まって、ポリマー層8が厚いにも拘わらず精度よ
く導体パターン3が形成される。
When dry etching a polymer using O and gas as a medium, the main chain of the polymer is made of carbon, so even stable polymers may be 0. In gas plasma, the main chain is easily broken and vaporized into carbon dioxide (COx) and water vapor (HtO), resulting in ashing.
However, the polymer irradiated with ultraviolet rays according to the present invention has an etching rate of 6 because the irradiated area is altered.
000-8000 (A/min) and the conventional 4000-50.
00 (A/min), and since the ultraviolet rays are irradiated perpendicularly to the substrate surface, the polymer layer 8 is altered by creating a clear boundary, so combined with the straightness of reactive ion etching, the polymer layer 8 Although the conductor pattern 3 is thick, it is formed with high accuracy.

(X)発明の効果 本発明は3j−構造のエツチングにおいては微細パター
ンが形成できるもの一エツチングに時間を要し、またポ
リマー層の厚さが厚いため精度が低下する傾向をもつの
に対し1本発明の実施によりこれらの欠点が改良され、
微細パターンが精度よく形成できるようになった◎
(X) Effects of the Invention The present invention is capable of forming fine patterns in etching of 3J-structures, but etching takes time, and the accuracy tends to decrease due to the thick polymer layer.1 Implementation of the present invention ameliorates these drawbacks,
Fine patterns can now be formed with high precision◎

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の微細パターン形成法の説明図で、(4)
は断面図才た03)は微細パターンの平面図、第2図(
4)〜(ト)は本発明に係る3層構造のエツチング方法
による工程を説明する断面図である0図において、lは
基板、2は導体パターン、3は導体層、4.10はホト
レジスト層、8はポリマー層、9は中間層。 11−
Figure 1 is an explanatory diagram of the conventional fine pattern formation method, (4)
03) is a cross-sectional view, and Figure 2 (03) is a plan view of the fine pattern.
4) to (g) are cross-sectional views illustrating the steps of the etching method for a three-layer structure according to the present invention. , 8 is a polymer layer, and 9 is an intermediate layer. 11-

Claims (1)

【特許請求の範囲】[Claims] 表面に段差を伴う基板上に薄膜よりなる微細パターンを
形成する際、rfJi膜を被覆した基板上に段差を平坦
化するポリマー層、該ポリマー層よりも耐アツシング性
が優れ且つ基板面を透視可能な中間層、レジスト層と順
次形成し、レジスト層および中間1−を選択エツチング
して微細パターン形成部を除き窓開を行った後基根全面
に短波長の紫外線を照射し次にリアクティブイオンエツ
チングを行(1)、該窓開は部を薄@部才でエツチング
して薄膜パターンを形成することを特徴とする微細パタ
ーンの形成方法。
When forming a fine pattern made of a thin film on a substrate with steps on the surface, a polymer layer is used to flatten the steps on the substrate coated with an rfJi film, which has better ashes resistance than the polymer layer and allows the substrate surface to be seen through. The intermediate layer and resist layer are sequentially formed, and the resist layer and intermediate layer 1- are selectively etched to remove the fine pattern forming area and a window is opened.The entire surface of the base is irradiated with short wavelength ultraviolet rays, and then reactive ions are applied. A method for forming a fine pattern, characterized in that etching is performed (1), and a thin film pattern is formed by etching the window opening in a thin manner.
JP15956083A 1983-08-31 1983-08-31 Formation of fine pattern Pending JPS6052026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15956083A JPS6052026A (en) 1983-08-31 1983-08-31 Formation of fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15956083A JPS6052026A (en) 1983-08-31 1983-08-31 Formation of fine pattern

Publications (1)

Publication Number Publication Date
JPS6052026A true JPS6052026A (en) 1985-03-23

Family

ID=15696400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15956083A Pending JPS6052026A (en) 1983-08-31 1983-08-31 Formation of fine pattern

Country Status (1)

Country Link
JP (1) JPS6052026A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186338A (en) * 1981-05-11 1982-11-16 Mitsubishi Electric Corp Forming method for fine pattern
JPS5898931A (en) * 1981-12-08 1983-06-13 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186338A (en) * 1981-05-11 1982-11-16 Mitsubishi Electric Corp Forming method for fine pattern
JPS5898931A (en) * 1981-12-08 1983-06-13 Mitsubishi Electric Corp Manufacture of semiconductor device

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