JPS61128524A - Forming method of fine pattern - Google Patents

Forming method of fine pattern

Info

Publication number
JPS61128524A
JPS61128524A JP25073884A JP25073884A JPS61128524A JP S61128524 A JPS61128524 A JP S61128524A JP 25073884 A JP25073884 A JP 25073884A JP 25073884 A JP25073884 A JP 25073884A JP S61128524 A JPS61128524 A JP S61128524A
Authority
JP
Japan
Prior art keywords
pattern
resist
film
reactive ion
fine pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25073884A
Other languages
Japanese (ja)
Inventor
Shuichi Matsuda
修一 松田
Kazuhiro Tanaka
和裕 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP25073884A priority Critical patent/JPS61128524A/en
Publication of JPS61128524A publication Critical patent/JPS61128524A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a fine pattern with high precision by conducting the reactive ion etching of argon on the removal of scum. CONSTITUTION:A resist 3 for electron beams is applied onto a plate in which a metallic thin-film 2 is applied onto a glass substrate 1, and pre-baked, and electron beams are projected in response to a desired pattern. A resist pattern 4 is obtained through irradiation and development, and scum is removed through plasma irradiation at 21Pa, the flow rate of 70sec.cm of Ar gas 8 and output power of 300W by using a reactive ion etching device, thus shaping the pattern. The surface of the resist is processed by Ar ions at that time. A Cr thin-film is etched by mixed plasma of CCl4+O2 at 35Pa by employing a dry etching device, and the resst is removed, thus acquiring a metallic chromium thin-film pattern.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、微細パターン形成方法に関し、特にその形成
に際し半導体ウェハあるいはマスク等の基板上に形成さ
れたレジストを現像してレジストパターンを形成した後
、スカム除去をするようにしたものに関するものである
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for forming a fine pattern, and in particular, a method for forming a resist pattern by developing a resist formed on a substrate such as a semiconductor wafer or a mask. The second one concerns something that removes scum.

〔従来の技術・〕[Conventional technology]

半導体集積回路等の半導体装置を製造する際、写真製版
工程は必要不可欠のものである。近年、微細パターン形
成においては電子ビーム露光装置又はXa露光装置によ
り該微細、パターンが高精度に作成されつつある。ここ
で従来の微細パターン形成方法の一例を第2図を参照し
て説明する。
A photolithography process is essential when manufacturing semiconductor devices such as semiconductor integrated circuits. In recent years, in forming fine patterns, electron beam exposure equipment or Xa exposure equipment has been used to create fine patterns with high precision. An example of a conventional fine pattern forming method will now be described with reference to FIG. 2.

まず最初に、第2図(alに示すように、ガラス基板1
上に金属薄膜22例えばCrを被着させたプレートに、
電子ビーム又は光用のレジスト31例えばAZ−135
0を約5ooo人の厚さに被着させ、80℃で30分間
プリベークを行なう。
First, as shown in Figure 2 (al), a glass substrate 1
A plate on which a metal thin film 22, for example Cr, is deposited,
Electron beam or photoresist 31 such as AZ-135
0 to a thickness of about 5 mm and prebaked at 80° C. for 30 minutes.

次に第2図(b)に示すように、電子ビームを2×10
  C/adのドーズ量にて所望のパターンに対応して
照射する。その後、第2図(C1に示すようにAZ−1
350の現像液で現像を行ない、レジストパターン4を
得る。その後リンス、乾燥して第2図(dlに示すよう
に、レジストパターン4にウェット空気のプラズマ7を
I Torr 、 300 Wで2.2分間照射してス
カム除去を行ない、パターン整形し、このレジストパタ
ーン4をマスクとして第2図(e)に示すように金属薄
膜2をエツチングする。最後に、第2図(f)に糸すよ
うにレジストパターン4を除去して金属薄膜パターン5
を得る。
Next, as shown in Figure 2(b), the electron beam is
Irradiation is performed at a dose of C/ad corresponding to a desired pattern. Then, as shown in Figure 2 (C1), AZ-1
A resist pattern 4 is obtained by developing with a No. 350 developer. Thereafter, the resist pattern 4 is rinsed and dried, and as shown in FIG. Using the pattern 4 as a mask, the metal thin film 2 is etched as shown in FIG. 2(e).Finally, the resist pattern 4 is removed as shown in FIG. 2(f) to form the metal thin film pattern 5.
get.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかるに上記従来の微細パターン形成方法では、スカム
工程としてはウェット空気によるプラズマエツチングを
行なっており、これは等方性の強いプラズマエツチング
であるため膜減りやサイドエッチが起こりやすいなどの
欠点等があった。
However, in the conventional fine pattern forming method described above, plasma etching using wet air is performed as the scum process, and since this is a highly isotropic plasma etching, it has drawbacks such as film thinning and side etching. Ta.

本発明は、上記のような従来のものの欠点を除去するた
めになされたもので、膜減りやサイドエッチを少なくで
きる微細パターン形成方法を提供することを目的として
いる。
The present invention was made to eliminate the above-mentioned drawbacks of the conventional methods, and an object of the present invention is to provide a fine pattern forming method that can reduce film thinning and side etching.

〔問題点を解決するための手段〕 この発明に係る微細パターン形成方法は、レジストパタ
ーンを形成し、その後スカム除去する際に、反応性イオ
ンエツチング装置(RIE)を用いてアルゴンイオンプ
ラズマを照射してパターン整形するものである。
[Means for Solving the Problems] The fine pattern forming method according to the present invention involves irradiating argon ion plasma using a reactive ion etching device (RIE) when forming a resist pattern and then removing scum. It is used to shape the pattern.

〔作用〕[Effect]

この発明においては、レジストパターンの整形をアルゴ
ンイオンプラズマにて行うから、精度のよい微細パター
ンが形成される。
In this invention, since the resist pattern is shaped using argon ion plasma, a fine pattern with high precision is formed.

〔実施例〕〔Example〕

以下、本発明の一実施例による微細パターン加工方法を
第1図を用いて説明する。
Hereinafter, a fine pattern processing method according to an embodiment of the present invention will be explained with reference to FIG.

第1図(a)に示すように、ガラス基板1上に金属S膜
21例えばCrを約800人の厚さに被着したプレート
上に、電子ビーム用レジスト39例えばAZ−1350
を約5000人の厚さに被着させる。
As shown in FIG. 1(a), an electron beam resist 39 such as AZ-1350 is placed on a glass substrate 1 on which a metal S film 21 such as Cr is deposited to a thickness of approximately 800 mm.
is applied to a thickness of about 5,000 people.

約80℃で30分間プリベータを行なった後、第1図づ (blに示すように、電子ビームを2X10  C/c
n!のドーズ量にて所望のパターンに対応して照射する
After pre-heating at about 80°C for 30 minutes, the electron beam was
n! The irradiation is performed at a dose of 200 nm to correspond to the desired pattern.

照射後第1図(0)に示すように、AZ−1350の現
像液で現像を行ないレジストパターン4を得る。
After the irradiation, as shown in FIG. 1(0), development is performed with an AZ-1350 developer to obtain a resist pattern 4.

次に第1図(d)に示すように反応性イオンエツチング
装置を用いて、21Pa、Arガス8の流量70scc
a+、出力電力300Wでもってプラズマ照射を行なっ
てスカム除去をしてパターン整形する。この際、レジス
ト表面はArイオンで加工されることになる。次に、第
1図(Q)に示すようにドライエツチング装置を用い、
35Pa、CCl4+02の混合プラズマで約300W
の出力にてCr薄膜をエツチングし、第1図(f)に示
すようにレジスト除去後金属クロム薄膜パターン5を得
る。このようにして得られたパターンはシャープなエツ
ジで、サイドエッチの少ない微細パターンであった。
Next, as shown in FIG. 1(d), using a reactive ion etching device, a flow rate of 70 sc of Ar gas 8 was applied at 21 Pa.
a+, plasma irradiation is performed with an output power of 300 W to remove scum and shape the pattern. At this time, the resist surface will be processed with Ar ions. Next, as shown in FIG. 1 (Q), using a dry etching device,
Approximately 300W with 35Pa, CCl4+02 mixed plasma
The Cr thin film is etched using the output of 1, and after removing the resist, a metallic chromium thin film pattern 5 is obtained as shown in FIG. 1(f). The pattern thus obtained was a fine pattern with sharp edges and little side etching.

このように本実施例では、従来と異なり、スカム除去を
、異方性が強(、レジストを、02やウェット空気のプ
ラズマはどはサイドエッチすることのないアルゴンを用
いた反応性イオンエ・ノチングにより行なうようにした
ので、膜減りが大幅に少なくなる。また同時にレジスト
表面の加工がアルゴンイオンプラズマで行なわれるため
、該アルゴンプラズマ処理をしていないものに比ベレジ
ストの耐ドライエツチ性を太き(向上できる。
In this way, unlike the conventional method, scum removal was carried out by reactive ion etching using argon, which has strong anisotropy (resist) and does not side-etch the plasma of 02 or wet air. Since the resist surface is processed by argon ion plasma, the dry etch resistance of the resist is improved (compared to those not subjected to argon plasma treatment). You can improve.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明に係る微細パターン形成方法によ
れば、スカム除去を行なう際に、アルゴンの反応性イオ
ンエ・ノチングを行なうようにしたので、レジストの膜
減りを少なくでき、かつレジストの表面が加工されて耐
ドライエツチ性を向上でき、さらにサイドエッチも少な
い精度の良い微細パターンを形成できる効果がある。
As described above, according to the fine pattern forming method according to the present invention, since reactive ion etching with argon is performed when removing scum, the loss of the resist film can be reduced, and the resist surface This has the effect of improving dry etch resistance and forming highly accurate fine patterns with less side etching.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(flは本発明の一実施例による微細パ
ターン形成方法を示す工程断面図、第2図(aJ〜(f
)は従来方法の一例を示す工程断面図である。 1・・・ガラス基板、2・・・金属クロム(薄膜)、3
・・・電子ビーム用レジスト(レジスト膜)、4・・・
レジストパターン、6・・・電子ビーム(放射線)、8
・・・アルゴンの反応性イオンプラズマ。 なお図中、同一符号は同−又は相当部分を示す。
FIGS. 1(a) to (fl are process sectional views showing a fine pattern forming method according to an embodiment of the present invention, and FIGS. 2(a) to (f
) is a process sectional view showing an example of a conventional method. 1...Glass substrate, 2...Metal chromium (thin film), 3
...Electron beam resist (resist film), 4...
Resist pattern, 6... Electron beam (radiation), 8
... Argon reactive ion plasma. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に形成された薄膜にレジスト膜を塗布し、
このレジスト膜に放射線等を選択的に照射してパターン
ニングし、これを現像してレジストパターンを形成し、
該レジストパターンに反応性イオンエッチング装置を用
いてアルゴンの反応性イオンプラズマでスカム除去を行
いパターン整形することを特徴とする微細パターン形成
方法。
(1) Applying a resist film to the thin film formed on the substrate,
This resist film is patterned by selectively irradiating radiation etc., and this is developed to form a resist pattern,
A method for forming a fine pattern, which comprises using a reactive ion etching device to remove scum from the resist pattern with reactive ion plasma of argon and shaping the resist pattern.
JP25073884A 1984-11-27 1984-11-27 Forming method of fine pattern Pending JPS61128524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25073884A JPS61128524A (en) 1984-11-27 1984-11-27 Forming method of fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25073884A JPS61128524A (en) 1984-11-27 1984-11-27 Forming method of fine pattern

Publications (1)

Publication Number Publication Date
JPS61128524A true JPS61128524A (en) 1986-06-16

Family

ID=17212302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25073884A Pending JPS61128524A (en) 1984-11-27 1984-11-27 Forming method of fine pattern

Country Status (1)

Country Link
JP (1) JPS61128524A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679499A (en) * 1995-02-21 1997-10-21 Nec Corporation Method for forming photo mask for use in fabricating semiconductor device
JP2003332073A (en) * 2002-03-07 2003-11-21 Semiconductor Energy Lab Co Ltd Light emitting device and its manufacturing method
US8968822B2 (en) 2002-03-07 2015-03-03 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method of fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679499A (en) * 1995-02-21 1997-10-21 Nec Corporation Method for forming photo mask for use in fabricating semiconductor device
JP2003332073A (en) * 2002-03-07 2003-11-21 Semiconductor Energy Lab Co Ltd Light emitting device and its manufacturing method
US8968822B2 (en) 2002-03-07 2015-03-03 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method of fabricating the same
US10170724B2 (en) 2002-03-07 2019-01-01 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method of fabricating the same
US11005062B2 (en) 2002-03-07 2021-05-11 Semiconductor Energy Laboratory Co., Ltd. Light emitting apparatus and method of fabricating the same

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