JPS5895843A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5895843A JPS5895843A JP19617681A JP19617681A JPS5895843A JP S5895843 A JPS5895843 A JP S5895843A JP 19617681 A JP19617681 A JP 19617681A JP 19617681 A JP19617681 A JP 19617681A JP S5895843 A JPS5895843 A JP S5895843A
- Authority
- JP
- Japan
- Prior art keywords
- film
- passivation film
- semiconductor device
- photo
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特に半導体基
板表面を保護するための絶縁膜(パッシベーション膜)
を有する半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to an insulating film (passivation film) for protecting the surface of a semiconductor substrate.
The present invention relates to a method of manufacturing a semiconductor device having the following.
半導体装置において、所望の能動領域及びそれらを外部
回路に接続するための配線用金属層を形成した後、半導
体基板表面を保護するため、半導体基板表面全体に絶縁
膜(パッシベーションII)を形成する構成が良く知ら
れている。In a semiconductor device, after forming desired active regions and wiring metal layers for connecting them to an external circuit, an insulating film (passivation II) is formed over the entire surface of the semiconductor substrate in order to protect the surface of the semiconductor substrate. is well known.
コ17)パッシベーション膜を有する半導体装置におい
ては、半導体装置を外部回路に接続するために、上記の
パッシベーション膜の所望の領域のみパッシベーション
膜を完全に除去することが重要となる。この所望の領域
内のパッシベーション膜の除去が不完全であれば、ボン
ディングが不完全となり、ひいては半導体装置の信頼性
の低下の要因となる〇
従来より半導体装置の配線用金属材料として、高周波ト
ランジスタ等高信頼度が侠求されるものについては、金
が採用されている0金を電極として使用する場合には、
金の半導体への拡散を防止するために障壁金属膜を必要
とし、またこの金属層とパッシベーション膜との密着性
を良くするための接着性金属層をも必要とするので、多
層構造の電極となるのが普通である。(17) In a semiconductor device having a passivation film, in order to connect the semiconductor device to an external circuit, it is important to completely remove the passivation film only from a desired region of the passivation film. If the removal of the passivation film within the desired region is incomplete, bonding will be incomplete and this will eventually lead to a decrease in the reliability of the semiconductor device. For products that require high reliability, if gold is used as the electrode,
A barrier metal film is required to prevent gold from diffusing into the semiconductor, and an adhesive metal layer is also required to improve the adhesion between this metal layer and the passivation film. It is normal.
この多層構造の金電極を有する学導体基板上に上記パッ
シベーション膜を付着させ、所望の領域のみそのパッシ
ベーション膜を除去しようとする場合には最上層の金が
、種々のパッシベーション膜エツチング液などの薬品に
対して安定であるので、完全にパッシベーション膜の所
望領域が除去されたか、どうかを判定することが困難で
、ややもすればパッシベーション膜の1−バーエツチン
グを惹起し、所望の領域よりも大きい開孔部を生じさせ
ることがあった。特に、高周波トランジスタなど微細パ
ターンを有する一半導体装置では、必然的にこの開孔部
の大きさも制限され、この開孔部オーバーエツチングは
半導体装置全体の信頼性を低下させる一因ともなってい
た・、
この発明は以上のような点に鑑みてなされたもノテ、パ
ッシベーション膜の所望部分の除去が完了したかどうか
をモニタする手段を用いることにヨッテ、パッシベーシ
ョン膜の所望領域のみ全完全に除去することができ、信
頼性の高い半導体装置が得られる製造方法を提供するこ
とを目的としている。When the passivation film is deposited on a conductor substrate having a multilayered gold electrode and the passivation film is to be removed only from a desired area, the top layer of gold can be removed using various chemicals such as passivation film etching solutions. It is difficult to judge whether the desired area of the passivation film has been completely removed, and if the passivation film is stable, it may cause 1-bar etching of the passivation film, and the openings larger than the desired area may be removed. Sometimes it caused. In particular, in a semiconductor device having a fine pattern such as a high-frequency transistor, the size of the opening is inevitably limited, and over-etching of the opening becomes a factor in reducing the reliability of the entire semiconductor device. The present invention has been made in view of the above points, and it is possible to completely remove only the desired area of the passivation film by using means for monitoring whether the removal of the desired portion of the passivation film is completed. The purpose of the present invention is to provide a manufacturing method that allows a highly reliable semiconductor device to be obtained.
以下、この発明を高周波用シリコン拡散形プレーナトラ
ンジスタ素子の製造に適用した場合を例にとって、図面
に従って説明する。第1図〜第10図はこの発明の上述
の実施例の各工程段階における状態を示す断面図である
〇
第1図は通常の方法で、コレクタ領域を構成する基板(
1)の一方の主面の一部にベース領域(2)を形成し、
更にその一部にエミッタ領域(3)を形成し能動領域と
し、上記主−全面に酸化シリコン層(4)を形成し、こ
の酸化シリコン層(4)にベース窓(2a)およびエミ
ツタ窓(3a)を形成した状態を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings, taking as an example a case in which the present invention is applied to the manufacture of a silicon diffused planar transistor element for high frequency use. 1 to 10 are cross-sectional views showing the state of each process step in the above-described embodiment of the present invention. FIG. 1 shows a substrate constituting the collector region (
Forming a base region (2) on a part of one main surface of 1),
Further, an emitter region (3) is formed in a part of the active region, a silicon oxide layer (4) is formed on the main surface, and a base window (2a) and an emitter window (3a) are formed on this silicon oxide layer (4). ) is formed.
第2図はこれも通常の方法で、エミツタ窓(3a)およ
びベース窓(2a)に低抵抗のオーミックコンタクトを
得るために白金シリサイド層(5)を形成し、同じく通
常の方法で、所望の形状をなし、接着性金属層としての
チタン層(6)と、障壁金属層としての白金層(7)お
よび最上部金属層としての金層(8)からなる配線用金
属層(9)を選択的に形成した状態を示す。FIG. 2 shows that a platinum silicide layer (5) is formed on the emitter window (3a) and the base window (2a) to obtain a low-resistance ohmic contact, also using the usual method. A metal layer (9) for wiring is selected, which has a shape and consists of a titanium layer (6) as an adhesive metal layer, a platinum layer (7) as a barrier metal layer and a gold layer (8) as a top metal layer. This shows the state in which it was formed.
以下、この発明の要点の工程に移る。第3図は第2図の
状態の半導体基板の上面にホトレジスト膜Q(Iを付着
させ、通常の写真製版技術を用いてホトレジスト開孔部
(11)を能動領域を外れた部分の酸化シリコン層(4
)の上に有するホトレジストパターンを形成した状態を
示す。Hereinafter, we will move on to the essential steps of this invention. Figure 3 shows that a photoresist film Q (I) is deposited on the upper surface of the semiconductor substrate in the state shown in Figure 2, and the photoresist openings (11) are formed in the silicon oxide layer outside the active area using ordinary photolithography. (4
) shows a state in which a photoresist pattern is formed on top of the photoresist pattern.
第4図は開孔部(11)内を含めてホトレジスト膜11
10の上全面に蒸着、スパッタリングなどの方法によっ
てアルミニウムXOaを形成した状態を示す。Figure 4 shows the photoresist film 11 including the inside of the opening (11).
A state in which aluminum XOa is formed on the entire upper surface of 10 by a method such as vapor deposition or sputtering is shown.
つづいて、第5図はホトレジスト膜QOを溶剤、例えば
アセ′)ンを用いて溶かすとともに、ホトレジスト膜0
)上に付着していたアルミニウム層Hをもあわせて半導
体基板から剥離させ、ホトレジスト膜を介せずに酸化シ
リコン層(4)の上に付着させていた部分〔開孔部(1
N)に対応する部分〕のみを残存させた状態を示す。こ
の残存アルミニウム層が、この発明の要点をなすモニタ
一部0罎である。Continuing on, FIG. 5 shows that the photoresist film QO is dissolved using a solvent such as acetone, and the photoresist film 0 is dissolved.
) was also peeled off from the semiconductor substrate, and the portion that had been adhered to the silicon oxide layer (4) without the photoresist film [opening area (1
The state in which only the portion corresponding to N) remains is shown. This remaining aluminum layer is part of the monitor, which is the key point of this invention.
第6図は、更にモニタ一部−の上を含めて第5図の状態
の半導体基板上全体に例えばスパッタリングによって酸
化シリコンなどからなるパッシベーション膜(141を
形成した状態を示−す。FIG. 6 further shows a state in which a passivation film (141) made of silicon oxide or the like is formed by sputtering, for example, over the entire semiconductor substrate in the state shown in FIG. 5, including a portion of the monitor.
次に、第7図はこのパッシベーションat+<の上に、
この実施例の目的とする外部回路との接続のためにバッ
ジ゛ベーション膜(I4)を除去すべき部位に対応する
能動領域上の部分およびモニタ一部−の直上部に開孔を
有するホトレジスト膜0句を形成した状態を示す。Next, in Fig. 7, on top of this passivation at+<,
A photoresist film having openings directly above the active region and part of the monitor corresponding to the part where the badging film (I4) is to be removed for connection with an external circuit, which is the purpose of this example. Indicates the state in which 0 phrases have been formed.
第8図はンツ酸とフン化アンモニウム水溶液との混合液
(例えば答槓比5:lの→で上記ホトレシスト膜019
をマスクとして、例えば酸化シリコンからなるパッシベ
ーション膜C14)をエツチングし、ホトレジスト膜彌
の開孔に対応する部分を選択的に、しかも完全に除去し
た状態を示す。 Hはエミッタ接続用開孔、0ηはベー
ス′接続用開孔でめる0第9図は、その後に塩酸などの
エツチング液でアルミニウムからなるモニタ一部Nを除
去した状態を示す。FIG. 8 shows the above photoresist film 019 in which a mixed solution of nitrous acid and ammonium fluoride aqueous solution (for example, a reaction ratio of 5:1) is used.
The passivation film C14) made of silicon oxide, for example, is etched using the mask as a mask, and the portions corresponding to the openings in the photoresist film are selectively and completely removed. H is the opening for connecting the emitter, and 0η is the opening for connecting the base. 0 FIG. 9 shows a state in which a portion of the monitor made of aluminum N was subsequently removed using an etching solution such as hydrochloric acid.
この実施例の要点は、この段階でモニタ一部01が完全
に除去されるか否かをもってパッシベーション膜幀の所
望の領域が完全に除去されたか否かをモニタリングでき
るという点にある。すなわち、第8図の段階において、
パッシベーション膜onの除去が不完全であれば、モニ
タ一部0萄の上にもパッシベーション膜(14+が残存
していることになり、塩酸などのエツチング液でアルミ
ニウムからなるモニタ一部01をエツチングしようとし
ても、エツチング液がアルミニウムに直接接触しないの
で、第9図のようにモニタ一部(11が除去されること
がない。換言すれば、モニタ一部晴がエツチング除去さ
れることをもって、パッシベーション膜04)の除去が
確認できるのである。しかも、エミッタ接続用開孔θ呻
およびベース接続用開孔(17)には金層(8)が露出
しそいるので、このアルミニウムのエツチング液では何
の影−も受けない。The point of this embodiment is that it is possible to monitor whether a desired area of the passivation film has been completely removed by checking whether the monitor portion 01 is completely removed at this stage. That is, at the stage shown in Figure 8,
If the removal of the passivation film ON is incomplete, this means that the passivation film (14+) remains on the monitor part 0, so let's etch the monitor part 01 made of aluminum with an etching solution such as hydrochloric acid. However, since the etching solution does not come into direct contact with the aluminum, a portion of the monitor (11) is not removed as shown in FIG. 04) can be confirmed to have been removed.Moreover, since the gold layer (8) is likely to be exposed in the emitter connection hole θ and the base connection hole (17), this aluminum etching solution will not cause any effect. - I also don't accept it.
さて、第1θ図は、ホトレジスト膜a荀を除去して、パ
ッシベーション膜瑣への外部回路の接続用の開孔作業が
完了した状態を示す。エミッタ接続用開孔Hおよびベー
ス接続用開孔07)にはともに金層(8)が露出してい
る。Now, FIG. 1θ shows a state in which the photoresist film a has been removed and the work of opening a hole for connection of an external circuit to the passivation film 4 has been completed. The gold layer (8) is exposed in both the emitter connection hole H and the base connection hole 07).
M10図以降は裏面ラッピング、スクライビング、プレ
イキングなど周知の方法によって、素子単体として切り
出し、半導体装置用パッケージに装着し、所望の性能を
有する半導体装置を得ることができる。After the M10 diagram, the element can be cut out as a single element by well-known methods such as back lapping, scribing, and pre-king, and mounted in a semiconductor device package to obtain a semiconductor device having desired performance.
上述の実施例では、白金シリサイド層中チタン層・白金
層・金層からなる金電極構造を有するシリコン・プレー
ナトランジスタ素子について説明したが、この発明は上
述の構造の金電極に限らず、少なくとも最上層が金層で
ある電極構造の場合に適用でき、半導体基板もシリコン
に限らず、またプレーナ形トランジスタ以外の半導体装
置の製造に広く適用できることは明らかである。また、
パッシベーション膜としてスパッタリングで形成した酸
化シリコン膜を用い、モニタ一部の材料としてアルミニ
ウムを用いた場合について説明したが、この発明の主旨
にそうものであれば任意に選んでよいことも勿論である
。In the above embodiment, a silicon planar transistor element having a gold electrode structure consisting of a titanium layer, a platinum layer, and a gold layer in a platinum silicide layer was described, but the present invention is not limited to the gold electrode having the above structure. It is clear that the present invention can be applied to an electrode structure in which the upper layer is a gold layer, and the semiconductor substrate is not limited to silicon, and can be widely applied to the manufacture of semiconductor devices other than planar transistors. Also,
Although a case has been described in which a silicon oxide film formed by sputtering is used as the passivation film and aluminum is used as the material for a part of the monitor, it is of course possible to select any material as long as it is consistent with the gist of the present invention.
要するに、この発明では最上層が金層である電極構造を
有する半導体装置のバツシベーショ、ン膜の所望領域に
窓開けを行なうに際して、金、半導体基体およびパッシ
ベーション膜をエツチングしないエツチング液で容易に
エツチングされうる卑金属からなるモニタ一部をパッシ
ベーション膜形成前に形成しておき、パッシベーション
膜を形成後、このモニタ一部の上を含めてパッシベーシ
ョン膜に窓明けを行ない、上記モニタ一部を選択的にエ
ツチングするエツチング液でモニタ一部が完全に除去さ
れるか否かをもって、上記所望領域のパッシベーション
膜の除去をモニターリングすることに要点があるので、
モニタ一部形成材料としては上記条件を満たすものであ
ればよいのであるが、アルミニウムは簡単な方法で形成
できるので極めて好適である。In short, in the present invention, when opening a window in a desired region of a buffer film of a semiconductor device having an electrode structure in which the uppermost layer is a gold layer, the window can be easily etched with an etching solution that does not etch the gold, the semiconductor substrate, and the passivation film. A part of the monitor made of a transparent base metal is formed before forming the passivation film, and after the passivation film is formed, a window is opened in the passivation film including the top of this part of the monitor, and the part of the monitor is selectively etched. The key point is to monitor the removal of the passivation film in the desired area by checking whether a part of the monitor is completely removed with the etching solution.
The material for forming part of the monitor may be any material as long as it satisfies the above conditions, but aluminum is extremely suitable because it can be formed by a simple method.
以上詳述したように、この発明の製造方法ではパッシベ
ーション膜の除去をモニターリングしてその完了を検知
できるようにしたので、パッシベーション膜の開孔を過
大にすることもなく、微細パターンの半導体装置でもそ
の製造歩留りおよび製品の信頼性を向上させることがで
きる。As detailed above, in the manufacturing method of the present invention, the removal of the passivation film can be monitored and the completion of the removal can be detected, so that the openings in the passivation film are not made too large and the semiconductor device with a fine pattern can be manufactured. Even its manufacturing yield and product reliability can be improved.
第1図〜第10図はこの発明の一実施例の各工程段階で
の状態を示す断面図である。
図において、(1)は半導体基板、(2)はペース領域
、(3)はコレクタ領域、(8)は金層、(9)は配線
金属層、(131ハモニタ一部(金属膜) 、(14)
はパッシベーション膜(保護絶縁膜)、0@はエミッタ
接続用開孔、Oηはベース接続用開孔である。
なお、図中同一符号は同一または相当部分を示す。
〉 〉 \第
5図
第8図
第9図
第1O図FIGS. 1 to 10 are cross-sectional views showing the state at each process step of an embodiment of the present invention. In the figure, (1) is a semiconductor substrate, (2) is a space region, (3) is a collector region, (8) is a gold layer, (9) is a wiring metal layer, (131 hamonitor part (metal film), ( 14)
is a passivation film (protective insulating film), 0@ is an opening for emitter connection, and Oη is an opening for base connection. Note that the same reference numerals in the figures indicate the same or corresponding parts. 〉 〉 \Figure 5 Figure 8 Figure 9 Figure 1O
Claims (2)
の電気的機能を取り出すために少なくとも最上層が金層
からなる配線金属贋金形成した後に、上記配線金属層の
上を含めて上記半導体基板上に保護絶縁膜を形成し、上
記配線゛金属層を外部回路に接続するための開孔を上記
保護絶縁膜に形成する工程を備えた半導体装置の製造方
法において、上記保護絶−縁膜を形成する以前に金、上
記半導体基板および上記保護絶縁膜を実質的にエツチン
グしないエツチング液で容易にエツチングされ得る金員
膜を上記半導体基板上の上記電気的機能に影響を与えな
い部分に形成し、その後に上記保護絶縁膜を形成するよ
うにし、上記金属膜の上にも上記絶縁保論膜に開孔を形
成し、上記エツチング液で上記金属膜がエツチングされ
るようになるととKよって上記絶縁保護膜の上記開孔の
形成が完了したことを判定することを特徴とする半導体
装置の製造方法。(1) After forming an active region in a semiconductor substrate and forming a wiring metal counterfeit whose top layer is at least a gold layer in order to take out the electrical function of the active region, the semiconductor substrate including the top layer of the wiring metal layer is formed. A method for manufacturing a semiconductor device comprising the steps of: forming a protective insulating film on a substrate; and forming an opening in the protective insulating film for connecting the wiring (metal layer) to an external circuit; Before forming gold, a gold film that can be easily etched with an etching solution that does not substantially etch the semiconductor substrate and the protective insulating film is formed on a portion of the semiconductor substrate that does not affect the electrical function. Then, the protective insulating film is formed, and an opening is formed in the insulating film on the metal film, so that the metal film is etched with the etching solution. A method for manufacturing a semiconductor device, comprising determining that formation of the opening in the insulating protective film is completed.
を用いることを特徴とする特許請求の範囲第1項記載の
半導体装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, characterized in that aluminum is used for the metal film and hydrochloric acid is used for the etching solution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19617681A JPS5895843A (en) | 1981-12-02 | 1981-12-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19617681A JPS5895843A (en) | 1981-12-02 | 1981-12-02 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5895843A true JPS5895843A (en) | 1983-06-07 |
JPS6360538B2 JPS6360538B2 (en) | 1988-11-24 |
Family
ID=16353459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19617681A Granted JPS5895843A (en) | 1981-12-02 | 1981-12-02 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5895843A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51117885A (en) * | 1975-04-10 | 1976-10-16 | Fujitsu Ltd | Semiconductor device manufacturing method |
-
1981
- 1981-12-02 JP JP19617681A patent/JPS5895843A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51117885A (en) * | 1975-04-10 | 1976-10-16 | Fujitsu Ltd | Semiconductor device manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
JPS6360538B2 (en) | 1988-11-24 |
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