JPS5895815A - Preparation of semiconductor device having laminate structure - Google Patents

Preparation of semiconductor device having laminate structure

Info

Publication number
JPS5895815A
JPS5895815A JP56194712A JP19471281A JPS5895815A JP S5895815 A JPS5895815 A JP S5895815A JP 56194712 A JP56194712 A JP 56194712A JP 19471281 A JP19471281 A JP 19471281A JP S5895815 A JPS5895815 A JP S5895815A
Authority
JP
Japan
Prior art keywords
single crystal
silicon layer
layer
crystal silicon
epitaxial growing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56194712A
Other languages
Japanese (ja)
Inventor
Nobufumi Komori
伸史 小守
Sunao Nishioka
西岡　直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56194712A priority Critical patent/JPS5895815A/en
Publication of JPS5895815A publication Critical patent/JPS5895815A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a single crystal silicon layer being excellent in the uniformity of the quality and thickness of a film, by performing simultaneously the epitaxial growing and laser annealing thereof. CONSTITUTION:Annealing by laser beams 5 are performed simultaneously when a wafer is placed in the ambience of epitaxial growing, and thereby a single crystal silicon layer 6 having few crystal defects and being flat can be obtained. Although the embodiment refers only to the case wherein the present invention is applied to a semicondutor device having a laminate structure, an epitaxially- grown layer of excellent quality having few crystal defects can be obtained by applying laser annealing during the epitaxial growing, even when the mere epitaxial growing is applied.

Description

【発明の詳細な説明】 この発明は、積層構造を有する半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having a stacked structure.

従来、積層部の単結晶シリコン層を形成するためには、
まず第１図に示すように、開口部を有する二酸化シリコ
ン腺（２）ｒ形成した単結晶シリコン基板（１）をエビ
成長雰囲気中に電いて二酸化シリコン層（２）の上には
多結晶シリコン層（４ａ）を、また二酸化シリコン層（
２）の関口部分には単結晶シリコン層（８ａ）を成長さ
せた後、レーザー光線（５）を照射し、図２に示すよう
に単結晶シリコン層（８ｂ）の部分を核として多結晶シ
リコン層（４ａ）を単結晶シリコン層（４ｂ）化させて
いた。Conventionally, in order to form the single crystal silicon layer of the laminated part,
First, as shown in Figure 1, a monocrystalline silicon substrate (1) formed with silicon dioxide glands (2) having openings is placed in a shrimp growth atmosphere, and polycrystalline silicon is deposited on top of the silicon dioxide layer (2). layer (4a) and also a silicon dioxide layer (
After growing a single crystal silicon layer (8a) in the Sekiguchi part of 2), a laser beam (5) is irradiated to form a polycrystalline silicon layer using the single crystal silicon layer (8b) as a core, as shown in FIG. (4a) was made into a single crystal silicon layer (4b).

従来の方法では、二酸化シリコン１１（２）の上に多結
晶シリコンｍ　（４ａ）を、また二酸化シリコン層（２
）の開口部分には単結晶シリコン層（８ａ）を成長させ
た後に、レーザー光線照射によるアニールを行っている
ため、二酸化シリコン（２）のエツジ周辺に結晶欠陥が
多く含まれる（８１ｂ）、また、積層部が平たんになり
にくい等の欠点があった。In the conventional method, polycrystalline silicon m (4a) is placed on silicon dioxide 11 (2) and silicon dioxide layer (2) is placed on top of silicon dioxide layer (2).
), after growing the single crystal silicon layer (8a), annealing is performed by laser beam irradiation, so many crystal defects are included around the edges of the silicon dioxide (2) (81b). There were drawbacks such as the laminated portion being difficult to flatten.

この発明は、上記の従来法の欠点を除去するためになさ
れたもので、８ｉ１層部の単結晶シリコン−（６）を形
成する時に、エビ成長雰囲気に直ぐと同時にレーサー光
線（５）の照射によるアニールを行うことにより、結晶
欠陥の少ない、また平たんな積層部を形成することを目
的としている。This invention was made to eliminate the drawbacks of the conventional method described above, and when forming the 8i1 layer of single crystal silicon (6), the shrimp growth atmosphere is immediately and simultaneously irradiated with a laser beam (5). The purpose of this annealing is to form a flat stacked part with few crystal defects.

第８図に示すように、ウェハをエビ成長雰囲気中に置く
と同時にレーザー光線（５）によるアニールを行うこと
によって、結晶欠陥が少なく、平たんな単結晶シリコン
層（６）が得ら口る。As shown in FIG. 8, a flat single-crystal silicon layer (6) with few crystal defects can be obtained by placing the wafer in a growth atmosphere and simultaneously annealing it with a laser beam (5).

なお、上記実施例では横層構造を有する半導体装置に本
発明を適用した場合についてのみ述べたが、単なるエビ
成長を行う場合でも、エビ成長中にレーザーアニールを
行うことによって結晶欠陥の少ない良質のエピタキシャ
ル成長層が得られることは言うまでもない。In the above embodiment, only the case where the present invention is applied to a semiconductor device having a horizontal layer structure has been described, but even when simple shrimp growth is performed, laser annealing can be performed during shrimp growth to produce high-quality crystals with few crystal defects. Needless to say, an epitaxially grown layer can be obtained.

以上のように、エビ成長とレーザーアニールを同時に行
うことによって、膜質、膜厚の均一性ともに良好な単結
晶シリコン層が得らｎるという効果がおる。As described above, by performing shrimp growth and laser annealing at the same time, a single crystal silicon layer with good film quality and film thickness uniformity can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来の方法による製造過程を示す断面
図であり、第８図は本発明の実施例を示す断面図でろり
、（１）は単結晶シリコン層、（２）は二酸化シリコン
層、（８ａ）はレーザー照射前の単結晶シリコン層、（
８ｂ）はレーザー照射後の単結晶シリコン層、（８１ｂ
）はレーザー照射後も、結晶欠陥を多く含む単結晶シリ
コン層、（４ａ）はレーザー照射前の多結晶シリコン層
、（４ｂ）はレーザー照射後の単結晶シリコン層、（５
）はレーザー光線、（６）は横まｎると同時にレーザー
・アニールによって単結晶化さｎた単結晶シリコン層を
示している。 なお、図中同一符号は同一、甘たは相当部分を示す。 代理人　　　葛　野　信　− 第１図 第２図 第３図1 and 2 are cross-sectional views showing the manufacturing process using a conventional method, and FIG. 8 is a cross-sectional view showing an embodiment of the present invention, in which (1) is a single crystal silicon layer, (2) is a Silicon dioxide layer, (8a) is the single crystal silicon layer before laser irradiation, (
8b) is a single crystal silicon layer after laser irradiation, (81b)
) is a single crystal silicon layer containing many crystal defects even after laser irradiation, (4a) is a polycrystalline silicon layer before laser irradiation, (4b) is a single crystal silicon layer after laser irradiation, (5
) shows a laser beam, and (6) shows a single-crystal silicon layer that has been monocrystalized by laser annealing at the same time as it is traversed. In addition, the same reference numerals in the drawings indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 積層部の基板を形成する時に、エピタキシャル成長雰囲
気中に櫨くと同時にレーザー光線を照射することを特徴
とする積層構造を有する半導体装置の製造方法。A method for manufacturing a semiconductor device having a laminated structure, characterized in that when forming a substrate of a laminated part, the substrate is placed in an epitaxial growth atmosphere and simultaneously irradiated with a laser beam.
JP56194712A 1981-11-30 1981-11-30 Preparation of semiconductor device having laminate structure Pending JPS5895815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56194712A JPS5895815A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device having laminate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56194712A JPS5895815A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device having laminate structure

Publications (1)

Publication Number Publication Date
JPS5895815A true JPS5895815A (en) 1983-06-07

Family

ID=16328990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56194712A Pending JPS5895815A (en) 1981-11-30 1981-11-30 Preparation of semiconductor device having laminate structure

Country Status (1)

Country Link
JP (1) JPS5895815A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630681A (en) * 1992-07-16 1994-02-08 Tomu Komiyuniikeeshiyonzu Kk Electric float

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630681A (en) * 1992-07-16 1994-02-08 Tomu Komiyuniikeeshiyonzu Kk Electric float

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