JPS5894042A - Information collecting system - Google Patents

Information collecting system

Info

Publication number
JPS5894042A
JPS5894042A JP56192577A JP19257781A JPS5894042A JP S5894042 A JPS5894042 A JP S5894042A JP 56192577 A JP56192577 A JP 56192577A JP 19257781 A JP19257781 A JP 19257781A JP S5894042 A JPS5894042 A JP S5894042A
Authority
JP
Japan
Prior art keywords
timer
interrupt
circuit
auxiliary
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56192577A
Other languages
Japanese (ja)
Inventor
Keiji Toki
戸木 啓治
Yoshimasa Saito
好正 斎藤
Koichi Matsuda
晃一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56192577A priority Critical patent/JPS5894042A/en
Publication of JPS5894042A publication Critical patent/JPS5894042A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Abstract

PURPOSE:To collect the information produced before a monitor timer works and to avoid the working of a processor for an electronic computer system, by detecting an interruption due to an auxiliary timer by a discriminating circuit. CONSTITUTION:A processor contains an interval timer 4, a monitor timer 6, an auxiliary timer 8 which is set at a desired time within the time rangesset by the timers 4 and 6 respectively, and a discriminating circuit 10 which discriminates the contents of interruption. When the circuit 10 detects an interruption due to the timer 8 with the signal B, the timers 6 and 8 are reset. Then the memory stacking is performed at that moment for the program information. Then a jog abort processing part 12 is started when a stack area is filled. Thus only the faulty jog is aborted, and the working of the processor is not stopped.

Description

【発明の詳細な説明】 本発明は情報収集方式に関し、特に電子計算機システム
の処理装置が暴走をなし監視タイマが作動し処理装置が
障害を発生する際の情報収集方式現在史用されている′
シ子計算機システムの処理装置には処理装置が何らかの
理由例えばプログラム作成上の誤とか装置の障害等によ
り所要の処理が遂行されず暴走をすることが生じる。こ
の埴走を検知するために監視タイマを設けである。更に
一万処理装置は処理能力を高めるために、複数の処理を
並列して遂行する割込み前作を許可している。このW」
込み前作のe町のタイミングはインターパ〃・タイマに
て行うのが一般である。一方剖込み動作であるが、プロ
グラム処理上連続して処理を遂行せねばならないことが
生じるので、インターバル・タイマには割込み可否を示
すフラグをもたし1めている。従って割込み禁止のフラ
グが付せられたプログラム遂行中に何らかの障害例えば
プログツム・ミスが生じると直接鹸視タイマにひっかか
り処理装置を停止状惑にしてしまうのである。処理装置
が停止状惑になるとその時の状態情報が何ら得られず、
障害発生後の対策に困雉を米たすという欠点とプログツ
ムによる綽走の検出が不可能である欠点があっ几。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information collection method, and in particular, an information collection method currently in use when a processing unit of a computer system goes out of control, a monitoring timer is activated, and a failure occurs in the processing unit.
In the processing device of the Shiko computer system, for some reason, for example, due to an error in programming or a failure of the device, the processing device may not be able to perform the required processing and run out of control. A monitoring timer is provided to detect this clay running. Furthermore, the 10,000 processing units allow interrupt pre-processing to perform multiple processes in parallel in order to increase processing capacity. This W”
The timing of the e-town in the previous work is generally done using an interpa/timer. On the other hand, regarding the interrupt operation, since it is necessary to execute the process continuously in program processing, the interval timer is provided with a flag indicating whether or not an interrupt is allowed. Therefore, if some kind of failure, such as a program error, occurs during the execution of a program to which an interrupt prohibition flag has been attached, it will be directly caught by the interrupt timer and cause the processing device to stop. When the processing equipment is stopped, no status information can be obtained at that time.
There are two drawbacks: it makes it difficult to take measures after a failure occurs, and it is impossible to detect skidding using a program.

本発明は以上の欠点に鑑みなされたものにして、本発明
#′i刷込み補止時の障害発生時に処理装置が停止状態
になる直前の情報を収集する情報収集方式を提供するこ
とを目的とするものである0木発明を略6見すると、処
理装置のインターバル・タイマと監視タイマとにそれぞ
れ設定され九時+ijJ囲内の所要時間に設定された刈
込禁止機能をもたない補助タイマと、刷込み内容を識別
する回路とを処理装置に設け、職別回路が補助タイマに
よる割込みを検知して、監視タイマ作#J曲の情報を収
集するとともに異常が起きたジョブのみをアボートし、
処理装置を停止状態にしないことを特赦とするものであ
る。
The present invention has been made in view of the above drawbacks, and an object of the present invention is to provide an information collection method that collects information immediately before the processing device is stopped when a failure occurs during imprint compensation. If we look at the 0 tree invention, which is a device that does A circuit for identifying the contents is provided in the processing device, and the job-specific circuit detects the interrupt by the auxiliary timer, collects information on the #J song created by the monitoring timer, and aborts only the job in which an abnormality has occurred.
This provides amnesty for not shutting down processing equipment.

以下本発明を実施するのに好ましい具体例を図を用いて
詳細に説明する。@1図は従来の処理装置の要部ブロッ
ク図であり、第2図は9本′41.用の情報収集方式を
示す処+l!I装置の一実施例の要部ブロック図、′4
IJ3図は処理フロー図である。1は処理装置、2は割
込み制御部、3は命令実行部、4はインターバル・タイ
マ、5はデログフム情m、J!i、6はwM視タイマ、
7はアンド回路、8は補助タイマ、9はオア回路、lO
は割込内g識別回路、11はモード切替、fI呻部であ
る。以下@1図と第2図を対称しながら第2図について
説明する。処理部1這1のインターバル・タイマ4と甑
硯タイマ6は例えば鏡大500XlO”沙と2秒とにそ
れぞれセソー□トされており付設した補助タイマ8は5
00X10  ”秒以上2秒以下にセラYする。プログ
ラム情報胎5(以後PSW5と記す)の剖込みを表示す
る信号部フラグビットFとインターバル・タイマ4の(
4号はアンド回路7に入力される。これはフラグがあり
インターバル・タイマ4が″オン″になるとアンド回v
!17が別込み信号Aを出力するのである。
Preferred specific examples for carrying out the present invention will be described in detail below with reference to the drawings. @ Figure 1 is a block diagram of the main parts of a conventional processing device, and Figure 2 is a block diagram of nine '41. This is the place to show the information gathering method for +l! Main part block diagram of an embodiment of I device, '4
Diagram IJ3 is a processing flow diagram. 1 is a processing unit, 2 is an interrupt control unit, 3 is an instruction execution unit, 4 is an interval timer, 5 is a deroghum information m, J! i, 6 is wM visual timer,
7 is an AND circuit, 8 is an auxiliary timer, 9 is an OR circuit, IO
Reference numeral 11 indicates an interrupt internal g identification circuit, and 11 indicates a mode switching and fI switching section. Below, Fig. 2 will be explained while comparing Fig. 1 and Fig. 2. The interval timer 4 and the timer 6 of the processing unit 1 are sesorted to, for example, 500X1O" and 2 seconds, respectively, and the attached auxiliary timer 8 is set to 5.
00
No. 4 is input to the AND circuit 7. This has a flag and when interval timer 4 turns "on", the AND
! 17 outputs the separate signal A.

この刷込信号Aと補助タイマ8の18号Bがオア回路9
に入力される。補助タイマ8は作−J硬所蜜時間になる
と“オン“信号を出力するのである。従1\ 米量にはこの補助タイマ8及びオア回路9はなかった。
This printing signal A and No. 18 B of the auxiliary timer 8 are OR circuit 9
is input. The auxiliary timer 8 outputs an "on" signal when the working time is reached. Sub 1\ This auxiliary timer 8 and OR circuit 9 were not included in the quantity.

結果としてオア回路9の出力tS号Cが刷込み信号とな
る。出力イd号Cは割込み#lJ両部2に入力され、一
方割込み制御部2には割込み内容識別回路10が設けら
れており、識別回路11j入力信号Cが信号A或いは信
号Bによるものかを識別し、ダに信号Bによる場合には
デパック篭−ド切54tlJ御部11に信号を送出しデ
パックモードに切替えるのである。従来例の場合は本割
込内容鐵別回路lOはなかった。割込み内容識別回路1
0がA信号即ち従来例信号であると検出すると割込み制
御部2は割込みの信号によりPiプログフふをPi+1
プログラムへの処理変更2−1と監視タイマをリセット
処理する2−2を#lJ御しタイマ・リセット信号りは
監視タイマ6をリセツFする。一方の処理変jl!2−
IK基すいて命令実行部3は命令を変更する。割込みが
なければ命令実行部3は現在実行中の命令を実行し続け
る。以上の何れにしても監視タイマ6が前作すると出力
18号Eにより処理装置を停止状態にするのである。以
上が従来例の前作であり停止状態に至るまで情報収集を
行っていないのである。本発明はインターパ〃・タイマ
4の動作に続いて補助タイマ8が動作をなし、割込み内
容−別回路lOは信号Bによる割込みであることを検知
する。しかもこの割込みは補助タイマ8並びに監視タイ
マ6をリセットすると共に、モード切替制御部11はデ
バッグ状態に切替えた後、命4r犬行部3の命令の実行
を再開する。そして、ダパッグ状l漣であるが故に、1
命令若しくはプツンチ命令を実行する反にデバッグモー
ドdJ込みDBIを生ずる。
As a result, the output tS C of the OR circuit 9 becomes the imprint signal. The output ID number C is input to the interrupt #lJ unit 2, and on the other hand, the interrupt control unit 2 is provided with an interrupt content identification circuit 10, and the identification circuit 11j determines whether the input signal C is due to the signal A or the signal B. If the signal B is used, a signal is sent to the depack cage switch 54tlJ control section 11 to switch to the depack mode. In the case of the conventional example, there was no circuit 10 for this interrupt content. Interrupt content identification circuit 1
When detecting that 0 is the A signal, that is, the conventional signal, the interrupt control unit 2 changes the Pi program to Pi+1 by the interrupt signal.
#lJ controls the process change 2-1 to the program and the process 2-2 for resetting the monitoring timer, and the timer reset signal resets the monitoring timer 6. One processing change! 2-
The instruction execution unit 3 changes the instruction based on the IK. If there is no interrupt, the instruction execution unit 3 continues to execute the instruction currently being executed. In any case, if the monitoring timer 6 is activated, the output No. 18 E causes the processing device to be stopped. The above is the previous version of the conventional example, and information is not collected until the system is stopped. In the present invention, the auxiliary timer 8 operates following the operation of the inter-timer 4, and the interrupt content-separate circuit 10 detects that the interrupt is caused by the signal B. Moreover, this interrupt resets the auxiliary timer 8 and the monitoring timer 6, and the mode switching control section 11 resumes execution of the commands of the life cycle section 3 after switching to the debug state. And since it is a dapagu-like lren, 1
Executing an instruction or a push instruction causes a debug mode dJ included DBI.

割込内容絨別回路lOでは、デバツグ七−ド割込みの発
生を検出すると、監視タイマ6および補助タイマ8をリ
セットすると共に、その時点の、psw情報のメモリス
タックを行う。尚、その後スタックエリアが満杯時には
、ジョグアボート処理部12に起動がかかり、当該ジョ
グのみアボートする。
When the interrupt content sorting circuit IO detects the occurrence of a debug code interrupt, it resets the monitoring timer 6 and the auxiliary timer 8, and performs memory stacking of the psw information at that time. Note that when the stack area becomes full thereafter, the jog abort processing section 12 is activated and only the jog in question is aborted.

以上の説明より明らかなように、“本発明によれば特に
割込み禁止時に発生する障害時の情報が収集できる情報
収集方式となり、本発明を電子計算機Vステムに適用す
れば14M解析上きわめて利点の多いものとなる。
As is clear from the above explanation, "According to the present invention, an information collection method can be obtained that can collect information especially when a failure occurs when interrupts are disabled. If the present invention is applied to a computer V-stem, it will be extremely advantageous in terms of 14M analysis. There will be many.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の処理装置の要部ブロック図、第2図は本
発明の情報収集方式を示す処理装置の一実施例の要部ブ
ロック図、第3図は本発明のフローチャートである。 図において、lFi処理装置、4はインターバル・タイ
マ、6は監視タイマ、8は補助タイマ、10は誠別回路
を示す。 代理人  弁理士 松 岡 宏四部5′、コ第1図 第3図
FIG. 1 is a block diagram of a main part of a conventional processing device, FIG. 2 is a block diagram of a main part of an embodiment of a processing device showing the information collection method of the present invention, and FIG. 3 is a flowchart of the present invention. In the figure, 4 is an interval timer, 6 is a monitoring timer, 8 is an auxiliary timer, and 10 is a Seibetsu circuit. Agent: Patent Attorney Hiroshi Matsuoka 5', Ko Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 割込み可否のフラグをもつインターバル・タイマと装置
の暴走を示す時間を規定する監視タイマを具備し該イン
ターパ〃・タイマにより割込みを実行する処理装置にお
いて、該インターパ〜・タイマと監視タイマとのそれぞ
れに設定された時間の範囲内に所要時間を設定された前
記フラグ機能をもたない補助タイマを設けるとともに、
割込み円安を識別する回路を設け、該識別回路が前記補
助タイマによる割込みを検知して前記監視タイマ作動前
の情報を収集するとともにエラー波及範囲をローカライ
ズするようにしたことを特徴とする情報収集方式。
In a processing device that is equipped with an interval timer having a flag indicating whether or not an interrupt is allowed and a monitoring timer that specifies a time indicating a runaway of the device, and that executes an interrupt using the interval timer, each of the interval timer and the monitoring timer In addition to providing an auxiliary timer without the flag function whose required time is set within a set time range,
Information collection characterized in that a circuit is provided to identify an interrupt depreciation of the yen, and the identification circuit detects an interrupt by the auxiliary timer, collects information before the monitoring timer is activated, and localizes an error spread range. method.
JP56192577A 1981-11-30 1981-11-30 Information collecting system Pending JPS5894042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56192577A JPS5894042A (en) 1981-11-30 1981-11-30 Information collecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56192577A JPS5894042A (en) 1981-11-30 1981-11-30 Information collecting system

Publications (1)

Publication Number Publication Date
JPS5894042A true JPS5894042A (en) 1983-06-04

Family

ID=16293590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56192577A Pending JPS5894042A (en) 1981-11-30 1981-11-30 Information collecting system

Country Status (1)

Country Link
JP (1) JPS5894042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63257041A (en) * 1987-04-14 1988-10-24 Nec Corp Diagnosing system for system of real time os

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63257041A (en) * 1987-04-14 1988-10-24 Nec Corp Diagnosing system for system of real time os

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