JPS5893300A - Method of producing multilayer printed board - Google Patents
Method of producing multilayer printed boardInfo
- Publication number
- JPS5893300A JPS5893300A JP19092281A JP19092281A JPS5893300A JP S5893300 A JPS5893300 A JP S5893300A JP 19092281 A JP19092281 A JP 19092281A JP 19092281 A JP19092281 A JP 19092281A JP S5893300 A JPS5893300 A JP S5893300A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- multilayer printed
- printed board
- conductor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 14
- 239000004020 conductor Substances 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 49
- 238000007650 screen-printing Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000007639 printing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004534 enameling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は多層プリント板の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a multilayer printed board.
(2)技術の背景
各種電子機器において、電子回路をパターン印刷した多
層プリント板が用いられている。電子機器の小型化、機
能の多様化等に伴いプリント板の配線・!ターンが高密
度化し、ノリ一ン切れやi4ターンの歪み等の彦い品質
の優′i″L、た信頼性の高い多層プリント板が要求さ
れている。(2) Background of the Technology Multilayer printed boards on which electronic circuit patterns are printed are used in various electronic devices. With the miniaturization of electronic devices and diversification of functions, printed circuit board wiring and! As the density of turns increases, there is a demand for highly reliable multilayer printed circuit boards with superior quality such as cut-off of glue and distortion of i4 turns.
(3)従来技術と問題点
従来の多層プリント板製造方法による2層のプリント板
の断面図を第1図に示す。従来の製造方法においては、
まず基板1上に第1導体パターン層2を印刷形成し、次
に絶縁層3を形成する。続いて適当な位IMで第1導体
・ぐターン層2と導通する第2導体パターン層4を絶縁
層3上に印刷形成する。このような従来方法においては
、絶縁層3の表面には第1導体・やターンl脅2の形状
に従って凹凸が形成されるため、i22導パターン層4
の印刷が均一に行われず連続して形成すべき導体パター
ンが絶縁層3の四部で・ヤターン切れ5を起したp、普
た凸部と凸部での・パターンの太さが一足とならず、凸
部上に印刷したノeターンが太くなり隣接するパターン
との誤接触の問題が生じ、壕だ一足の信号伝達特性が得
られなくなるという問題も生ずる。(3) Prior Art and Problems FIG. 1 shows a cross-sectional view of a two-layer printed board manufactured by a conventional multilayer printed board manufacturing method. In conventional manufacturing methods,
First, a first conductive pattern layer 2 is printed on a substrate 1, and then an insulating layer 3 is formed. Subsequently, a second conductor pattern layer 4 electrically connected to the first conductor/gut pattern layer 2 is printed on the insulating layer 3 by IM to an appropriate extent. In such a conventional method, unevenness is formed on the surface of the insulating layer 3 according to the shape of the first conductor or the turn latch 2, so that the i22 conductive pattern layer 4
Printing was not done uniformly, and the conductor pattern that should be formed continuously was cut off in the four parts of the insulating layer 3, and the thickness of the pattern was not equal between the convex parts. In addition, the problem of erroneous contact with the adjacent pattern occurs because the no.e-turn printed on the convex portion becomes thicker, and the problem arises that the signal transmission characteristics of the trench cannot be obtained.
(4)発明の目的
本発明は上記従来技術の欠点に筋1みなされたものであ
って、絶縁層表面の凹凸に基くその」一層の導体パター
ンのパターン切れやパターンのT1ミみ、太さの不均−
等をなくし信頼性の高い導体パターンを形成できる多層
プリント板の製造方法の提供を目的とする。(4) Purpose of the Invention The present invention addresses the drawbacks of the above-mentioned prior art, and addresses the problem of pattern breakage in a single-layer conductor pattern, T1 depth, and thickness of the pattern due to unevenness on the surface of the insulating layer. The disparity of -
The purpose of the present invention is to provide a method for manufacturing a multilayer printed board that can form a highly reliable conductor pattern by eliminating such problems.
(5)発明の構成
この目的を達成するため、本発明では基板上に少くとも
2層の導体パターン層を絶縁層を介して積層した多層シ
リンド板の製造方法において、最上層以外の導体パター
ン形成後に該導体パターン形成部以外の部分を該導体パ
ターンと同じ厚さの絶縁層で憶う工程を含むことを特徴
としている。(5) Structure of the Invention In order to achieve this object, the present invention provides a method for manufacturing a multilayer cylinder board in which at least two conductor pattern layers are laminated on a substrate with an insulating layer interposed therebetween, in which the conductor pattern is formed on layers other than the top layer. The method is characterized in that it includes a step of later covering a portion other than the conductor pattern forming portion with an insulating layer having the same thickness as the conductor pattern.
(6)発明の実施例
第2図は本発明方法によυ製造した2層のプリント板の
断面図であり、第3図から第7図は本発明方法の各別の
工程におけるプリント板を順番に示した平面図である。(6) Embodiments of the Invention Fig. 2 is a cross-sectional view of a two-layer printed board manufactured by the method of the present invention, and Figs. 3 to 7 show printed boards in different steps of the method of the present invention. It is a top view shown in order.
セラミック又は鉄若しくはアルミニウム基板上にガラス
等の絶縁材でホーロー処理したホーロー材からなる基板
10上にスクリーン印刷により第1導体パターン層ll
を形成する(第3図)。第1.導体パターン層11の乾
燥後渣たは乾燥−焼成後、この第1導体パターン層11
のネガティブなパター(3)
ン、即ち第14体パターン層11 bt外の部分を絶縁
ペーストにより印刷し絶縁層12を形成する(第4図)
。このようなネガティフ゛パターンのスクリーン印刷用
マスクは第1導体・やターン層月1のマスクフィルムを
用いて芥易に作ることができる。A first conductor pattern layer 11 is formed by screen printing on a substrate 10 made of an enameled material obtained by enameling a ceramic, iron, or aluminum substrate with an insulating material such as glass.
(Figure 3). 1st. After drying the conductive pattern layer 11 or after drying and baking, this first conductive pattern layer 11
The negative pattern (3), that is, the part outside the 14th body pattern layer 11 bt is printed with an insulating paste to form an insulating layer 12 (FIG. 4).
. Such a screen printing mask with a negative pattern can be easily made using a mask film having the first conductor or turn layer.
この絶縁層12の厚さは第1導体ノぐターン層11の厚
さと同じとなるように、スクリーンのメッ71、絶縁ペ
ースト材料、印刷回数等を適当に選定する。The mesh 71 of the screen, the material of the insulating paste, the number of times of printing, etc. are appropriately selected so that the thickness of the insulating layer 12 is the same as the thickness of the first conductor nozzle layer 11.
この絶縁層12の焼成後、第14体ノぐターン層11の
ランド上に導体層間導通用の導通層13をスクリーン印
刷により形成する(第5図)。続いて、第4図に示した
絶縁層12と同様に、導通層13のネガティグなノやタ
ーンの絶縁層14を絶縁ペーストを用いてスクリーン印
刷により形成する(第6図)。続いて、この絶縁層14
上に第2導体ノ4ターン層15をスクリーン印刷により
形成する。この絶縁層12.14は11.13のネガテ
ィブノ?ターンと説明した’#E、11.13のiZタ
ーン巾、導通穴径に対して12.14をmfkX 0.
2 rut程度大きめに構成してもよく、この場合絶縁
層12゜(4)
14印刷時の流れ込みによってランド径、パターン巾が
小さくなることを防止できる。After firing this insulating layer 12, a conductive layer 13 for conduction between conductor layers is formed on the land of the fourteenth body turn layer 11 by screen printing (FIG. 5). Subsequently, in the same way as the insulating layer 12 shown in FIG. 4, an insulating layer 14 of the negative turns of the conductive layer 13 is formed by screen printing using an insulating paste (FIG. 6). Subsequently, this insulating layer 14
A second conductor four-turn layer 15 is formed thereon by screen printing. This insulating layer 12.14 is the negative node of 11.13? '#E explained as a turn, iZ turn width of 11.13, 12.14 for the conduction hole diameter mfkX 0.
It may be configured to be approximately 2 ruts larger, in which case it is possible to prevent the land diameter and pattern width from becoming smaller due to inflow during printing of the insulating layer 12° (4) 14.
以上のような導体パターン層の積層工程をさらに繰り返
して3層以上の多層プリント板を構成してもよい。また
、第3図に示した導通層13の形成工程と第4図に示し
た絶縁層14の形成工程の順序は逆であってもよい。A multilayer printed board having three or more layers may be constructed by further repeating the process of laminating the conductor pattern layers as described above. Further, the order of the process of forming the conductive layer 13 shown in FIG. 3 and the process of forming the insulating layer 14 shown in FIG. 4 may be reversed.
(7)発明の詳細
な説明したように、本発明に係る多層プリント板の製造
方法においては、下層の導体ノ母ターン11形成後にこ
の導体パターン形成部以外の部分をこの導体パターン1
1と同じ厚さの絶縁層12で覆うことにより導体パター
ン表面とその周囲の絶縁層表面の高さを揃えている。従
って、この導体パターン層11上に設けた絶縁層14は
第2図に示すように平坦に形成され、従来のように凹凸
表面が形成されることはない。従って、この絶縁層14
上の導体・リーン層15は・ぞターン切れやノ4ターン
の歪みあるいはパターン太さの不揃い等を起すことはな
く、均一で優れた品質の配線i4←ンを有する信頼性の
高い多層プリント板が得られる。(7) As described in detail of the invention, in the method for manufacturing a multilayer printed board according to the present invention, after forming the lower layer conductor mother turn 11, the portion other than the conductor pattern forming portion is removed from the conductor pattern 1.
By covering with an insulating layer 12 having the same thickness as 1, the heights of the surface of the conductor pattern and the surface of the surrounding insulating layer are made equal. Therefore, the insulating layer 14 provided on the conductor pattern layer 11 is formed flat as shown in FIG. 2, and does not have an uneven surface as in the conventional case. Therefore, this insulating layer 14
The upper conductor/lean layer 15 is a highly reliable multilayer printed board with uniform and excellent quality wiring without causing turn breakage, distortion of turns, uneven pattern thickness, etc. is obtained.
第1図は従来方法により製造1−7だ多層プリント板の
断面図、第2図は本発明方法により製造した多層プリン
ト板の断面図、第3図から第7図は各各本発明方法の各
別工程でのプリント板を順番に示す平面図である。
10・・・基板、11・・・第1導体パターン層、12
゜14・・・絶縁層、15・・・第2導体パターン層。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士西舘和之
弁理士内田幸男
弁理士 山 口 昭 之Fig. 1 is a sectional view of a multilayer printed board manufactured by the conventional method 1-7, Fig. 2 is a sectional view of a multilayer printed board manufactured by the method of the present invention, and Figs. FIG. 3 is a plan view sequentially showing printed boards in different steps. 10... Substrate, 11... First conductor pattern layer, 12
゜14... Insulating layer, 15... Second conductor pattern layer. Patent applicant: Fujitsu Limited Patent application agent: Akira Aoki, patent attorney: Kazuyuki Nishidate, patent attorney: Yukio Uchida, patent attorney: Akira Yamaguchi
Claims (1)
iを介して積層した多層プリント板の製造方法において
、最上層以外の導体パターン形成後に該導体パターン形
成部以外の部分を該導体・やターンと同じ厚さの絶縁層
で檎う工程を含むことを特徴とする多層プリント板の製
造方法。■Insulate at least two layers of conductor/thousand turns on the board N
A method for manufacturing a multilayer printed board laminated via i, including a step of covering a portion other than the conductor pattern forming portion with an insulating layer having the same thickness as the conductor or turn after forming a conductor pattern on a layer other than the top layer. A method for manufacturing a multilayer printed board characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19092281A JPS5893300A (en) | 1981-11-30 | 1981-11-30 | Method of producing multilayer printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19092281A JPS5893300A (en) | 1981-11-30 | 1981-11-30 | Method of producing multilayer printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5893300A true JPS5893300A (en) | 1983-06-02 |
Family
ID=16265923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19092281A Pending JPS5893300A (en) | 1981-11-30 | 1981-11-30 | Method of producing multilayer printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5893300A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60171793A (en) * | 1984-02-17 | 1985-09-05 | 松下電器産業株式会社 | Method of producing multilayer circuit board |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50135559A (en) * | 1974-04-17 | 1975-10-27 | ||
JPS54108271A (en) * | 1978-02-14 | 1979-08-24 | Toppan Printing Co Ltd | Substrate for multiilayer printed circuit board |
JPS56130992A (en) * | 1980-03-18 | 1981-10-14 | Hitachi Ltd | Method of producing thick film board |
-
1981
- 1981-11-30 JP JP19092281A patent/JPS5893300A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50135559A (en) * | 1974-04-17 | 1975-10-27 | ||
JPS54108271A (en) * | 1978-02-14 | 1979-08-24 | Toppan Printing Co Ltd | Substrate for multiilayer printed circuit board |
JPS56130992A (en) * | 1980-03-18 | 1981-10-14 | Hitachi Ltd | Method of producing thick film board |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60171793A (en) * | 1984-02-17 | 1985-09-05 | 松下電器産業株式会社 | Method of producing multilayer circuit board |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62501181A (en) | Method for manufacturing internal connection plates with stable dimensions | |
JP2767312B2 (en) | Connection method between electromagnetic wave shielding layer and ground circuit in printed wiring board | |
JPS5893300A (en) | Method of producing multilayer printed board | |
JPH066031A (en) | Manufacturing method of printed wiring board | |
JPH10135640A (en) | Structure of printed wiring board and its manufacture | |
JPH0645758A (en) | Multilayer ceramic board and manufacture thereof | |
JPH04217389A (en) | Thick film multilayer circuit substrate and manufacture thereof | |
JP2542128B2 (en) | Ceramic multilayer wiring board and manufacturing method thereof | |
JPS59225590A (en) | High density multilayer circuit board | |
JPS593993A (en) | Method of producing thin film circuit board | |
JPS6148996A (en) | Method of producing ceramic multilayer wiring board | |
JPS5992599A (en) | Method of producing thick film hybrid integrated circuit | |
JPS58171896A (en) | Wet multilayer ceramic board and method of producing same | |
JPS59207691A (en) | Method of producing multilayer circuit board | |
JPH03288494A (en) | Via formation in multilayer ceramic substrate | |
JPH07193369A (en) | Method of manufacturing thick film multilayer wiring substrate | |
JP2002270448A (en) | Method for producing inductor component | |
JPS58147097A (en) | Method of producing multilayer circuit board | |
JPH066028A (en) | Manufacturing method of printed wiring board | |
JPH0464276A (en) | Formation of through hole | |
JPS63102398A (en) | Manufacture of ceramic circuit board | |
JPS60210898A (en) | Method of producing multilayer porcelain substrate | |
JPH0147912B2 (en) | ||
JPS62281395A (en) | Manufacture of ceramic wiring board | |
JPS6244840B2 (en) |