JPS5893236A - Formation of microminiature pattern - Google Patents

Formation of microminiature pattern

Info

Publication number
JPS5893236A
JPS5893236A JP19216281A JP19216281A JPS5893236A JP S5893236 A JPS5893236 A JP S5893236A JP 19216281 A JP19216281 A JP 19216281A JP 19216281 A JP19216281 A JP 19216281A JP S5893236 A JPS5893236 A JP S5893236A
Authority
JP
Japan
Prior art keywords
film
resist
mask
organic material
material film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19216281A
Other languages
Japanese (ja)
Inventor
Iwao Tokawa
東川 巌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP19216281A priority Critical patent/JPS5893236A/en
Publication of JPS5893236A publication Critical patent/JPS5893236A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve accuracy of processings by forming a flat surface organic substance film to a material having a stepped part or dents or projected areas to be processed, forming an organic substance mask providing an inorganic substance film mask and by etching such material to be processed. CONSTITUTION:A photo resist 8 is rotatingly coated on an Al-Si alloy film 6 of MOSFET, such photo resist is exposed by ultra violet ray using a mask having thick and thin areas in accordance with high and low levels and developed. Thereby the surface is almost flattened. Then, an Al film 9 is vacuum deposited, a thin resist film 10 is formed and these are exposed and developed. Thereby, the surface becomes flat, Al 9 prevents disturbed reflection from the base material and a highly accurate mask can be obtained. The Al 9 is anisotropically etched by CCl4 and O2. Thereafter, the resist film 8 is etched by the gas mainly composed of O2, and Al-Si alloy 6 is etched by the gas mainly composed of CCl4. According to this constitution, a highly accurate pattern can be produced without deformation of pattern due to stepped parts and dent or projected portions of base material and without any disable resolution.

Description

【発明の詳細な説明】 発明の観する技術分野 本発明は、微細ノ4ターン形成方法ζ;係わり、特に段
差或いは凹凸を有する被加工物にf#度良く微細・母タ
ーンを形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field: The present invention relates to a method for forming four fine turns, and more particularly, to a method for forming fine main turns with high f# on a workpiece having steps or irregularities. .

従来技術とその問題点 近時、半導体技術の分野では、各種のりソグラフイの開
発により最小寸法が1〔μ九〕程闇の微細加工技術の確
立がはかられている。しかし、被加工物の表面に段差や
凹凸等がある場合、上記したW[の微細加工を行なうこ
とは困雉である。これは、被加工物表面の段差や凹凸前
によりレジスト膜厚に不均一性が生じ、この膜埠不均−
に起因して解像度の低下が生じるためである。すなわち
、凹陥部や段差の下部等では運上な露光および現像が困
難となり、これにより加工種度が低下するためである。
Prior art and its problems Recently, in the field of semiconductor technology, efforts have been made to establish microfabrication technology with a minimum dimension of 1 [μ9] due to the development of various types of lamination. However, if the surface of the workpiece has steps, irregularities, etc., it is difficult to perform the above-mentioned fine processing of W[. This is because unevenness in the resist film thickness occurs due to steps and unevenness on the surface of the workpiece.
This is because a decrease in resolution occurs due to. In other words, it is difficult to perform exposure and development at the bottom of a recess or a step, thereby reducing the degree of processing.

また、被加工物表面からの乱反射により前記解像度が低
下するという問題もあった。
Furthermore, there is also the problem that the resolution is reduced due to diffused reflection from the surface of the workpiece.

そこで峡近、前記レジスト膜1嗅の不均一性および乱反
射の問題を解決するものとして、3層構造方式の微細・
譬ターン形成方法が楊粟されている。例えば、130 
th FiC8(1976Fall)Meeting 
Fxtended Abstracta Vo+ 76
−2,743〜744或いはJ、Vac、8ci。
Therefore, in order to solve the problems of non-uniformity and diffused reflection of the resist film 1, we proposed a three-layer structure method for fine-grained
The parable turn formation method is Yang Rui. For example, 130
th FiC8 (1976 Fall) Meeting
Fxtended Abstracta Vo+ 76
-2,743 to 744 or J, Vac, 8ci.

Technology  1 6 (61Nov/De
c  1979、P1620に詳しく述られている。こ
れらの提粂は、被加工物上に有機物′1Ilt喚をスピ
ンコードすると共にこの有穢物厨膜上に#載物質膜およ
びレジストを設け、レジストを所望iJ?ターンに4光
現像したのち該レノストをマスクとして無1幾物質膜を
選択エツチングし、次いで無機物質膜をマスクとして有
機物U膜を選択エツチングし、しかるのち有機物質1莫
として被加工物を選択エツチングする方法である。そし
て、下地被加工物の表面段差の影響を少なくし、レジス
トおよび有機物質膜を精度良くパターニングすることが
でき。
Technology 1 6 (61Nov/De
c 1979, P1620. These strips are used to spin-code an organic substance on the workpiece, and to provide a # coating material film and a resist on the impurity film, and to apply the resist to the desired iJ? After 4 photo-developments in one turn, selectively etching a non-material film using the renost as a mask, then selectively etching an organic U film using an inorganic material film as a mask, and then selectively etching a workpiece using an organic material as a mask. This is the way to do it. In addition, the influence of the surface level difference of the underlying workpiece can be reduced, and the resist and organic substance film can be patterned with high precision.

これにより被加工物の加工fit rK向丘をはかり得
る。
This makes it possible to measure the machining fit rK of the workpiece.

しかしながら、このような3+−構造方式の微細)臂タ
ーン形成方法にあってもレジストの平坦性および膜厚均
一性が十分とは云えず、十分な解像性を得ることはでき
なかった。すなわち、前記有機@’f(模の表面は広い
面償にわたり清らかな傾斜を有し、この上に積層される
叫機物質便の表面も滑らかな傾斜を有する。このため。
However, even with such a 3+- structure method for forming fine arm turns, the flatness of the resist and the uniformity of the film thickness cannot be said to be sufficient, and sufficient resolution cannot be obtained. That is, the surface of the organic @'f(form) has a clear slope over a wide area, and the surface of the organic material layer laminated thereon also has a smooth slope.For this reason.

無機物m膜上に積層されるレジストの1換厚は十分均一
とはならず、これによりレジストツヤターンの解像性が
低下する。また、スピンコード法により十分厚く設けら
れた有機物質膜の表面は、下地被加工物の段差や凹凸等
が密な領域でほとんど高低差のない平坦なものとなるが
、段差や凹凸等が疎な領域では下地被加工物の高低差を
反映した高低差のあるものとなる。このため。
The thickness of the resist layered on the inorganic film is not uniform enough, and the resolution of resist gloss and turns is thereby reduced. In addition, the surface of an organic material film formed sufficiently thickly by the spin-coding method will be flat with almost no difference in height in areas where there are dense steps and unevenness on the underlying workpiece. In such a region, there will be a difference in height that reflects the difference in height of the underlying workpiece. For this reason.

下地被加工物の段差や凹凸が疎な領域でレジストツヤタ
ーンの解像性低下を招く。
Resist gloss and turn resolution deteriorates in areas where the underlying workpiece has sparse steps and unevenness.

一方、スピンコード法により十分滑らかな表面を1尋る
には有機物質膜の膜厚を下地段差の2倍以上にも厚く形
成しなければならない。しかし、このように有機物質膜
の膜厚を厚くした場合、最kfdに形成されたレジスト
ツヤターンに忠実に被加工物を加工することは、種間お
よび処理時間等の面で困難であった。
On the other hand, in order to obtain a sufficiently smooth surface using the spin code method, it is necessary to form the organic material film to be at least twice as thick as the underlying step. However, when the thickness of the organic material film is increased in this way, it is difficult to process the workpiece faithfully to the resist glossy turn formed at the highest kfd due to the difference between seeds and processing time. .

発明の目的 本発明はこのような事情を考慮してなされたもので、そ
の目的とするところは、被加工物表面の段差や凹凸等に
起因するレジスト解1象ホの低下を確実に防止すること
ができ、被加工物の加工精度の大幅な向上をはかり得る
微細・母ターン形戎方法を提供することにある。
Purpose of the Invention The present invention has been made in consideration of the above circumstances, and its purpose is to reliably prevent a decrease in the resist resolution due to steps, irregularities, etc. on the surface of the workpiece. The object of the present invention is to provide a method for cutting a fine, main turn shape, which can greatly improve the processing accuracy of a workpiece.

発明の概要 本発明は、段差或いは凹凸を有する被加工物上に有機物
質膜をスピンコードしたのちこの有機物質膜表面を選択
エツチングし該表面を高低差のない平坦面に加工し、次
いで上記有機物質膜およびレジストを順次設けたのち該
レノストを所望)臂ターンに露光現像し、その後ドライ
エツチング法によりレジストをマスクとして無機物質膜
を選択エツチングし、5次いで無機物質膜をマスクとし
て有機物′直膜を選択エツチングし1、しかるのち有機
物質膜をマスクとして被加工物を選、択、エツチングす
るようにした方法である。
Summary of the Invention The present invention involves spin-coding an organic material film on a workpiece having steps or irregularities, and then selectively etching the surface of the organic material film to make the surface flat with no difference in height. After the material film and the resist are sequentially provided, the renost is exposed and developed in the desired direction (as desired), and then the inorganic material film is selectively etched using the resist as a mask using a dry etching method. In this method, the material to be processed is selectively etched (1), and then the workpiece is selectively etched using the organic material film as a mask.

すなわち、本発明は通常の3mm造方式の微細、ツクタ
ーン形成方法において、有機物質膜の表面を完全に平坦
fヒするため、有機物質膜表面に例えば露光処理を施し
て該表面を選択的にエツチングするようにした方法であ
る。
That is, in order to completely flatten the surface of an organic material film in a normal 3 mm manufacturing method for forming fine patterns, the present invention selectively etches the surface by subjecting the surface of the organic material film to, for example, an exposure treatment. This is how I did it.

発明の効果 本発明によれば、被加工物上C二股けられた有機物質膜
の表面が略完全に平坦化されるので、この上に積層され
る無機物質膜およびレジストの平坦性や膜厚均一性は十
分良好なものとなる。
Effects of the Invention According to the present invention, the surface of the organic material film bifurcated on the workpiece is almost completely flattened, so that the flatness and film thickness of the inorganic material film and resist laminated thereon are improved. The uniformity is sufficiently good.

このため、被加工物表面の段差や凹凸等に起因するレノ
ス) z4ターン解像性の低下を確実に防止することが
でき、これにより被加工物の加工精度の大幅な向上をは
かり得る。また、有機物質膜表面を選、択エツチングす
ることにより該表面の平坦化をはかつているので、有機
物″成膜の膜厚を従来の3層構造方式の場合より薄くす
ることができる。このため、エツチング加工の容易化を
はかり得る等の効果を奏する。
Therefore, it is possible to reliably prevent a decrease in the resolution of 4-turns caused by steps, unevenness, etc. on the surface of the workpiece, thereby significantly improving the processing accuracy of the workpiece. Furthermore, since the surface of the organic material film is planarized by selective etching, the thickness of the organic material film can be made thinner than in the case of the conventional three-layer structure method. , the etching process can be facilitated.

発明の実施例 以下1本発明の詳細を図示の実施例によって説明する。Examples of the invention The details of the present invention will be explained below with reference to the illustrated embodiments.

・ 第1図乃至第6図は本発明の一実施例に係わるMOS)
ランジスタ製造工程を示す断面図である。まず1周知の
技術を用い第1図に示す如くシリコンウェーハ11に素
子分離のためのフィールド酸化膜2、r−)酸化膜3お
よび多結晶シリコン?−) 4を杉成し、さらにこれら
のLに酸1ヒ膜5を堆積する。そして、酸化膜5にコン
タクトホールを形成し、この酸化膜5上に配線用のA7
− S i合金膜6(被加工物)を堆積した。なお、図
中2はソース・ドレイン1泊域を示している。
- Figures 1 to 6 are MOSs according to an embodiment of the present invention)
FIG. 3 is a cross-sectional view showing a transistor manufacturing process. First, using a well-known technique, as shown in FIG. 1, a silicon wafer 11 is coated with a field oxide film 2, an r-) oxide film 3, and a polycrystalline silicon wafer 11 for device isolation. -) 4 is deposited, and an acid 1 arsenic film 5 is further deposited on these L. Then, a contact hole is formed in the oxide film 5, and an A7 for wiring is formed on this oxide film 5.
- A Si alloy film 6 (workpiece) was deposited. Note that 2 in the figure indicates the source/drain overnight region.

次に、第2図に示す如<A1−8i合金模6上に有機物
質膜8(フォトレジストQFPR東京応化製)を約3〔
μ乳〕の厚さにスピンコードした。この状態で有機物酸
膜8の表面は、A−!−8i合金膜6の表面に比べれば
かなり平坦rヒされるが完全に平坦なものではなく1〔
μ雇〕程度の旨低差を有していた。次己、何機物質膜8
の最も低い部分は露光せず、他の部分にはその普低差に
応じた濃淡を有するマスクを用い通常の露光法により紫
外線4光を施した。その後、専用現像液で有機物質膜を
所定時開現像したところ有機物質膜8の表面晶低差は1
/3に低減され、該表面は第3図に示す如く略平坦なも
のとなった。
Next, as shown in FIG.
The thickness was spin-coded to the thickness of [μ milk]. In this state, the surface of the organic acid film 8 is A-! Although it is quite flat compared to the surface of the -8i alloy film 6, it is not completely flat.
There was a difference in performance between the two. Tsugumi, what machine material membrane 8
The lowest part was not exposed, and the other parts were exposed to four ultraviolet rays using a mask having shading according to the flatness difference. Thereafter, when the organic material film was opened and developed at a predetermined time using a special developer, the surface crystal height difference of the organic material film 8 was 1.
/3, and the surface became approximately flat as shown in FIG.

次に、第4図に示す如く有機物質膜8上に0.15〔μ
m〕厚のA!膜9をスパッタ蒸着すると共にAi膜9上
にレジスト10を約(1,5(μ乳〕1厚に塗布した。
Next, as shown in FIG. 4, 0.15 [μ
m] Thick A! At the same time as the film 9 was sputter-deposited, a resist 10 was applied on the Ai film 9 to a thickness of about (1.5 μm).

そして、Vシスト10を所望i+ターンに露光現像して
第5図に示す如きレジストツヤターンを形1戊した。こ
こで、レジスト10はその膜厚が薄く、膜厚変動が極め
て小さく、さらに良好な平面上に高低差のない状態に設
けられていたため、適正露光適正現像を行ない得て、そ
の解像性が極めて昼いものであった。また、レジスト下
地が十分に平坦であったためA1表面からの悪影響も極
、、めで少なく、さらにA!++乾9が十分な遮光性を
有し下地からの乱反射も認められず、レゾストパターン
の加工Mll’は極めて良好なものであった。
Then, the V cyst 10 was exposed and developed to a desired i+ turn to form a resist glossy turn as shown in FIG. Here, the resist 10 has a thin film thickness, extremely small film thickness fluctuations, and is provided on a good flat surface with no difference in height, so that proper exposure and development can be performed, and its resolution is high. It was very early in the day. In addition, since the resist base was sufficiently flat, there was very little negative influence from the A1 surface, and furthermore, A! ++Dui 9 had sufficient light-shielding properties, no diffused reflection from the base was observed, and the processed Mll' of the resist pattern was extremely good.

次に、CCノ、と0.との混合ガスによる異方性ドライ
エツチング法を用い、g6図に示す如くレジスト10を
マスクとしてAノ膜9を選択エツチングした。このとき
、A111%9はレジストツヤターンに忠実に′n1度
良く加工された。
Next, CCノ, and 0. The A film 9 was selectively etched using the resist 10 as a mask, as shown in Fig. g6, using an anisotropic dry etching method using a mixed gas. At this time, A111%9 was processed faithfully to the resist gloss and turn with excellent accuracy.

次いで、O,、l/スを主成分と1−る異方性ドライエ
ツチング法を用い、第7図に示す如< AAAg3マス
クとして有機物質膜8を選択エツチングした。このとき
形成されたパターンは罰記A 7 /4’ターンに忠実
な垂直壁を有する形状となり、A1−8i合金膜6の段
差形状になんら影特されなかった。また、レジスト10
は消失していたがA7膜9をネ何ら損なわれていなかっ
た。
Next, the organic material film 8 was selectively etched using an AAAg3 mask as shown in FIG. The pattern formed at this time had a shape having vertical walls faithful to the A 7 /4' turn, and was not affected by the stepped shape of the A1-8i alloy film 6. Also, resist 10
had disappeared, but the A7 membrane 9 was not damaged in any way.

次に、C(、#、を主成分とする異方性ドライエツチン
グ法を用い二第81図に示す如く有機物質1漢8をマス
クとしてA7(−8+合金膜6を選択エツチングした。
Next, the A7(-8+ alloy film 6 was selectively etched using an anisotropic dry etching method mainly containing C(, #) and using the organic material 1 to 8 as a mask, as shown in FIG.

このとき、A7パターンはすでに消失していたが、レジ
ストノやターンは何ら横われなかった。しかるのち、有
機物゛成膜8を除去することにより、所望配線・9ター
ンを得た。
At this time, the A7 pattern had already disappeared, but the resist number and turn were not crossed at all. Thereafter, by removing the organic film 8, desired wiring and nine turns were obtained.

かくして形成された配線〕やターンは設計・臂ターンを
楕1ず良く転写したレジス) /IPターンに忠実なも
のであった。つまり、下地段差や凹凸によるパターン変
形や解像不能といった問題がなく、高稍匿加工が可能と
なった。
The wiring] and turns thus formed were faithful to the designed/IP turns, which were perfectly transcribed. In other words, there are no problems such as pattern deformation or inability to resolve due to differences in base level or unevenness, and it is now possible to perform highly opaque processing.

このように本実施例方法によれば、凹凸を有した人7−
 S i合金膜6七に有機物′成膜8をスピンコードし
たのち、有機物質膜8の表面をその高低差に応じて選択
エツチングし該表面な略完全に平坦化しているので、有
機物質膜8L1−堆積されるA!膜9やレジスト10の
膜ItiT均一性および表面平坦性の大幅な向上をはか
り得る。
In this way, according to the method of this embodiment, the person 7-
After the organic material film 8 is spin-coded on the Si alloy film 67, the surface of the organic material film 8 is selectively etched according to the height difference, and the surface is almost completely flattened. -A deposited! It is possible to significantly improve the film ItiT uniformity and surface flatness of the film 9 and the resist 10.

このため、レジスト10の解像性を高めることができ、
&、#−8i合金膜6の加工精度向丘をはかり得る。ま
た、通常の3層構造方式の欧細ノ々ターン形成方法に比
して有機物’1tHIX8の膜厚を薄くすることができ
るので有機物質膜8に対するエツチング加工の交易化を
はかり寿る等の利点がある。
Therefore, the resolution of the resist 10 can be improved,
&, the machining accuracy of the #-8i alloy film 6 can be measured. In addition, since the film thickness of the organic material '1tHIX8 can be made thinner than in the conventional three-layer structure method of forming thin strips, the etching process for the organic material film 8 can be made more commercially viable. There is.

なお、本発明は上述した実施例に限定されるものではな
い。例えば、削記破加工物としては、A4−84合金膜
1;限るものではなく、多結晶シリコン膜、シリコン合
金膜、その他凹凸や段差を有する基板上に設けられた膜
であればよい。
Note that the present invention is not limited to the embodiments described above. For example, an A4-84 alloy film 1 may be used as an abrasion-broken workpiece, but the present invention is not limited to this, and may be a polycrystalline silicon film, a silicon alloy film, or any other film provided on a substrate having unevenness or steps.

さらに、配線加工に限定されるものではなく、r−)電
極形成工程、その他各種の半導体素子製造工程に適用す
ることができる。また、@記無機物質膜は人!膜に限定
されるものではなく、金属、金属酸化物、ガラス質材料
或いはシリコン化合物等であればよい。また、有機物質
膜としては、通常の一ノ型レジストであれば、フォトレ
ジストに限定されるものでなく、DeepUVレジスト
、ネガ型レジストも十分に調整された露光条件で処理で
きる。その池、本発明の。
Furthermore, the present invention is not limited to wiring processing, but can be applied to an r-) electrode formation process and various other semiconductor element manufacturing processes. Also, @Inorganic material membranes are people! The material is not limited to a film, and may be any metal, metal oxide, glassy material, silicon compound, or the like. Further, the organic material film is not limited to a photoresist as long as it is a normal one-type resist, and deep UV resists and negative resists can also be processed under well-adjusted exposure conditions. The pond, of the present invention.

要旨を逸脱しない範囲で、種々変形して実施することが
できる。
Various modifications can be made without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第8図はそれぞれ本発明の一実施例に係わる
MOS)ランジスタ製造工程を示す断面図である。 1・・・8Lウエーハ、2・・・フィールド酸化1換、
3・・・?−)酸化膜、4・・・多結晶シリコンゲート
、5・・・酸化膜、6・・・A7−8+合金膜(被加工
物)、7・・・ソース・ドレイン領域、8・・・有機物
質膜。 9・・・AA膜(無機物質膜)、10・・・レノスト。 出願人代理人  弁理士 鈴 江 武 彦、     
           (NW&         藪 0                寸w&     
    味
FIGS. 1 to 8 are cross-sectional views showing the manufacturing process of a MOS transistor according to an embodiment of the present invention. 1...8L wafer, 2...field oxidation 1 conversion,
3...? -) Oxide film, 4... Polycrystalline silicon gate, 5... Oxide film, 6... A7-8+ alloy film (workpiece), 7... Source/drain region, 8... Organic material membrane. 9...AA membrane (inorganic substance film), 10... Renost. Applicant's agent: Takehiko Suzue, patent attorney
(NW & Yabu 0 size w &
taste

Claims (1)

【特許請求の範囲】[Claims] 段差或いは凹凸を有する被加工物上(二有機物質膜を設
けたのちこの有機物質膜表面を選択エツチングし該表面
を高低差のない平坦面に加工し、次いで上記有機物質膜
上に無機物質膜およびレジストを順次設けたのち上記レ
ジストを所望)母ターンに露光現象し、その後1記レジ
ストをマスクとして1記無機物質膜をドライエツチング
し1次いでt記無機物質膜をマスクとして前記有機物質
膜をドライエツチングし、しかるのち1記有機物質膜を
マスクとして前記液加′工物をドライエツチングするこ
とを特徴とする微細ノfターン形成方法。
On a workpiece having steps or irregularities (two organic material films are provided, the surface of this organic material film is selectively etched, the surface is processed into a flat surface with no difference in height, and then an inorganic material film is formed on the organic material film). and a resist are sequentially provided, and then the above-mentioned resist (as desired) is exposed to light in the main turn.Then, the inorganic material film (1) is dry-etched using the resist (1) as a mask, and the organic material film is etched using the inorganic material film (1) as a mask. 1. A method for forming fine f-turns, comprising dry etching, and then dry etching the liquid-processed product using the organic material film as described above as a mask.
JP19216281A 1981-11-30 1981-11-30 Formation of microminiature pattern Pending JPS5893236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19216281A JPS5893236A (en) 1981-11-30 1981-11-30 Formation of microminiature pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19216281A JPS5893236A (en) 1981-11-30 1981-11-30 Formation of microminiature pattern

Publications (1)

Publication Number Publication Date
JPS5893236A true JPS5893236A (en) 1983-06-02

Family

ID=16286713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19216281A Pending JPS5893236A (en) 1981-11-30 1981-11-30 Formation of microminiature pattern

Country Status (1)

Country Link
JP (1) JPS5893236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9513551B2 (en) 2009-01-29 2016-12-06 Digiflex Ltd. Process for producing a photomask on a photopolymeric surface
CN109698121A (en) * 2018-12-27 2019-04-30 上海华力集成电路制造有限公司 The manufacturing method of integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9513551B2 (en) 2009-01-29 2016-12-06 Digiflex Ltd. Process for producing a photomask on a photopolymeric surface
CN109698121A (en) * 2018-12-27 2019-04-30 上海华力集成电路制造有限公司 The manufacturing method of integrated circuit

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