JPS5893217A - Manufacture of semiconductor crystal film - Google Patents

Manufacture of semiconductor crystal film

Info

Publication number
JPS5893217A
JPS5893217A JP56190620A JP19062081A JPS5893217A JP S5893217 A JPS5893217 A JP S5893217A JP 56190620 A JP56190620 A JP 56190620A JP 19062081 A JP19062081 A JP 19062081A JP S5893217 A JPS5893217 A JP S5893217A
Authority
JP
Japan
Prior art keywords
film
semiconductor
crystal
islands
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56190620A
Other languages
Japanese (ja)
Inventor
Tomoyasu Inoue
井上　知泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56190620A priority Critical patent/JPS5893217A/en
Publication of JPS5893217A publication Critical patent/JPS5893217A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make integrated circuits with less floating capacity by a method wherein a semiconductor film is patterned into the form of islands each including an opening and then an electron or laser beam is irradiated thereon to effect epitaxial growth sideward from the openings, thereby allowing all the islands to come into singlecrystals having the same orientation as the substrate. CONSTITUTION:An insulating film 2 is formed on a silicon substrate 1 by the normal method, and the film 2 is removed at the part where a crystal nuclears is to be formed, thereby to bore a crystal nuclears region 6. Then, a polycrystalline silicon film 3 is deposited thereon with the CVD process, and singlecrystal silicon islands 7 are formed on the film 3 in the shape of islands with the photo etching process. Then, an energy beams 4 such as an electron or laser beams are irradiated thereon the effect epitaxial growth sideward from each opening of the crystal nuclears region 6, so that all the islands 7 come into singlecrystals having the same orientation as the substrate. With this, it becomes possible to reduce floating capacity of integrated circuits.

Description

【発明の詳細な説明】 発明の属する技術４野 本発明は、多層半導体素子の製造方法に関わり、特に絶
縁膜上に下地半導体基板と同一の結晶面方位を有する半
導体単結晶領域を育成する半導体結晶膜の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a multilayer semiconductor device, and in particular to a method for manufacturing a semiconductor crystal for growing a semiconductor single crystal region having the same crystal plane orientation as a base semiconductor substrate on an insulating film. The present invention relates to a method for producing a membrane.

従来技術とその問題点 周知のように、半導体基板上に形成する半導体装置、特
に集積回路素子においては、酸化、拡散、イオン注入、
ＣｖＤ、写真蝕刻等の公知の技術を用いて、基板上に二
次元的に素子を配列させるものであった。そのため従来
の技術を用いて、半導体装置を＾集積化、高速化する事
には限界がある。Prior Art and its Problems As is well known, semiconductor devices formed on semiconductor substrates, especially integrated circuit elements, require oxidation, diffusion, ion implantation,
Devices were two-dimensionally arranged on a substrate using known techniques such as CvD and photolithography. Therefore, there are limits to increasing the integration and speed of semiconductor devices using conventional techniques.

この限界を打破する方法として素子を多層に積み重ねる
、所謂三次元集積回路が提案されておりそれを実現させ
るだめの基板材料として絶縁膜上の多結晶シリコンまた
は非品質シリコン層を、レーザー光や電子ビーム等のエ
ネルギービーム照射により、粗大結晶粒化または単結晶
化し、それを積層するものが有望視されている。A so-called three-dimensional integrated circuit, in which elements are stacked in multiple layers, has been proposed as a way to overcome this limit. A method in which coarse crystal grains or single crystals are formed by irradiation with an energy beam such as a beam, and the crystals are laminated is considered to be promising.

多層半導体素子に用いる基板材料の製造方法は現在迄に
幾つか提案されているが、その中で最も有望視されてい
るものにＬＥＳＳ法（Ｌａｔｅｒａｌ　Ｒｐｉｔａｘｙ
ｂｙ　Ｓｅｅｄｅｄ　Ｓｏｌｉｄｉｆｉｃａｔｉｏｎ）
がある。ＬＥＳＳ法は第１図に示す様に、シリコン基板
（１）上の絶縁膜（２）の一部を開孔し、その上に多結
晶せたは非晶質シリコン膜を堆積し、連続ビームのレー
ザー光または電子線を照射して、上記開口部で下地単結
晶シリコン基板との接触部を種結晶として、そこから横
方向に結晶成長させる。この場合開孔部から最大約１０
０μｍ程度、単結晶領域（３）が伸びて行く。Several methods for manufacturing substrate materials used in multilayer semiconductor devices have been proposed to date, but the most promising method is the LESS method (Lateral Rpitaxy).
by Seeded Solidification)
There is. As shown in Figure 1, in the LESS method, a hole is formed in a part of an insulating film (2) on a silicon substrate (1), a polycrystalline or amorphous silicon film is deposited on the hole, and a continuous beam is applied. A laser beam or an electron beam is irradiated to cause crystal growth in the lateral direction from the contact portion of the opening with the underlying single crystal silicon substrate as a seed crystal. In this case, a maximum of about 10
The single crystal region (3) extends by about 0 μm.

この方法の特長は前記、種結晶部分の位置の定め方によ
り単結晶領域を基板面内の希望する場所に作り得る事に
より、半導体素子を必らず単結晶領域の上に形成できる
事である。The advantage of this method is that, as mentioned above, by determining the position of the seed crystal portion, a single crystal region can be created at a desired location within the substrate surface, so that semiconductor elements can always be formed on the single crystal region. .

しかし、現在の技術では、種結晶部から横方向に伸びる
単結晶領域の長さには限りがあり、その長さは通常２〜
１００μｍであシ、それより離れた部分では、第１図に
示すように多結晶（５）となってしまう。半導体結晶膜
にトランジスタ等の能動素子群を作って集積回路を構成
する際、これらの能動素子は良好な電気的特性を得るた
めには、単結晶領域上に形成する必要があり、上記の多
結晶領域は除去するか、または別の目的に利用しなけれ
ばならない。その点、高速動作の集積回路を得るだめに
は、ＳＯ８（Ｓｉｌｉｃｏｎ　ｏｎ　５ａｐｐｂｉｒｅ
）素子技術と同様に、能動素子を形成する部分のみの半
導体層を／Ｎ、状に形成し、それ以外の部分の半導体層
は除去する事により素子間の浮遊容量を減少させる事に
効果があって好ましい。捷だ、このことは所謂、ランチ
アップ現象防止にも有効である。However, with the current technology, there is a limit to the length of the single crystal region extending laterally from the seed crystal part, and the length is usually 2 to 2.
The distance is 100 .mu.m, and the portions further away from this become polycrystalline (5) as shown in FIG. When constructing an integrated circuit by creating a group of active elements such as transistors in a semiconductor crystal film, these active elements must be formed on a single crystal region in order to obtain good electrical characteristics, and the above multilayer The crystalline regions must be removed or repurposed. In this regard, in order to obtain a high-speed operation integrated circuit, SO8 (Silicon on 5appwire)
) Similar to the device technology, forming the semiconductor layer only in the part where the active device is to be formed in a /N shape, and removing the semiconductor layer in the other part is effective in reducing the stray capacitance between the devices. It's good to have it. This is also effective in preventing the so-called lunch-up phenomenon.

発明の目的 本発明はこの様な点に鑑みてなされたもので、特性の優
れた半導体装置を得る事を目的とする。OBJECTS OF THE INVENTION The present invention has been made in view of the above points, and an object thereof is to obtain a semiconductor device with excellent characteristics.

発明の概要 即ち、予め多結晶或は非晶質のシリコン層を種結晶と々
るべき開口部から適切な距離までの領域の島に抜く工程
を経た後、ビームアニールする事により分離した単結晶
領域を形成する半導体結晶膜の製造方法を提供するもの
である。Summary of the invention: A polycrystalline or amorphous silicon layer is separated into single crystals by beam annealing after a process of cutting a polycrystalline or amorphous silicon layer into islands at an appropriate distance from the opening where the seed crystal is to be placed. A method of manufacturing a semiconductor crystal film forming a region is provided.

発明の効果 本発明によれば、多結晶の混在することのない単結晶半
導体層を得る事が出来、しかも素子間の浮遊容量を減少
させる事が出来るので特性の優れれ半導体装置を得る事
が出来る。Effects of the Invention According to the present invention, it is possible to obtain a single crystal semiconductor layer without the presence of polycrystals, and in addition, it is possible to reduce the stray capacitance between elements, thereby making it possible to obtain a semiconductor device with excellent characteristics. I can do it.

又、（−１ｅやスズ等、半導体膜と同族元素の不純物を
ドープしておいてビームアニールすれば、素子特性に全
んど影響を与える事なく速やかに単結晶化を行なう事が
出来、良質な単結晶を大面積に亘って得る事が出来る。Furthermore, if the semiconductor film is doped with an impurity of an element in the same group as the semiconductor film, such as tin, and then subjected to beam annealing, single crystallization can be quickly performed without affecting the device characteristics at all, resulting in high quality. It is possible to obtain a single crystal over a large area.

発明の実施例 以下本発明の実施例を図面を用いながら説明する。Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

第２図、紀３図はそれぞれ本発明による単結晶領域の断
面図と上面図である。まず、シリコン基板（１）の上に
通常の工程により、シリコン酸化膜（ａを形成した後、
種結晶とすべき場所のシリコン酸化膜（２）を写真蝕刻
法により除去して開口部（６）を形成する。次に多結晶
シリコン膜（３）を減圧ＣＸｒＤ法により堆積し、写真
蝕刻法により第３図の様に多結晶シリコン膜を島状（７
）に単結晶化し得る最大領域になる如く形成した。シリ
コン酸化膜（２）と多結晶シリコン膜（３）の厚みはそ
れぞれ０．５μｍと０．３μｍである。シリコン島の幅
（Ｗ）゛は２００／１ｍ、長さくＬ）は５籠であった。FIGS. 2 and 3 are a cross-sectional view and a top view, respectively, of a single crystal region according to the present invention. First, after forming a silicon oxide film (a) on a silicon substrate (1) by a normal process,
The silicon oxide film (2) at the location to be used as a seed crystal is removed by photolithography to form an opening (6). Next, a polycrystalline silicon film (3) is deposited by low pressure CXrD method, and by photolithography, the polycrystalline silicon film (3) is deposited in the form of islands (7
) was formed so as to have the maximum area that could be made into a single crystal. The thicknesses of the silicon oxide film (2) and the polycrystalline silicon film (3) are 0.5 μm and 0.3 μm, respectively. The width (W) of the silicon island was 200/1 m, and the length L) was 5 cages.

次に、電子ビームアニールにより表面近傍を加熱して横
方向結晶成長させた。電子ビームの加熱′直圧はｌ０Ｋ
Ｖ１　ビーム電流２ｍＡ、ビーム径約１００μｍである
。電子線は図に示す様に種結晶部からシリコン島の幅方
向に平行に走査させ、走査速度５０　ｏＪ　ｓ　でラス
タースキャンさせて照射した。この結果、全てのシリコ
ン島は下地基板と同一面方位の単結晶膜となった。Next, the vicinity of the surface was heated by electron beam annealing to cause lateral crystal growth. The direct pressure of electron beam heating is l0K
V1 beam current is 2 mA, beam diameter is approximately 100 μm. As shown in the figure, the electron beam was scanned parallel to the width direction of the silicon island from the seed crystal portion, and irradiated by raster scanning at a scanning speed of 50 oJ s. As a result, all the silicon islands became single crystal films with the same plane orientation as the underlying substrate.

本実施例では電子ビームアニール法による単結晶化を示
したが、ＣＷ発振レーザーアニールでも同等の効果が得
られる。捷た、本実施例では多結晶、或は非晶質シリコ
ン膜の形成に減圧ＣｖＤを用いたが、スパッタリング、
イオンビームデボジシラン、超高真空中での蒸着等を用
いても同等の効果が得られる。In this example, single crystallization was performed by electron beam annealing, but the same effect can be obtained by CW oscillation laser annealing. In this example, low pressure CvD was used to form a polycrystalline or amorphous silicon film, but sputtering,
Similar effects can be obtained by using ion beam devodisilane, vapor deposition in an ultra-high vacuum, or the like.

シリコン島の大きさについては、本実施例では長さを５
　ｍｍとしたが、さらに基板の表面温度均一性やアニー
ル条件の安定性を高める事により３０〜ｂ　Ｏｍｍ程度
まで大きくする事が可能になる。また、シＩＪコン島の
幅についても、本実施例では１００μｍとしたが、前記
の工夫に加え、シリコン膜へ不純物の適切なドーピング
や予備加熱手段（他のエネルギービームを重畳したり基
板温度を高める等）の採用等により５〜５０１ｍ程度捷
で大きくする事も可能となる。ドーピングは、Ａ、ｓ　
＋Ｐ等の活性不純物であっても良いが、Ｇｅ、スズ等Ｓ
ｉと同族元素を半導体被着中又は被着後に１０１９〜１
０２２／ａｒｉ’ドーピングし、しかる懐エネルギービ
ームでアニールずれｅ」、結晶化か早ブリ、均一で大面
積の単結晶膜を得る事が出来る。しかも同族元素である
ので、膜甲にＭＯＳトランジヌタや抵抗米子等を形成し
ても集子特性には全んど影響を与えない。ドーピングは
半専体膜中の全面に行なっても良いし、開口から遠い部
分のみに施しても良く、又、開口から離１しるに従って
次第に謎くなる様に行なう事も出来る。Regarding the size of the silicon island, in this example, the length is set to 5.
However, by further improving the uniformity of the surface temperature of the substrate and the stability of the annealing conditions, it is possible to increase the thickness to about 30 to b Omm. In addition, the width of the silicon IJ island was set to 100 μm in this example, but in addition to the above measures, appropriate doping of impurities to the silicon film and preheating means (superimposing other energy beams or controlling the substrate temperature) It is also possible to increase the size by about 5 to 501 m by adopting a method such as increasing the height. Doping is A, s
It may be an active impurity such as +P, but it may also be an active impurity such as Ge, tin, etc.
i and homologous elements during or after semiconductor deposition 1019-1
022/ari' doping and annealing with an appropriate energy beam, crystallization or premature brittleness occurs, making it possible to obtain a uniform, large-area single crystal film. Moreover, since they are homologous elements, even if MOS transistors, resistors, etc. are formed on the membrane shell, the collector characteristics are not affected at all. The doping may be carried out over the entire surface of the semi-dedicated film, or it may be carried out only in a portion far from the opening, or it may be carried out in such a manner that the doping gradually becomes more mysterious as the distance from the opening increases.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はエネルギービーム照射による単結晶膜の形成過
程を説明する断面図、第２図は、本発明による単結晶シ
リコン島形成過程を説明する断面図、第３図は、本発明
による単結晶シリコン膜の上面図である。 図に於いて、 １・・・シリコン基板　　２・・・絶Ｒ膜３・・・単結
晶シリコン膜　４・・・エネルギービーム５・・・多結
晶ミリコン膜　６・・・柚結晶領域７・・・単結晶シリ
コン島 ８・・・エネルギービーム走査方向 Ｗ・・・シリコンｈの幅　Ｌ・・・シリコン島の長さ第
１図 ／〜４ Ｉ４２図 第３図FIG. 1 is a cross-sectional view explaining the process of forming a single crystal film by energy beam irradiation, FIG. 2 is a cross-sectional view explaining the process of forming a single crystal silicon island according to the present invention, and FIG. FIG. 3 is a top view of a silicon film. In the figure, 1...Silicon substrate 2...R film 3...Single crystal silicon film 4...Energy beam 5...Polycrystalline silicon film 6...Yuzu crystal region 7...・Single crystal silicon island 8...Energy beam scanning direction W...Width of silicon h L...Length of silicon island Figure 1/~4 Figure I42 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）単結晶半導体基板表面に絶縁膜を被着し、該絶縁
膜の一部を除去して開口させ、その上に多結晶或は非晶
質の半導体膜を被着した後、該半導体膜を、開口部を含
む犬゛きさの島状にパターンニングした後、電子ビーム
或はレーザー光照射する事により、上記開口部から横方
向にエピタキシャル成長させてシリコン島全体を下地半
導体基板と同一面方位の単結晶化させる事を特徴とする
半導体結晶膜の製造方法。(1) After depositing an insulating film on the surface of a single-crystal semiconductor substrate, removing a portion of the insulating film to create an opening, and depositing a polycrystalline or amorphous semiconductor film thereon, the semiconductor After patterning the film into a dog-sized island including an opening, irradiation with an electron beam or laser beam causes epitaxial growth in the lateral direction from the opening, making the entire silicon island identical to the underlying semiconductor substrate. A method for manufacturing a semiconductor crystal film characterized by making the plane orientation single crystal. （２）半導体膜に該半導体膜と同族元素をドーピングし
ておく事を特徴とする特許 １項記載の半導体結晶膜の製造方法。(2) The method for manufacturing a semiconductor crystal film described in Patent No. 1, characterized in that the semiconductor film is doped with an element of the same group as the semiconductor film.
JP56190620A 1981-11-30 1981-11-30 Manufacture of semiconductor crystal film Pending JPS5893217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190620A JPS5893217A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor crystal film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190620A JPS5893217A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor crystal film

Publications (1)

Publication Number Publication Date
JPS5893217A true JPS5893217A (en) 1983-06-02

Family

ID=16261096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190620A Pending JPS5893217A (en) 1981-11-30 1981-11-30 Manufacture of semiconductor crystal film

Country Status (1)

Country Link
JP (1) JPS5893217A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257718A (en) * 1986-04-30 1987-11-10 Sony Corp Solid phase epitaxy of semiconductor thin film
JPS63257214A (en) * 1987-04-14 1988-10-25 Sony Corp Manufacture of semiconductor substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5667923A (en) * 1979-11-07 1981-06-08 Toshiba Corp Preparation method of semiconductor system
JPS56126915A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5667923A (en) * 1979-11-07 1981-06-08 Toshiba Corp Preparation method of semiconductor system
JPS56126915A (en) * 1980-03-11 1981-10-05 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62257718A (en) * 1986-04-30 1987-11-10 Sony Corp Solid phase epitaxy of semiconductor thin film
JPS63257214A (en) * 1987-04-14 1988-10-25 Sony Corp Manufacture of semiconductor substrate

Similar Documents

Publication Publication Date Title
EP0073487B1 (en) Method for manufacturing three-dimensional semiconductor device
US4874718A (en) Method for forming SOI film
JP4203141B2 (en) Method for crystallizing amorphous silicon layer and method for producing thin film transistor using the same
US20020115246A1 (en) Method for crystallizing silicon film and thin film transistor and fabricating method using the same
JPS5939790A (en) Production of single crystal
JPS62160712A (en) Manufacture of semiconductor device
JPS5893217A (en) Manufacture of semiconductor crystal film
JPS5893220A (en) Preparation of semiconductor single crystal film
JPS5856322A (en) Manufacture of semiconductor substrate
JPS5840852A (en) Complementary metal oxide semiconductor device and its manufacture
JPH0332208B2 (en)
JPH04206932A (en) Semiconductor device and manufacture thereof
JPS5840851A (en) Complementary metal oxide semiconductor device and its manufacture
JPS5939791A (en) Production of single crystal
JPH0368532B2 (en)
JPS5880831A (en) Manufacture of substrate for semiconductor device
JPS6191917A (en) Manufacture of semiconductor thin film crystal
JPH01264215A (en) Manufacture of semiconductor device
JPH0810669B2 (en) Method of forming SOI film
JPS58180019A (en) Semiconductor base body and its manufacture
JPH0257337B2 (en)
JPS63300510A (en) Laminated semiconductor device
JPH0732121B2 (en) Method for manufacturing semiconductor device
JPS5892209A (en) Manufacture of semiconductor device
JPS5837951A (en) Manufacture of multi-layer semiconductor element