JPS5890192A - Electronic clock - Google Patents

Abstract

PURPOSE:To enable the accurate adjustment of a watch error by providing an oscillation circuit with a circuit generating a conditional control signal at the time of a watch error adjustment mode. CONSTITUTION:One end of a crystal resonator 41 is connected to the input of an inverter 42, and the other end thereof to the output of the inverter 42 through the intermediary of an output resistor 42. Moreover, both ends of the resonator 41 are earthed via capacitors 44 and 45 respectively, the input and output of the inverter 42 are connected to each other by a feedback resistor 46, and a clocked inverter 47 is connected in parallel to the inverter 42. A control signal of the inverter 47 is made to be a signal obtained by a method wherein a signal A generated at the time of a fall of a supply voltage and the operation of an alarm, etc. is multiplied logically in an AND circuit 48 by a signal obtained by passing through an inverter 49 a watch error adjustment mode signal generated at the time of a watch error adjustment mode.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece capable of accurate rate adjustment.

(2) Prior Art FIGS. 1 and 2 show the oscillation circuit of a conventional electronic watch. One end of the co-crystal resonator 11 in FIGS. 1 and 2 is an inverter 12.
The other end is connected to the output of the inverter 12 via the output resistor 13. Still crystal resonator 11
Both ends of are grounded via capacitors 14 and 15, respectively. Also, a feedback resistor 1 is connected between the input and output of the inverter 12.
6. Figure 1 shows this inverter 1.
A clocked inverter 17 is connected in parallel to 2. The clocked inverter 17 is controlled by a control signal. Figure 2 shows a circuit that switches the power supply of the inverter 12, and there is no parallel inverter.
The control signal also goes to the crystal resonator 1 with the above configuration.
The basic clock signal excited to match the natural frequency of 1 is taken out as the output of the inverter 12. This is frequency-divided by a subsequent frequency dividing circuit to create a unit clock signal of unit frequency. The clock in/out shown in FIG. 1 and the power supply switching shown in FIG. 2 operate temporarily when the battery voltage drops, and are controlled by the control signal A. As a rate adjustment mechanism for correcting the deviation of the basic taro clock signal of such an electronic clock, there are two methods: attaching capacitors 14 and 15 externally to the circuit and trimming them, and using a frequency dividing circuit to adjust the specific clock signal. There are methods of adjusting the step IW by adding and subtracting.

(3) Problems with the Prior Art In the oscillator circuit of a conventional electronic timepiece, the clock function and the power supply switching circuit may operate even when the rate is being adjusted. In other words, a clocked inverter operates together with a normal inverter when the power supply voltage drops, but it also operates when it is affected by other noises or when an alarm etc. The oscillation frequency when the oscillation frequency is applied is different from normal because the 9m of the circuit changes.One more anastomosis of the power supply switching circuit is that when the power supply voltage drops, the oscillation circuit power supply voltage changes from the 1.5V system to the 1.5V system. The system switches to 3V. This voltage change affects the oscillation frequency of the oscillation circuit and changes it by l-. FIG. 3 is a graph showing the relationship between the power supply voltage of the oscillation circuit and the deviation in the oscillation frequency.

The frequency when the voltage is 1.5V is f = 32.768 KH
Adjust so that △f with z becomes almost 0. In this state, the pressure is 3. When changing to Ov, △f becomes almost 10 (0
It can be seen that [)M) also changes. Therefore, if the rate adjustment is performed during operation of the clocked inverter and the power supply switching circuit, the frequency will be adjusted to a wrong frequency, and there is a problem in that accurate rate adjustment cannot be performed.

(4) Purpose of the Invention An object of the present invention is to overcome the problems of the conventional art and provide an electronic timepiece that can accurately adjust the rate.

(5) Structure of the Invention The present invention comprises an oscillation circuit that generates a basic clock signal, a frequency division circuit that divides the basic clock No. 1g generated from the oscillation circuit, and a unit frequency-divided by the frequency division circuit. An electronic timepiece comprising a counter that counts clock signals, a display section that displays time according to a signal from the counter, and a rate adjustment circuit that adjusts a deviation of the basic clock signal, wherein the oscillation circuit is a crystal resonator. , an inverter whose input part is connected to one end of the crystal resonator, an output resistor connected between the output part of this inverter and the other end of the crystal resonator, and a ground potential between both ends of the crystal resonator. an inverter operated by a control signal is connected in parallel to the inverter; Alternatively, a circuit including a circuit for switching the power supply of the inverter according to a control signal, and these circuits are included in step 11! It is characterized by comprising a logic circuit that conditions the 9j control so that it does not operate in the mode using the adjustment means.

(6) Embodiments of the Invention An embodiment of the electronic timepiece of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing the overall configuration. First, the oscillation circuit 31 generates a basic clock signal of 32.768 KF (z). This signal is frequency-divided by the frequency dividing circuit 32 and becomes a clock signal for one city. Based on this l Hz clock signal, the second Counter 339 minutes □ Counter 34 and hour counter 35 each indicate 1 minute per second.

The time is counted and displayed on the display section 36. The rate adjustment circuit 37 controls the frequency dividing circuit 32 to add and subtract appropriate pulses to adjust the rate. At the same time, a signal indicating the rate adjustment mode is sent to the oscillation circuit 31 to control the clocked inverter so that it does not operate.

FIG. 5 is a detailed diagram of the oscillation circuit. One end of the crystal resistor 41 is connected to an input of an inverter 42, and the other end is connected to an output of the inverter 42 via an output resistor 43.

Both ends of the crystal resonator 41 are still connected to capacitors 44.
It is grounded via 45. One input and one output of the inverter 42 are still connected through the feedback resistor 46. A clocked inverter 47 is connected in parallel to this inverter 42. The signals that control the clocked inverter 47 are a control signal A that is established when the power supply voltage drops or an alarm is activated, and a rate adjustment mode signal B that is established when the rate adjustment mode is entered, through the inverter 49. This is a signal obtained by logically multiplying the signal and the signal as input to the AND circuit 48.

The above circuit configuration normally generates a square wave with a frequency of 32.768 KHz as the output of the inverter 42.

Furthermore, if there is a drop in the source can pressure, etc., the clocked inverter 47 operates to compensate for the inverter 42, but when the rate and the 11-order mode signal B are established, the control signal The clocked inverter 47 cannot operate regardless of whether or not a person is present. Therefore, there is no fear that the gm of the oscillation circuit will fluctuate due to the addition of a clocked inverter when in the walk adjustment mode, and the walk If can be adjusted at a ratio of 1 to the fundamental frequency in the steady state.

, Fig. 6 shows a frequency dividing circuit and a rate adjusting circuit. The frequency dividing circuit is composed of 14 stages of binary counters 13C1 to 13C14. 3 generated in the oscillation circuit 2.7
The 68 KHz basic clock signal is
It passes through a counter and becomes a unit clock signal of IHz.

A rate adjustment circuit for this frequency dividing circuit is configured as follows. The outputs of ANI) circuits 51 and 52 are connected to the cent terminals of binary counters BC1 and BO2, and the AND terminals are connected to the reset terminals of binary counters BC3 and BO2.
The outputs of the circuits 53 are commonly connected. As will be explained later, the lead/lag of the frequency dividing circuit is adjusted by setting and resetting these binary counters BCI to BC4.

The AND circuits 51 to 53 receive a rate adjustment instruction signal 1]T1.
-DT3 are respectively input, and at the same time, a common timing signal φB is input. Signals 1) Tl to DT3 indicate the magnitude of rate adjustment, and are sent from external terminals to the inverter 5.
4 to 56 are input. Timing signal φB is the output of NOR circuit 57. The input of the NOR circuit 57 is the timing signal φA and the inverted signal of φ.
Kl (This is the data signal of the shift register SR that is output at the rising edge of the clock signal of z. In other words, the shift register SR has a clock signal of 32.768 Kl (z) as the φ input, the timing signal φA, f as the data input, and the data Output Q is sent to Ail NO1% circuit 57. Timing signal φA is output from inverter 58 to QR.

The input of the inverter 58 is the output of the NOR circuit 59. The input of the NOR circuit 59 is a signal obtained by inverting the pulse φ103 that rises once every 10 seconds using an inverter 61.
N0I (is the output of the circuit 60).The inputs of the NOR circuit 6o are the output of the NOROR circuit and a 4,096 KHz clock signal frequency-divided by the binary counters BCI to BC3.

Next, the operation of this circuit will be explained using the timing charts shown in FIGS. 7(a) to 7(d). FIG. 7(a) shows the instruction M
No. DT t~D'ra='t (VDD V Hell) (1) 'ih combination, and at this time, the step [X11 adjustment is not performed. The pulse φ108 is a pulse that rises once every 10 seconds, and its width should be at least one cycle of the 4 fG (z signal). This pulse φ105 and the 4KHz signal are connected to the NOR circuit 59.60 and the inverter 58.61 The signal φA is normally logic 1, so when the pulse φ103 is rising, it becomes the timing signal φ.
2 becomes logic 0 only when the signal becomes logic 1. This 4g No. φN is transferred to shift register SR, and N
By passing it through OR circuit 57, timing signal φB is obtained. This signal φB is normally at logic O, and φN is at logic O.
When it reaches K, it rises and becomes logic 1 + 32 K
It is a pulse signal that becomes a logic 0 in half a cycle of the Hz signal. In FIG. 7(a), I)'rl~DT3=1
Therefore, the signal passing through inverters 9 to 11 is logic O.
Therefore, regardless of the value of φB, the signal passing through the AND circuits 51 to 53 becomes logic 0, and the binary counters BCI to B
C4 is not affected. Next, the case of DTI~D'['320 will be explained using FIG. 7(b). In this case, AN
All D circuits 51 to 53 output the timing signal φB as is. Therefore, when the signal .phi.B becomes logic 1, the binary counters 1-3C1 and BO2 are set, and the output signal becomes logic 1 unconditionally. Furthermore, the binary counters BC3 and BC4 are in a reset state, and their outputs become logic O unconditionally. Result 1 (8K in '5.

and 4Ki (the rise and fall of the output signal of z, and 32
In the end, the clock signal is also delayed by one cycle of 32 Kf-Iz. Figure 7 (c) [1IT
l=l) T3=1 tef) T2=0 (This is case D.

In this case, only the binary counter BC2 is in the set state, and the output signal advances by 2 periods of 32 Kl (z.
1') This is the case when T 3 = O. In the case of ・Only the secondary counter 13C3 is in the reset state and 32
Kl(4 periods of z are generated in the mouth.The above relationship is expressed as the first
They are summarized in the table.

As shown in Table 1 below, it is possible to adjust the rate of ±3P-PM in the minimum width, and the adjustment width can be freely changed depending on the number of stages of the frequency dividing circuit to be set.

FIG. 8 is an example of a circuit that allows a watch user to adjust the advance or lag of the watch. Rate adjustment instruction signal 1) The levels of T1 to DT3 are controlled by the output of the up/down counter 71. The up/down counter 71 receives an up clock signal from the switch S1 via the AND circuit 72, and
The down clock signal from switch S2 is sent to AND circuit 7.
After 3 steps, it will be done manually. The mode signal M defining the rate adjustment mode is still input to the AND circuits 72 and 73. In this circuit, when the rate adjustment mode is established, 81
If you use human power, 1) TI by up clock signal,
DT2.

1) The value of T3 is adjusted in the filling direction, and if 82 manpower is used, the down clock 1 signal will shift it in the forward direction.

With the above-described circuit configuration, this embodiment can adjust the rate in a very precise manner. This method is much easier than trimming an external capacitor, and adjustments can be made even after the product is completed. - Also, since there is no need to attach an external capacitor, space can be reduced.

When in rate adjustment mode to perform rate adjustment, the oscillation circuit does not operate the clocked inverter or switch the power supply, so there is no fear that the oscillation frequency of the oscillation circuit will fluctuate. Accurate rate adjustment is possible.

[Brief explanation of drawings]

Figures 1 and 2 are conventional oscillation circuit diagrams, Figure 3 is a graph showing the relationship between the power supply voltage of the oscillation circuit and the deviation in oscillation frequency, Figure 4 is a block diagram according to the present invention, and Figure 5 6 is a detailed oscillation circuit diagram according to the present invention, FIG. 6 is a frequency division circuit diagram and rate adjustment circuit diagram used in the present invention, and FIG. 7(a)
~(d) is a timing waveform diagram provided for explanation of FIG. 6,
FIG. 8 is a circuit diagram for adjusting the time delay. 31... Oscillation circuit 32... Branch circuit 33...
・Second counter 34...Minute counter 35...Hour counter 36...Display section 37...Rate adjustment circuit 4
1...Crystal common loss element 42...Inverter 43...
・Output resistance 44.45...Capacitor 46...
Feedback resistor 47... Clocked inverter 48...
... AND circuit 49... Inverter (7317) Agent Patent attorney Norichika Kensuke (and one other person) Figure 4 M1 Figure 75〈 4f 箪 Figure 6

Claims (1)

[Claims] an oscillation circuit that generates a basic clock signal; a dividing circuit that divides the frequency of the basic clock signal generated from the oscillation circuit; a counter that counts unit clock signals divided by the frequency dividing circuit; In the electronic timepiece, the oscillation circuit has a crystal resonator, and the input part is connected to one end of the crystal resonator. an inverter connected to the inverter; an output resistor connected between the output of the inverter and the other end of the crystal resonator; a capacitor connected between both ends of the crystal resonator and ground potential; A circuit in which an inverter operated by a control signal is connected in parallel to the inverter in a circuit consisting of a feedback resistor connected between the input part and the output part of the inverter, or the power supply of the inverter is switched by the control signal. 1. An electronic timepiece comprising: a circuit including a circuit; and a logic circuit that conditions the control signal so that the circuit does not operate in a mode using the rate adjustment means.