GB2036387A

GB2036387A - Electronic Timepiece

Info

Publication number: GB2036387A
Application number: GB7936416A
Authority: GB
Original assignee: Ebauches SA
Current assignee: Ebauches SA
Priority date: 1978-11-24
Filing date: 1979-10-19
Publication date: 1980-06-25
Also published as: FR2442468B1; GB2036387B; DE2943303A1; CH624536GA3; HK24888A; CH624536B; FR2442468A1; DE2943303C2; JPS5582087A; JPS631553B2

Abstract

An electronic watch comprises a stepping motor 6 for driving a mechanism for displaying the time information, a quartz crystal controlled oscillator 1, a frequency divider 2 with an adjustable division ratio, a circuit 7 for adjusting the division ratio eg by suppressing a number of pulses from the oscillator to the divider, a memory 8 containing data corresponding to the number of the pulses to be suppressed in each adjusting, cycle and a logic circuit 10 which, in response to an interrogation signal, (switch 9) produces a measuring signal at the output of gate 19 which is supplied to the coil of the stepping motor and which comprises a series of pulse trains whose distribution is representative of the division factor and the frequency of the oscillator and whose duration is sufficiently short so as not to cause the motor to rotate and sufficiently long to cause a magnetic stray field from the motor which can be detected by an external apparatus for measuring therefrom the rate of the watch. The interrogation signal upon closure of switch 9 causes the divider to divide with its unadjusted value. A gate 11 is enabled by 1 Hz pulses at 11a to pass trains of 256 Hz pulses in alternate half quartz-second intervals. The pulses pass through the gate 19 until their number, counted by counter 17, equals the adjustment number eg 5 held in memory 8. The interrogation signal also acts on switch circuit 4 to disconnect the motor control inputs at 4a 4b of circuit 5 from the divider 2, and apply the measuring signal pulses at input 4e from the gate 19 instead. In the embodiment described, a "quartz-second" is shorter than a normal second, the watch crystal frequency being higher than a nominal frequency, alternatively the measuring signal may be transmitted acoustically. The external measuring apparatus is described in App No. 79/36415. <IMAGE>

Description

SPECIFICATION Electronic Timepiece The present invention concerns an electronic timepiece comprising an oscillator used as a time base and a frequency divider with an adjustable division factor.

For the purposes of measuring the rate of watches of this kind, use is made of apparatuses which detect the magnetic stray field of the coil of the stepping motor, and which precisely measure the time which elapses between two drive pulses. These apparatuses rapidly give the required measured result when the drive pulses are separated by short periods of time, for example a second. On the other hand, in the case of watches which do not have second hands and in which the drive pulses may be spaced at from 10 or 20 seconds or even a minute, the rate measuring time is much longer.

U.S. Patent Specification No. 3,998,044 discloses apparatus which makes it possible to shorten the time required for measuring the rate of such watches, by supplying their motor with pulses which are produced by an intermediate stage of the frequency divider and which are sufficiently short for them not to cause the motor to react, which being of a sufficiently high frequency for the measuring time to be short. However, such apparatus cannot be used for watches in which the frequency divider has an adjustable division factor. In such watches, which are described for example in Swiss Patent Specifications Nos. 534 913 and 558 559, pulses are suppressed or added at certain positions in the division chain in the course of each adjustment cycle, which cycle may last up to 64 seconds.The result of this is that, in the course of one of the adjustment cycles, the time between two successive drive pulses is not constant.

In order to be certain of correctly determining the rate of the watch, it is therefore necessary to compute the mean time which elapses between two drive pulses from the measured values of the time which elapses between each pulse appearing for a period of time which is at least equal to an adjustment cycle. The difficulty with such measurement operations is that nothing indicates the commencement or the end of an adjustment cycle.

The object of the present invention is to overcome these problems, in particular by providing a timepiece with means for delivering to its motor signals such that they do not cause the motor to react but that they make it possible for the rate of the watch to be rapidly and accurately measured, taking account of the real frequency of the oscillator and the division factor of the frequency divider.

According to the present invention, there is provided an electronic timepiece comprising an oscillator used as a time base, a frequency divider with an adjustable division factor coupled to the oscillator, a circuit for adjusting the division factor, a memory which is associated with the adjusting circuit and whose state represents the magnitude of the adjustment, a transducer responsive to a signal generated in the timepiece to emit a wave which can be detected by an outside apparatus for measuring the rate of timepieces, a logic circuit which responds to the states of the memory and the divider to produce a measuring signal comprising pulses whose distribution is representative of the division factor and the frequency of the oscillator, and a change-over switching means for applying the measuring signal to the-transducer in response to an interrogation signal.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows the block circuit diagram of an embodiment of the invention; Figure 2 is a diagram illustrating the mode of operation of the circuit of Figure 1; and Figure 3 is a diagram of a detail of the circuit of Figure 1.

For the purposes of simplifying the description, the following abbreviations will be used: Logic states 0 and 1: '0' and '1' respectively D-type flip-flop: FF Monostable multivibrator: MONO Reset: RAZ Inputs and outputs of circuit elements are denoted by the reference numeral of the element followed by a letter.

In addition, the term 'quartz second' will be used to denote a period of time which is equal to a second of real time, multiplied by the quotient of the nominal frequency and the real frequency of oscillation of the quartz of the watch in question.

An embodiment of the invention is illustrated by means of the circuit of Figure 1, which comprises a quartz oscillator 1 supplying pulses at a frequency for example of 32,768 Hz, with a positive or negative tolerance of the order of 1 per 100,000 (this being a value which is generally achieved in manufacture), to a frequency divider 2 which has an adjustable division factor and which is provided for reducing the frequency of the pulses supplied by the oscillator to a precise frequency of for example 1 Hz. A circuit 3 for shaping the drive pulses is connected to the output of the divider; the two outputs of the shaper circuit 3 are connected to the inputs 4a and 4b of a change-over switching circuit 4 whose two outputs 4h and 4j are connected to a control circuit 5 for supplying drive pulses to the coil of a stepping motor 6 which drives a display mechanism (not shown here).

A circuit 7 for adjusting the division factor is connected to the frequency divider 2. Such a circuit 7 is known in particular from above-mentioned Swiss Patent No. 534 91 3 which describes an adjustment circuit intended to suppress a certain number of pulses, from the pulses which are supplied by the oscillator, for a given period of time. In this case, the frequency of the oscillator is deliberately selected at an excessively high value.

Swiss Patent No. 558 559 describes another system in which the adjusting circuit adds pulses to those supplied by the oscillator or, which comes to the same thing, periodically reduces the division factor of the frequency divider for a given period of time. This makes it possible to use a quartz oscillator whose frequency is lower than the nominal frequency.

Irrespective of the system in question, the adjusting circuit 7 is connected to a memory 8 which contains data concerning the magnitude of the adjustment to be made. The memory may be in various forms and in particular may comprise electronic components.

The watch is provided with a stem for setting the time (not shown), which may assume three axial positions: in the inwardly displaced position or position 1, the stem is inactive; in the middle position or position 2, it makes it possible to move the hands in order to set the time on the watch; while in the completely pulled position or position 3, the stem acts on an interrogation means 9 which is shown in Figure 1 by a switch connected between the positive terminal of the battery which supplies the motor and by way of adaptation or matching circuit (not shown), the inputs 4k of the switching means 4 and 71 of the adjusting circuit 7.

A logic circuit 10 is provided with inputs 1 0a and 1 Ob which are respectively connected to the outputs 2c and 2d of the divider 2, a plurality of inputs 1 Oc connected to the outputs 8m of the memory 8 and an output 1 Od connected to the information input 4e of the switching circuit 4.

The logic circuit 10 comprises elements 11 to 1 9 which will be described hereinafter.

The inputs 1 Oa and 1 Ob are connected to the inputs 11 a and 11 b respectively of an AND-gate 11.

The inputs 1 0c are connected to the inputs 1 6a of a comparator 1 6 whose inputs 1 6b are connected to the outputs 1 7a of the division stages of a counter 1 7. The output 16c is connected to the clock input 1 8a of a FF18. The non-inverted output Q and the inverted output Q of the FF18 are respectively connected to the resetting input 1 7RAZ of the counter and to the input 1 9a of an ANDgate 1 9. The resetting input 1 8RAZ is connected to the input 11 b of the gate 11. The output 11 c of the gate 11 is connected on the one hand to the clock input 1 7CL of the counter and on the other hand to the input 1 9b of the gate 19. The output 1 9c is connected to the output 1 Od of the logic circuit 10.

The mode of operation of the frequency divider 2 which has an adjustable division factor, the adjusting circuit 7 for adjusting the division factor of the frequency divider and the memory 8 are described in above-mentioned Swiss Patents Nos. 534 913 and 558 559. It may simply be noted that the adjusting circuit 7 receives at its input 7f from the divider 2, data concerning the duration of the adjusting cycle, while at its input 79 the adjusting circuit 7 receives data concerning the magnitude of the adjustment in respect of the division factor, which data are contained in the memory 8 in the form of a number whose unit at least approximately corresponds, in the example described, to a correction of one tenth of a second per day in the rate.of the watch.

The shaper circuit 3 uses the signals supplied by the divider 2 in order to produce a pulse each second laternately at one and the other of its outputs. Under normal circumstances, the pulses occur at the outputs of the circuit 4 and are used by the control circuit 5 in order to supply the motor 6 with the alternate drive pulses which cause it to move forward by one step per second. The shaper circuit 3 is well known and will not be described in detail herein.

Figure 3 shows a circuit diagram of the switching means 4 of Figure 1, which is disposed between the shaper circuit 3 and the control circuit 4.

The first output 3a of the shaper 3 is connected to a first input 4a of the switching means 4 which is connected to the input 21 b of an AND-gate 21 whose other input 21 a is connected to the output of an inverter 22. The second output 3b of the shaper 3 is connected to a second input 4b of the switching means 4 which is connected to the input 23b of an AND-gate 23 whose other input 23a is also connected to the output of the inverter stage 22. The data input 4e is connected to the input 24a of an AND-gate 24 whose other input 24b is connected to the control input 4k of the switching means 4. The input 4k is also connected to the input of the inverter 22. The outputs of the gates 21 and 24 are respectively connected to the inputs 25a and 25b of an OR-gate 25 whose output 25c is connected to the output 4h and thence to one of the inputs (G3) of the control circuit 5. The output 23c of the gate 23 is connected to the output 4j and to the other input of the circuit 5.

When the stem of the watch is in position 1 or position 2, the switch 9 is open and the input 4k of the switching means 4 is at logic state '0'. Consequently, the same logic state also occurs at the input 24b of the gate 24, preventing the signal at the input 4e from reaching the input 25b of the gate 25.

The input of the inverter 22 also being at '0', its output is then at logic state '1' which is transmitted to the inputs 21 a and 23a of the gates 21 and 23, whereby on the one hand the signal at the input 4a is permitted to reach the output 4h by way of the OR-gate 25 and on the other hand the signal at the input 4b is permitted to pass to the output 4j.

When the rate of the watch is to be measured, the stem is pulled into position 3 whereby the switch 9 is closed and a logic state '1' appears at the input 4k of the switching means 4 and consequently at the input 24b of the gate 24 and at the input of the inverter 22. This logic state permits the signal arriving at the data input 4e to reach the output 4h by way of the OR-gate 25. With the output of the inverter 22 being in the logic state '0', the gates 21 and 22 are closed, preventing the signals at the inputs 4a and 4b from reaching the outputs 4h and 4j of the switching means 4. The output 4j is consequently in logic state '0'.

It follows that the control circuit 5 which is connected to the outputs 4h and 4j in this case receives only the signal at the input 4e, the formation of which signal will be described hereinafter.

When the signal 4h is at '0', only the transistor T1 is conducting; therefore, the coil of the motor 6 does not receive any current. At each pulse of the signal 4h, the control gates G 1 and G3 of the transistors T1 and T3 remain in or switch to the logic state '1', while the gates G2 and G4 of the transistors T2 and T4 remain in the logic state '0'. Consequently, the transistors T1 and T4 conduct and the transistors T2 and T3 are non-conducting, thus giving the coil of the motor 6 a current pulse. In the embodiment described, this pulse lasts for about 2 mS, which is sufficiently short not to cause the motor to rotate and sufficiently long to permit measurement of the pulse by means of a device based on detection of the magnetic stray field of the motor.

The mode of operation of the logic circuit 10 of Figure 1, which is intended to supply the signals for permitting rapid measurement of the rate of the watch when the stem of the watch is in position 3, will now be described with reference to the diagram in Figure 2 showing the shape of the signals present at different points on the circuit.

When this measurement is to be made and the stem of the watch is in position 3, the switch 9 of the switching means is closed and applies an interrogation signal '1' to the input 7L of the adjusting circuit 7. The latter is so arranged as no longer to be active when its input 7L is at '1' and the divider 2 then operates without adjustment of its division factor.

From the output of two different stages of the divider 2, the inputs 1 Oa and 1 Ob receive signals at a frequency for example of 1 Hz and 256 Hz respectively.

The output 11 c of the AND-gate 11 then periodically supplies trains of pulses which are half a quartz second in duration, the width of each pulse being about 2 mS.

The pulses are on the one hand counted by the counter 1 7 and on the other hand transmitted to the input 1 9b of the gate 1 9. The output 1 9c of the gate 1 9 supplies those pulses to the data output 1 Od as long as the output 0 of the FF18 is at '1'.

The state of the outputs 1 7a of the division stages of the counter 1 7 is compared to the state of the outputs 1 8m of the memory 8 by the comparator 1 6. When these states coincide, the output 1 6c goes from '0' to '1', which causes a change in the state of the outputs Q and Q of the Off 18 which go respectively to '1' and '0'. This change causes the counter 17 to be reset to zero and causes closure of the gate 1 9 which no longer allows the signal supplied by the output 11 c to pass to the output 1 Od.

At the end of a fresh half-quartz second, the FF18 is reset by the signal occurring at the input 1 Ob, which causes the signal for resetting the counter 1 7 to disappear. The counter 1 7 can therefore count a fresh train of pulses. In addition, at the same moment, the input 1 9a is again at '1', which permits the fresh train of pulses to pass through the gate 1 9.

It will be seen therefore that, at each quartz second, a train of pulses is supplied by the output 1 Od to the data input 4e of the switching means 4. These trains of pulses form the measuring signal which is passed to the coil of the stepping motor, as already described above.

The diagram shown in Figure 2 illustrates an example in which the memory 8 contains the number 5 and in which the measuring signal (1 Od/4e) therefore comprises five pulses in each train of pulses. It will be recalled that, in this embodiment, this number which is contained in the memory 8 represents the number of pulses which are suppressed in each adjusting cycle, from the pulses which are supplied by the oscillator 1 to the divider 2.

The rate of a watch of this kind, of inhibition-type, can be calculated by means of the following formula: Nx10-6 m (s/d)=86 400 P-1 + 4.194304 in which m is the rate of the watch is seconds per day, P is the period of a train of pulses of the measuring signal 4e, N is the number of pulses contained in each train of the measuring signal 4e, that is to say, the number of pulses suppressed from the pulses supplied by the oscillator in each adjusting cycle, 86400 is the number of seconds in 24 hours and 4.1 94304x 106 is the result of the product of 32768 Hz (frequency of the oscillator) and 1 28 s (period of an adjusting cycle).

For example, if P is measured at 0.9999904 s and N is measured at 50, we have: 50x10-6 m=86400 (0.9999904-1+ )=0.2 s/d 4.194304 Such a calculation is tedious and in order to avoid it, apparatus for measuring the rate of a watch provided with an electronic circuit as illustrated in Figure 1 has been developed. This measuring apparatus is described in our UK Patent Application No. 79/36415 filed on the same day as the present Application with claim to priority from Swiss Patent Application 12063/78.

It will be apparent that the manner of transmitting the measuring signal outside of the watch may be different from that described hereinbefore. For example, the measuring signal could be transmitted acoustically by means of an electronic alarm device on the watch. Likewise, it would be possible to provide for a different manner of forming the measuring signal wherein the content of the memory of the adjusting circuit for adjusting the division factor could be for example introduced in coded form.

Claims

1. An electronic timepiece comprising an oscillator used as a time base, a frequency divider with an adjustable division factor coupled to the oscillator, a circuit for adjusting the division factor, a memory which is associated with the adjusting circuit and whose state represents the magnitude of the adjustment, a transducer responsive to a signal generated in the timepiece to emit a wave which can be detected by an outside apparatus for measuring the rate of timepieces, a logic circuit which responds to the states of the memory and the divider to produce a measuring signal comprising pulses whose distribution is representative of the division factor and the frequency of the oscillator, and a change-over switching means for applying the measuring signal to the transducer in response to an interrogation signal.

2. A timepiece according to claim 1, wherein the said transducer is a stepping motor which is coupled to the frequency divider and which is provided for driving a means for the analog display of time information.

3. A timepiece according to claim 2, wherein the measuring signal comprises pulses whose duration is sufficiently short not to cause the motor to turn and sufficiently long to cause the emission by the coil of the motor of a magnetic wave which can be detected by the apparatus for measuring the rate of timepieces.

4. A timepiece according to claim 2 or 3, wherein a pulse shaper circuit is connected between the output of the frequency divider and a control circuit which supplies drive pulses to the coil of the stepping motor, and wherein the switching means is disposed between the shaper circuit and the control circuit.

5. A timepiece according to claim 1, wherein the said transducer is of the electro-acoustic type producing an acoustic wave which can be detected by the apparatus for measuring the rate of timepieces.

6. A timepiece according to any of claims 1 to 5, wherein the logic circuit comprises means for producing trains of pulses whose period is derived from that of the oscillator, means for counting the pulses of each train, and means for comparing the state of the counting means with the state of the memory in order, when the said states are equal, to interrupt the application to the transducer of the train of pulses which forms the measuring signal.

7. An electronic timepiece substantially as hereinbefore described with reference tQ and as illustrated in the accompanying drawings.