JPS5889830A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5889830A
JPS5889830A JP18704081A JP18704081A JPS5889830A JP S5889830 A JPS5889830 A JP S5889830A JP 18704081 A JP18704081 A JP 18704081A JP 18704081 A JP18704081 A JP 18704081A JP S5889830 A JPS5889830 A JP S5889830A
Authority
JP
Japan
Prior art keywords
pellet
glass
compressive stress
subject
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18704081A
Other languages
Japanese (ja)
Inventor
Eiji Yamamoto
英治 山本
Hiroshi Tsuneno
常野　宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18704081A priority Critical patent/JPS5889830A/en
Publication of JPS5889830A publication Critical patent/JPS5889830A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the pellet from cracking or exforiating by a method wherein almost entire pellet sides are buried in glass layer. CONSTITUTION:The concavity 2 is formed into base element 1 and after softening the glass 4 filled in said convavity 2, the pellet 3 is depressed downward with appropriate load so that the sides are entirely filled with the glass which is fixed to the base element 1. Through these procedures, the pellet will not be subject to any bending moment because even if the pellet 3 is subject to the compressive stress resulting from the difference of the coefficient of thermal expansion between glass 4 and pellet 3 in case they are subject to thermal fluctuation, said compressive stress will be absorbed by the entire pellet sides. Accordingly, the pellet 3 is subject to even compressive stress only causing no crack or exforiation at all, since the pellet 3 is provided with the strength withstanding the compressive stress several times stronger than that withstanding the tensile stress.

Description

【発明の詳細な説明】 本発明はガラスｖＩＩ着材として半導体素子ベレットｔ
ペース部材に固着してなる半導体装置に関し、％にベレ
ットの熱履歴クラックの防止を図った半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides semiconductor device pellets as a glass vII bonding material.
The present invention relates to a semiconductor device fixed to a paste member, and relates to a semiconductor device which is designed to prevent thermal history cracking of the pellet to a large extent.

、パッケージ用のペース部材にセランツク材ｖＩ！用す
る半導体装置では、半導体素子ベレットのペース−材へ
の固着構造としてＡｕ−８ｉ共晶ｖ！Ａ用する構造やガ
ラスを接着材として利用する構造がある。前書はペース
部材の所定部分にＡｕドツト層を形成しておき、ベレッ
トな構成するシリコンｔベース部材上にスクラブし、Ａ
ｕ層とシリプンとの間にＡｕ−８ｉ共晶を形成して両者
を融着する構造であり、ｌｉｋ看はベース部材の所定部
分に低融点ガラス層を形成しベレットをガラス層上に押
し付けて両者の濡れにより固着する構゛邊である。, Selantsk material vI is used as a packaging material! In the semiconductor device used, Au-8i eutectic v! is used as the structure for fixing the semiconductor element pellet to the paste material. There are structures that use A and structures that use glass as an adhesive. In the previous paper, an Au dot layer was formed on a predetermined portion of the pace member, and then the Au dot layer was scrubbed on the silicon T base member constituting the pellet.
It has a structure in which an Au-8i eutectic is formed between the U layer and the silicone to fuse them together, and a similar method is to form a low melting point glass layer on a predetermined part of the base member and press the pellet onto the glass layer. The structure is such that it sticks together due to the wetness of both.

しかしながら、近年の１会対策の目的から前書の構造よ
り倹看の構造が今後一層の利用度が高まる状ＩＩＫある
。However, in recent years, for the purpose of preparing for one-time meetings, it seems that the use of the ``shukan'' structure rather than the ``previous'' structure will continue to increase in the future.

ところで、後者の構造でｊ寡、軟化されたガラス層の上
方からベレットを押し付けているが、ベレットはその底
面部おＬび肩輯９下縁よりの部位でガラスに＃１着して
いるのに丁ぎない。このため、半導体装置が熱変化（熱
履ａ）ｖ受けたときには、ベレットとガラスとの熱膨張
係数の差によってベレットの底面部とｊ１ｍ面下部にガ
ラスの収縮による圧縮応力を受けるが、ベレット上面部
では応力を殆んど受けないことからペレット内に曲０１
モーメントが生じ、この曲げモーメントによってベレッ
トの変形ないし割れが生じる。また、・ベレット側面の
ガラス層が破壊される。したがって、ペレットノ剥離や
ベレットのａ損が住じて半導体装置の信頼性の低下をま
ねく−という問題がある。特に。By the way, in the latter structure, the bullet is pressed from above the softened glass layer, but the bullet is in contact with the glass at the bottom and the lower edge of the shoulder. It's not even close. Therefore, when the semiconductor device undergoes a thermal change (heat cycle a), the bottom surface of the pellet and the lower part of the j1m surface are subjected to compressive stress due to the shrinkage of the glass due to the difference in the coefficient of thermal expansion between the pellet and the glass, but the top surface of the pellet Since the part receives almost no stress, there is a bend 01 in the pellet.
A bending moment is generated which causes deformation or cracking of the pellet. Additionally, the glass layer on the side of the beret is destroyed. Therefore, there is a problem that the pellet peels off and pellet a loss occurs, leading to a decrease in the reliability of the semiconductor device. especially.

ＭＱＩ９メ％９等のような大塵のペレットでハ前記した
不具合が原著であり、こめ種のペレットのガラス固着を
殆んど不可能な−ものにしている。The problem described above is the original problem with large dust pellets such as MQI9me%9, making it almost impossible to fix rice pellets to glass.

したがって本発明の目的は、半導体素子ベレットの側面
の略全部がガラス層内に堀設されるようにしてペレット
をガラスにて固着することにより、ペレットとガラスと
の熱膨張係数差に起因する応力がペレットに作用しても
、ペレット内での曲げモーメントの発生を防止し、これ
Ｋよりペレットの割れや剥離を防止して半導体装置の信
頼性を向上することができる半導体装置な提供すること
にある。Therefore, an object of the present invention is to fix the semiconductor element pellet with glass so that substantially the entire side surface of the pellet is bored in the glass layer, thereby reducing the stress caused by the difference in coefficient of thermal expansion between the pellet and the glass. To provide a semiconductor device which can prevent bending moment from occurring within the pellet even when the pellet acts on the pellet, thereby preventing cracking or peeling of the pellet and improving the reliability of the semiconductor device. be.

以下、本発Ｉｊｌｉｖｌ！！！示の実施例により説明す
る。Below is the original Ijlivl! ! ! This will be explained with reference to an example.

第１図は本発明の半導体装置の断面図であり、ｌはセラ
ンツク劇のペース部材である。このベース部材１の上面
には方形の凹部２ｖ形成し、この・凹部２内に半導体素
子ペレットｉｖ固着する・ようにしている。この凹［１
２内には低融点ガラス４に比較的厚内状園で入れた上で
、ペレッ）３ｖその側面の全部がガラス４内に埋まるよ
うにして固着している。即ち、凹部２内に入れ嬉ガラス
４を適当な温度に保ってガラスを軟化させた上で、ペレ
ット３をガラス４の上方から適当な荷重で押圧し、ペレ
ット３０ａｍがガラス内に全部場まるように、換言すれ
ばベレッ′ト表面とガラスｌ！！面とが同一面となるよ
うＫｇし込んでペレット３ｔガラス４にでベース部材ｌ
に固着しているのである。FIG. 1 is a cross-sectional view of the semiconductor device of the present invention, and l is a pace member of the Selangk play. A rectangular recess 2v is formed on the upper surface of the base member 1, and a semiconductor element pellet iv is fixed in the recess 2. This concavity [1
Inside the glass 2, the glass 4 is placed in a relatively thick shape, and the pellets are fixed so that the entire side surface of the glass 4 is buried within the glass 4. That is, after placing the glass 4 in the recess 2 and keeping it at an appropriate temperature to soften the glass, the pellet 3 is pressed from above the glass 4 with an appropriate load so that all the pellets 30am are placed inside the glass. In other words, the beret surface and the glass l! ! Insert 3 kg of pellets into the glass 4 so that the surfaces are flush with the base member l.
It is fixed to.

一方、前記ベース部材ｌの周辺上には外部導出リード５
ｖ低融点ガラス６にて取着し、このリード５と前記ペレ
ット３−との間にワイヤ７ｖボンデイングする。また、
ベース部材ｌの上部にはセラミック製のキャップ８ｖ被
せ周辺を前記低融点ガラス６にて封止することにより半
導体装置を構成している。On the other hand, external lead-out leads 5 are provided on the periphery of the base member l.
v Low melting point glass 6 is attached, and wire 7v is bonded between this lead 5 and the pellet 3-. Also,
A semiconductor device is constructed by covering the upper part of the base member 1 with a ceramic cap 8v and sealing the periphery with the low melting point glass 6.

したがって、このように構成した半導体装置によれば、
熱変化（熱履歴）Ｖ受けた際にガラス４とペレット３と
の熱膨張率の差に起因するガラスの圧縮応力がペレット
３に作用しても、この応力はペレットのｌ１ｌｆｆｉ全
体に作用することからペレットに曲げモーメントカミ発
生することはない。したがって−、ペレッ）３＆Ｃは均
一な圧縮応力のみが作用し、ペレットは圧縮応力に対し
ては引張応力に較べて数倍の強度な有するために、Ｑレ
ットにはクラック（割れ）や剥離が生じることは殆んど
ない。本発明看の実験によれば３−×６−のシリコンベ
レン）４Ｃおいてもクラックや剥離のないペレット付を
行なうこ゛とができ、これにより、半導体装置の信頼性
ｔｖ＆段に向上することができる。Therefore, according to the semiconductor device configured in this way,
Even if compressive stress of the glass due to the difference in thermal expansion coefficient between glass 4 and pellet 3 acts on pellet 3 when subjected to thermal change (thermal history) V, this stress acts on the entire l1lffi of the pellet. There is no bending moment generated in the pellet. Therefore, only uniform compressive stress acts on Pellet) 3&C, and since pellets are several times stronger against compressive stress than against tensile stress, cracks and peeling occur in Q-lets. There are almost no such things. According to experiments carried out in accordance with the present invention, it is possible to attach pellets without cracking or peeling even on 3-×6-Silicone 4C, thereby improving the reliability of semiconductor devices to a level of 5. .

第２ｗＪは本発明の他の実施例を示しており、第１図と
同一部分には同一符号を付し【説明な省略す暮。本実施
例ではガラ誠４ムｔベース部材ｌ上に盛り上げ形成し、
そこにペレット３ｖ［１着しているが、この場合にもペ
レット３のｌ１ｍの全部をガラス４Ａ内に堀設しており
、ガラスの圧縮応力がペレットの側聞全体に作用するよ
うにし【いる。2nd wJ shows another embodiment of the present invention, in which the same parts as in FIG. 1 are denoted by the same reference numerals. In this embodiment, a heap is formed on the base member L of the Gala Makoto 4,
There is a pellet 3v [1], but in this case, the entire l1m of pellet 3 is dug in the glass 4A, so that the compressive stress of the glass acts on the entire side of the pellet. .

この構成により、ペレットでの−げモーメントの発生を
防ぎペレットの割れや剥離を防止できることはいうまで
もない。It goes without saying that with this configuration, it is possible to prevent the occurrence of a bending moment in the pellets, thereby preventing cracking and peeling of the pellets.

なお、ペレットの厚さ、縦横寸＠によっては。Depending on the thickness and length and width of the pellet.

曲げモーメントに対する強度の高いペレットを得ること
ができ、この場合にはペレットの１内１面全体をガラス
内に堀設せず表面近傍部位が若干突出するように構成し
ても略同様に高信頼性を得ることができる。It is possible to obtain pellets with high strength against bending moments, and in this case, even if the entire surface of the pellet is not drilled in the glass and the part near the surface is slightly protruded, the reliability is almost the same. You can get sex.

以上のように本発明の半導体装置によれば、ガラスにて
ベース部材に固着するペレッ）Ｖ％その１１ｆｆｉｉの
略全部がガラス内に堀設するようにして固着しているの
で、熱変化により【生じる圧縮応力カヘレットに作用し
てもペレットに曲げモーメントが発生することはなく、
ペレットの割れやその剥離を確実に防止して半導体装置
の信頼性を向上することができるという効果な奏する。As described above, according to the semiconductor device of the present invention, substantially all of the pellets (V%) 11ffii that are fixed to the base member by the glass are fixed by being dug in the glass, so that due to thermal changes, Even if the resulting compressive stress is applied to the pellet, no bending moment is generated in the pellet.
It is possible to reliably prevent cracking of the pellet and its peeling, thereby improving the reliability of the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の−ｖＩ！施例の断面図、第２図は他の
実施例の断面図である。　　　。 ｌ・・・ペースＩＳＬ　３・・・ペレット、４．４人・
・・ガラス、５・・・外部導出リード、７；・・ワイヤ
、８・・・中ヤップ。FIG. 1 shows -vI! of the present invention! A sectional view of the embodiment, FIG. 2 is a sectional view of another embodiment. . l...Pace ISL 3...Pellet, 4.4 people
...Glass, 5...External lead-out lead, 7;...Wire, 8...Middle diameter.

Claims (1)

【特許請求の範囲】[Claims] １、！Ｐ導体素子ペレットをガラス材にてペース部材に
固着してなる半導体装置において、前記ベレットはその
側面の略全郁を前記ガラス内に堀設装置。1,! In a semiconductor device in which a P conductor element pellet is fixed to a paste member using a glass material, the pellet has a device in which substantially the entire side surface of the pellet is dug into the glass.
JP18704081A 1981-11-24 1981-11-24 Semiconductor device Pending JPS5889830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18704081A JPS5889830A (en) 1981-11-24 1981-11-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18704081A JPS5889830A (en) 1981-11-24 1981-11-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5889830A true JPS5889830A (en) 1983-05-28

Family

ID=16199117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18704081A Pending JPS5889830A (en) 1981-11-24 1981-11-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5889830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136534A (en) * 1986-11-27 1988-06-08 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63136534A (en) * 1986-11-27 1988-06-08 Nec Corp Semiconductor device

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