JPS5888896A - 記憶部デ−タの誤り訂正方式 - Google Patents

記憶部デ−タの誤り訂正方式

Info

Publication number
JPS5888896A
JPS5888896A JP56185970A JP18597081A JPS5888896A JP S5888896 A JPS5888896 A JP S5888896A JP 56185970 A JP56185970 A JP 56185970A JP 18597081 A JP18597081 A JP 18597081A JP S5888896 A JPS5888896 A JP S5888896A
Authority
JP
Japan
Prior art keywords
access
data
error
storage
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56185970A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0363097B2 (enExample
Inventor
Hidehiko Nishida
西田　秀彦
Minoru Etsuno
越野　実
Akira Hattori
彰 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56185970A priority Critical patent/JPS5888896A/ja
Publication of JPS5888896A publication Critical patent/JPS5888896A/ja
Publication of JPH0363097B2 publication Critical patent/JPH0363097B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP56185970A 1981-11-19 1981-11-19 記憶部デ−タの誤り訂正方式 Granted JPS5888896A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56185970A JPS5888896A (ja) 1981-11-19 1981-11-19 記憶部デ−タの誤り訂正方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56185970A JPS5888896A (ja) 1981-11-19 1981-11-19 記憶部デ−タの誤り訂正方式

Publications (2)

Publication Number Publication Date
JPS5888896A true JPS5888896A (ja) 1983-05-27
JPH0363097B2 JPH0363097B2 (enExample) 1991-09-30

Family

ID=16180057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56185970A Granted JPS5888896A (ja) 1981-11-19 1981-11-19 記憶部デ−タの誤り訂正方式

Country Status (1)

Country Link
JP (1) JPS5888896A (enExample)

Also Published As

Publication number Publication date
JPH0363097B2 (enExample) 1991-09-30

Similar Documents

Publication Publication Date Title
US3436734A (en) Error correcting and repairable data processing storage system
US4531213A (en) Memory through checking system with comparison of data word parity before and after ECC processing
US5488702A (en) Data block check sequence generation and validation in a file cache system
US6018817A (en) Error correcting code retrofit method and apparatus for multiple memory configurations
TWI466126B (zh) 多通道儲存裝置及在其中儲存資料之方法
US20030140300A1 (en) (146,130) error correction code utilizing address information
US3735105A (en) Error correcting system and method for monolithic memories
KR20220037518A (ko) 영구 메모리 시스템 등을 위한 데이터 무결성
US20120079346A1 (en) Simulated error causing apparatus
US20150347256A1 (en) Error injection and error counting during memory scrubbing operations
TWI771151B (zh) 快閃記憶體裝置及快閃記憶體儲存管理方法
US20140040680A1 (en) Memory control device and control method
US4388684A (en) Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources
CN102171658A (zh) 抑制比特错误校验码方案
US4236247A (en) Apparatus for correcting multiple errors in data words read from a memory
US5535227A (en) Digital information error correcting apparatus for single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC)
US3218612A (en) Data transfer system
US3411137A (en) Data processing equipment
JPS5888896A (ja) 記憶部デ−タの誤り訂正方式
US3794819A (en) Error correction method and apparatus
US20210004288A1 (en) Error detecting memory device
US5914970A (en) Computer memory system providing parity with standard non-parity memory devices
US11256569B2 (en) Error correcting bits
JPS59743A (ja) Ｅｃｃ回路診断方式
TWI867734B (zh) 快閃記憶體控制器、快閃記憶體控制器的操作方法及儲存裝置