JPS5887977A - Output signal control method for image sensor - Google Patents

Abstract

PURPOSE:To prevent the saturating state of an output signal, by detecting that signals photoelectric converted in excess of a prescribed level in output signal group per one frame are shared and adjusting the frame storage time through the detected value. CONSTITUTION:If video signals photoelectric converted in excess of a prescribed level take place during one frame scanning period, an F/F circuit 4 is set with an output of an analog comparator 2 and an AND gate 9 is closed. Thus, a U/D counter 5 is up-counted. The count value of the counter 5 shows the amount of signals photoelectric converted in excess of the prescribed level. This output is fetched to a latch circuit 12 and applied to an image sensor 1 via a D/A converter 10 and a V/F converter 13. Thus, the storage time of the image sensor 1 can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for appropriately controlling the frame accumulation time of a solid-state image sensor according to the amount of light input to the solid-state image sensor, thereby preventing output signal saturation.

If an excessive amount of human light is applied to a solid-state image sensor, the amount exceeds the storage tolerance of the charge storage capacitor, and the photoelectrically converted output signal becomes saturated, making it impossible to use it normally.

Conventionally, in order to deal with such a situation, a mechanical diaphragm mechanism was provided in the optical system added to the 4-mage sensor, and by adjusting this, the amount of input light was reduced.
This prevents the output signal of the 4-mage sensor from becoming saturated.

However, such a mechanical diaphragm mechanism has the disadvantage that its response is slow and that the amount of input light must always be photometered in order to make the diaphragm respond automatically.

The present invention eliminates the above-mentioned drawbacks and relates to a method for preventing output signal saturation with high-speed response. First, it detects the extent to which the photoelectrically converted signal is included at the saturation level of the solid-state 4-image sensor or a level close to the saturation level (hereinafter referred to as the saturation level, etc.). , the purpose is to control the frame accumulation time of the solid-state image sensor so as to increase or decrease the signal to be photoelectrically converted at the saturation level etc. according to the detected signal value. Describe.

Fig. 1 shows how to four-digitally measure whether and to what extent a video signal that is distorted in one frame contains a signal that exceeds the saturation level of the solid-state image sensor. 3 shows an embodiment of a circuit for controlling frame accumulation time.

A solid-state 4-image sensor (11 is a one-dimensional or two-dimensional self-scanning type that operates in charge accumulation mode, and its light '+s, converted output signal (hereinafter referred to as video signal) (el) The group is input to an analog comparator (2).

For example, a threshold value (Vs) corresponding to a level near the saturation level in the four main sensors (1) is set in the analog comparator (2), and the video signal (el) group is ) compared to 1, to
As a result, the analog comparator (2+) outputs a pulse signal (gl) corresponding to the video signal 1e, which exceeds the threshold (Vs) among the video signals (el) that have undergone photoelectric conversion as shown in FIG. ) is obtained.

Conopulse signal (g+) u, after passing through the AND gate (3) which is synchronized with the set meal clock pulse (C) of the image sensor (1), is set input to the F/F (flip-flop) circuit (4) (S) and the up input (UP) of the U/D (up/down) counter (5).

10,000, the video signal (el) group is filtered through a low-pass filter (6
), and the averaged video signal (eL) that has passed through the low-pass filter f6) is input to a V/F (voltage/frequency) converter) 8).

V / F converter +81 or 17 output pulse signal (g2
) triggers the town input (DN) of the U/D counter (5) after passing through the AND gate (9) which is opened when the F/F circuit (4) is set.

The U/D counter (5) has an initial preset that causes the D/A converter (10) to output the input voltage necessary for another V/F converter 03) to generate a clock pulse (C). The value (IP) is loaded at system start, after which it is input either up input (UP) or down input (
The count is continuously increased or decreased depending on the pulse signal (g, ) or (g2) applied to the DN).

Here, with the typing of the binary count data (d) u of the U/D counter (5) and the frame end signal (g3) outputted by the frame counter (11), the latch circuit (12) is serially called. When the latched signal (d) is input to the D/A converter (10).

Then, the analog signal (g,) output from the D/A converter (10) is input to the V/F converter (131), and the output pulse from this V/F converter (13) is clocked. The pulse (C) is used to control the scanning speed of the Maci sensor (1).

The frame counter (old) counts the number of transfer stages (N)'e for one frame of sensor (1) from the start of scanning of one image sensor (1), and the frame end (mM (g3)) at the end of scanning of one frame. This frame end signal (g3) is output to the reset input (R
, ) as well as the latch input of the latch circuit (121).

The V/F converter (13) converts the standard input light intensity ( A clock pulse (C
) is output.

In the above configuration, during the frame scanning period, the photoelectrically converted video signal (e
When l) occurs, the pulse signal (gl) output by the analog comparator (2) for the video signal (e,) that exceeds the threshold (Vs) at the beginning of the frame is FIF times j
! 8 (Set 41 and close Antogame-1-(9).

Thereafter, the threshold value (V
The video signal exceeding s) is passed through an analog comparator (2
), the number of detections is exhausted by the u/D counter (
5).

] At 1, when the first video signal (e,) exceeding the threshold (Vs) occurs after the scanning of the frame starts, F
/F circuit (4) c. Since it is reset by the frame end signal (g3), the AND gate (9) is open, and the output pulse (g2) of the V/F converter (8) is the U/D
The counter (5) receives 1.

Thus, the video signal (e,) exceeding the threshold (Vs)
When many occur, ■/F7! Since the input signal (g4) of the J converter (13) increases, the clock frequency (fs) increases. The number of overlapping video signals (el) is reduced.

When the input light t(L) decreases on average or the frame accumulation time (tF) is shortened with respect to the input light amount (L), the video signal (e,) group becomes below the threshold value (Vs). . As a result, the averaged video signal (el) decreases, so a V/F converter (
The number of output pulses (g2) in step 8) increases, thereby controlling the U/D counter (5) to decrease the count and increase the frame accumulation time (tF).

FIG. 4 shows how much of the photoelectrically converted video signal (el) is included below the lower limit level of the solid-state image sensor in addition to the upper limit level corresponding to the threshold value (Vs). 1 shows an example of a circuit for controlling frame accumulation time.

In the block diagrams below, blocks having the same functions are indicated by the same reference numerals as in FIG. 1, and the description of the foregoing ones will be omitted.

In Fig. 4, in place of the low-pass filter (6) in Fig. 1,
Another analog comparator (14) is provided, and the video signal (el) group is input to the analog comparator (old).
is provided with a threshold value (VS2) corresponding to the level value just before the signal level of noise etc. on the low light level side, and the other analog converter, <lator (2, 1), has a video signal (e,
).

The output of this analog comparator (14i) is the threshold value (V
s') When the following video signal (e,) is input,
As the output of the AND gate (+5), the video signal (
A pulse signal (g,) corresponding to el) is obtained in synchronization with tarok pulse (c) (see FIG. 5).

This pulse signal (g5) is sent to the analog comparator (2
It is sent to the town input (DN) of the U/D counter (5) along with the pulse signal (gl) from +.

Therefore, the U/D counter (5) cancels out the number of video signals (e,) exceeding the threshold value (vs) and the number of video signals (el) exceeding the threshold value (vs'). Count as follows.

As a result, the frame accumulation time (tF) is automatically balanced based on the count value of the U/D counter for each frame, and the video signal (el) group is always kept at both thresholds (Vs) (
vs').

6 and 8 show video signals (e,
) group per frame is detected in an analog manner.

Figure 6 shows the video signal (el) of the image sensor (1).
The integrated video signal (g7) is taken through the integrator (+8) into the sampling and hold circuit (17) by the frame end signal (g3), and then the integrator A clock pulse (C) is obtained from the sample value (g6) through the V/F converter (10) (see FIG. 7).

As a result, when each value of the video signal (el) group is biased to or near the saturation level, the integral value is raised, the clock frequency (fs) becomes high, and the frame accumulation time (tF) becomes short.

Conversely, if each value of the video signal (el) group is biased toward or near the signal level corresponding to the threshold value (vs') in FIG.
The integral value is lowered, the clock frequency (fs) is lowered, and the frame accumulation time (tp) is lengthened.

In both cases, a closed loop is formed in an uncategorized manner, and the self-balancing operation is performed stably.

In FIG. 8, an integrator 1181i is used like the embodiment in FIG. 6, and the integrating capacitor (19) of the integrator (18) is
The discharge occurs at the end of the frame, and the other closed loop circuit configuration and operation are the same as those in FIG. 6. However, in this embodiment, a multiplier (20, etc.) is provided as a sensitivity drift component correction means as will be described later (see FIG. 9).

It goes without saying that the emission rate of the capacitor (191) is determined after sampling.

In the embodiment shown in FIG. 8, the integral value (g
7) is obtained analogously at the end of the frame for one frame of rice, and according to this value, the frame accumulation time (tr
) is the one that controls it.

As in each of the above embodiments, when closed-loop feedback control is applied to the frame accumulation time (tF) of the image sensor (1), the light sensitivity of the image sensor (1) is controlled for each frame. , so the video signal <e,)
A sensitivity drift component is superimposed on vc.

In the embodiment shown in FIG. 8, all of the correction means for this sensitivity drift component are added, and this correction means can also be applied to each of the embodiments shown in FIGS. 1, 4, and 6. The video signal (e+) iq containing the sensitivity drift component is applied to the -1000 input terminal of the multiplier (20), and the input voltage (V) of the V/Ff filter (1o) is applied to the other input terminal. , the required coefficient (b) is multiplied and added via the coefficient unit (21).

The multiplier (20) multiplies these input signals, removes the sensitivity drift component, and outputs a video signal (el) corresponding only to the input light amount (L) of the 4-mage sensor (1). is expressed as the following equation.

', 'fs−αV. , -80, β-V-L-γ°β α L Input light amount (average output within time T) T Light integration time (every 1 clock) fs: Clock frequency el: Sensor output el: Multiplier output γ Proportional constant β of the sensor: Set value of the coefficient unit (21) V: Input terminal α of the V/F converter (10): Proportional constant of the V/F converter 00) In this way, the proportional constant of the q multiplier (20) Video signal to be output (e
l) is the amount of human light (L), each constant (α), (A, (
γ) and rob one's clothes. The proportionality constant (γ) of the 4-mage sensor (1) is a constant that has a small fluctuation rate with respect to changes in clock frequency (changes in frame accumulation time), so as in the present invention, the proportionality constant (γ) of the 4-mage sensor (1) Even if feedback control is performed, the video signal (el) corresponding to the input light amount (L)
) can be obtained.

As described above, according to the present invention, the optimal frame accumulation time for the amount of light is automatically shortened according to the amount of human light of the image sensor (1), thereby reducing the saturation of the output signal when excessive light weight is input. ” state, or when the amount of light is low manually, the light weight conversion can be performed reliably and below the lower limit level of the solid-state 1 main sensor.
The objective is to provide an image processing system with high-speed response and a wide range of input light intensity.

The video output from the secondary side 1 concave road in Ming to Xi Xi
The signal period is not constant. Therefore, if the video output has a fixed period of one or more signals, by using the signal period correction circuit as shown in Fig. 10,
Achieving that purpose becomes a powerful skill.

That is, the analog output from the control circuit (3o) according to the present invention is converted into digital by the A/D converter (31), and the digital signal is transferred to the frame memory of the chair via the selection switch (32). 03).

The first frame memory (33a) stores the first frame, the next frame memory (33b) stores ui2 frames, and during this storage, the first frame memory (33a) is read out. Clock (34
(Use the cycle required for the final video output.

Select switch (35) from valley frame memory (33)
and the D/A converter (if the cycle of the output from the control circuit +301 is faster than the video signal output through the field, the frame memo!J-Cd5) has a finite individual value, so it will eventually be And at this time,
Input for one frame is interrupted.

Conversely, when the output of the control circuit ((0) is slow compared to the output of the video signal, the same frame memory l) -C(31
The control can be controlled by performing the reading from j11 twice, etc.

[Brief explanation of drawings]

The figures are for explaining the method of the present invention, and FIG.
A block diagram of an embodiment in which the main parts are digitally controlled; Fig. 2 shows the waveforms of the main parts in Fig. 1; 4 is a graph showing the conversion characteristics of the V/F converters (13) and (8) shown in the figure. FIG. 4 is a block diagram of an embodiment different from that in FIG. 5 is a diagram showing the waveforms of the main parts of FIG. 4, FIG. 6 is a block diagram showing an example of controlling the main parts in an analog manner, and FIG. 4 Munayat, Figure 8 is a block diagram showing an embodiment different from that shown in Figure 6, in which the main parts are controlled analogously.
The figure shows the correction circuit for the signal station. (]l /I image sensor (2XMi analog converter f31 (9XI5) and gate fil F/F circuit (51U/D counter
T61 low pass filter L8X131 V/FK
llJ device (10) D/Af exchange! (18) Integrator
(19) Integrating capacitor (20) Multiplier (21) Coefficient unit (301 control circuit
(3) I A/D converter (32) Selection switch 4 Tuna (33) Frame memory (341 Read clock (35) Selection switch 1361D
/ A Con Hearter

Claims (2)

[Claims] (1) At least one of an upper limit level and a lower limit level of the amount of light input to the image sensor is set in the control circuit of the image sensor, and at least one of the output signal group per frame of the image sensor is set to exceed the above level. 1. A method for controlling an output signal in an image sensor, the method comprising: detecting the extent to which a photoelectrically converted signal is distorted; and increasing/decreasing the frame accumulation time of the image sensor based on the detected value. (2) The output of the image sensor according to claim 1, wherein the sensitivity drift component of the image sensor is corrected by multiplying the amount of light input to the image sensor by a required constant value. Signal control method.