JPH06113194A - Driving method for solid state image pickup device and electronic iris control circuit for video camera - Google Patents

Abstract

PURPOSE:To improve the response speed of iris control by changing charge accumulation period of time so that the rate of change of charge accumulation period of time between adjacent fields or adjacent frames becomes always constant. CONSTITUTION:Voltage corresponding to the brightness of a picture is outputted from a low pass filter 9, and the voltage is compared with reference voltage by comparison circuits 11, 12, and the count value of a count value designation circuit 14 is increased or decreased by a decoder 13. A shutter pulse generation circuit 20 gates the output pulse CLK of a clock generation circuit 15, and outputs it as a shutter pulse to a solid state image pickup device 2. Then, upon reception of a read-out signal XSG1, it allows the output pulse CLK to pass, the upon reception of the signal designated by the count value designation circuit 14, it inhibits it from passing, and the state continues until the next read-out signal XSG1 arrives. This inhibition period of time becomes the charge accumulated period of time, and the charge accumulation period of time is changed so that the rate of change (ratio of charge accumulated period of time of one field to that of the next field) becomes always constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a solid-state image pickup device and an electronic iris control circuit of a video camera, and more particularly to a method of driving a solid-state image pickup device in which the responsiveness in the iris control circuit is enhanced without fear of hunting. And an electronic iris control circuit for a video camera.

[0002]

2. Description of the Related Art In a solid-state image pickup device, for example, a CCD type solid-state image pickup device, generally, signal charges accumulated in each photoelectric conversion element in the solid-state image pickup device are swept to an overflow drain region or a semiconductor substrate side by applying a shutter pulse. The exposure time can be changed by adjusting the charge accumulation time in the field period by applying a shutter pulse.

The charge storage time is controlled by the shutter pulse in units of 1H (horizontal scanning period).
This is because the application timing of the shutter pulse was limited to the horizontal blanking period. The application timing of the shutter pulse is limited to within the horizontal scanning period in order to prevent noise from entering the video signal.

Some video cameras using such a solid-state image pickup device utilize the electronic shutter function for iris control. FIG. 8 (A) shows such an electronic iris control circuit, and FIG.
3 is a time chart for explaining the operation of the electronic iris control circuit. In the drawing, 1 is a lens, 2 is a solid-state image pickup device, 3 is a sample hold circuit for taking out the output of the solid-state image pickup device 2, 4 is an AGC circuit, 5 is a gamma correction circuit, 6
Is a white clip circuit, and 7 is a black clip circuit.

Reference numeral 8a shows a conventional example of an electronic iris control circuit, which comprises a low-pass filter 9 for integrating the output of the sample hold circuit 3 and a shutter control circuit 10. The low-pass filter 9 integrates the output of the sample hold circuit 3 so that the entire screen (average) is displayed.
The shutter control circuit 10 plays a role of detecting the brightness, and increases the shutter speed when the output of the low-pass filter 9 is higher than the reference value, and decreases the shutter speed when the output is low. .

V _BLK is a vertical blanking signal, X
_SG1 is a read signal, HD is a horizontal cycle signal, and X _SUB
(1) to (n) are shutter pulses for instructing the sweep-out in each other example. The exposure time of the solid-state imaging device is X
The case of _SUB (1) is the longest, X _SUB (2),
As shown in (3), (4), ..., It is possible to shorten the horizontal cycle unit. The charge accumulation time (exposure time) is
Is the time from the occurrence time of the last shutter pulse of the shutter pulse generated by 1H period after the occurrence of the read signal X _SG1 to occurrence time of the next read signal X _SG1.

In such a conventional electronic iris control circuit, if the output of the integrating circuit (low-pass filter) 9 is higher than the reference value, one horizontal period (1H) for each field as shown in FIG. 3B. Each time the exposure time is shortened so that the output of the integrating circuit 9 reaches the reference value,
On the contrary, if the output of the integrating circuit is lower than the reference value, then FIG.
Contrary to the case shown in (1), the exposure time is lengthened by 1H for each field so that the output of the integrating circuit 9 always becomes the reference value.

[0008]

By the way, according to the conventional electronic iris control circuit, the iris control is carried out by shortening the exposure time by one horizontal period or by lengthening it conversely. However, there is a problem that it takes a long time, that is, a response speed is low. Specifically, the range in which conventional iris control is possible is 1/60 to 1/1500 seconds, and approximately 24
There are 0 steps, and if the exposure time has to be changed from one end to the other end of the range, only 60 steps can be changed per second, so it takes about 4 papers to become the optimum iris. That is, in a dark place, the iris hardly changes in one step, and the response speed becomes very slow.

Further, the applicant company has expanded the dynamic range of the iris to 1/60 to 1/100000.
Succeeded in developing a technology for setting a second (or 1/60 to 1/200000 seconds or more) (applied at the same time as this application)
However, in such a case, the number of steps is further increased to about 1000, and it takes about 17 seconds. Cowardly,
Further increase the dynamic range of iris control to 1/60 to 1
When it is widened to / 200000 seconds, the maximum value of the time required to obtain the optimum iris becomes longer.

The present invention has been made to solve such a problem, and an object thereof is to increase the response speed in an iris control circuit without fear of hunting.

[0011]

According to another aspect of the present invention, there is provided a method of driving a solid-state image pickup device, which comprises changing the charge storage time so that the rate of change of the charge storage time between adjacent fields or adjacent frames is always constant. Characterize. An electronic iris control circuit for a video camera according to claim 2, wherein an integration circuit for integrating an output signal of the solid-state imaging device, a comparison circuit for comparing the output signal of the integration circuit with a reference value, and at least each vertical scanning period A clock generation circuit that generates a clock pulse for each horizontal blanking period, and each accumulation start point when changing the charge accumulation time so that the rate of change of the charge accumulation time between adjacent fields or adjacent frames is always constant. A counted pulse generation circuit that generates a counted pulse corresponding to the horizontal blanking period, a count value designating circuit that increases or decreases a designated count value based on the output of the comparison circuit, and the counted pulse in each field or For each frame, a counter that counts until the designated count value designated by the count value designation circuit is reached, and A shutter pulse generation circuit that outputs the clock pulse that is the output of the clock generation circuit to the solid-state imaging device as a shutter pulse during the period from the arrival of the charge read pulse to the output of the counter after the output of the charge read pulse. It is characterized by having.

According to the electronic iris control circuit of the video camera of claim 3, in the electronic iris control circuit of the video camera of claim 2, the counted pulse generation circuit counts the clock pulse when the charge read pulse arrives and addresses it. Generated at each horizontal blanking period, which is the start point of each charge accumulation when changing the charge accumulation time so that the change rate of the charge accumulation time between the adjacent field or adjacent frame is always constant. An address of a clock pulse to be stored is stored in advance, and a storage unit that generates a signal each time the address and the output address of the address counter coincide with each other.

An electronic iris control circuit for a video camera according to a fourth aspect of the present invention has a solid-state image pickup device, and adjusts a charge accumulation time by a time interval between a shutter pulse for discharging charges applied to the solid-state image pickup device and a charge read pulse. In the electronic iris control circuit of the video camera, an integrating circuit that integrates the output signal of the solid-state image pickup device, a comparing circuit that compares the output signal of the integrating means with a reference value, and a horizontal retrace line at least in each vertical scanning period. A clock generation circuit that generates a clock pulse for each period, a counter that starts counting the clock pulse generated from the clock generation circuit each time each accumulation time starts, a current count value that the counter counts, and The address input receives a signal that increases or decreases the count value based on the comparison result of the comparison circuit, Corresponding to each address input of the storage means for storing the optimum count value for the next counter in-count as data, receiving the charge read pulse and the output of the counter, and after the arrival of the charge read pulse, the carry output of the counter. And a shutter pulse generation circuit that outputs the clock pulse output from the clock generation circuit as a shutter pulse to the solid-state imaging device until receiving.

According to another aspect of the electronic iris control circuit of the video camera of the present invention, the magnitude of the count value increased / decreased by the storage means differs according to the magnitude of the difference between the video signal compared in the comparison circuit and the reference value. It was characterized as being done.

An electronic iris control circuit for a video camera according to a sixth aspect is the electronic iris control circuit for a video camera according to the second, third, fourth or fifth aspect, wherein in the frame read mode, each adjacent charge read pulse is generated. It is characterized in that it has a shutter pulse compulsion circuit for frame reading that generates a shutter pulse of 1 pulse which is input to the solid-state image pickup device at a substantially intermediate time point.

[0016]

According to the method of driving the solid-state image pickup device of claim 1,
There is no problem that the rate of change of brightness in a dark place is extremely small and the change becomes slow as in the case of changing the charge accumulation time in 1H increments in the related art, and the exposure time (brightness) is always kept at substantially the same rate of change. It can be changed, and the response speed of iris control can be increased. According to the electronic iris control circuit of the video camera of the present invention, the charge accumulation time is changed so that the rate of change of the charge accumulation time between adjacent fields or adjacent frames is always constant. Since the counted pulse generation circuit that generates the counted pulse corresponding to the horizontal blanking period is provided so that the shutter pulse may be generated only when the counted pulse is generated, there is a possibility that the shutter pulse may be generated between adjacent fields or adjacent frames. It is possible to change the charge storage time so that the rate of change of the charge storage time in step S1 is always constant.

According to the electronic iris control circuit of the video camera of the third aspect, the charge storage time is changed by the storage means so that the change rate of the charge storage time between adjacent fields or frames is always constant. The address (number) of the clock pulse at the start of each accumulation is stored, and the pulse counted by the counter is thinned out by the storage means so that the rate of change of the charge accumulation time is always constant, so that the charge accumulation is surely performed. It is possible to make the rate of change of time constant.

According to the electronic iris control circuit of the video camera of claim 4, the optimum value is always set as a new charge storage time to be switched from the current light amount and the current charge storage time (shutter speed). Since it is stored in the storage means, it is possible to always control the charge storage time (shutter speed) that is optimal for the condition at each time.

According to the electronic iris control circuit of the video camera of the present invention, since the count value can be greatly increased or decreased when the difference between the video signal and the reference value is large, the output video signal of the solid-state image pickup device can be increased or decreased. The control speed of the charge storage time when the difference from the reference value is large can be increased.

According to the electronic iris control circuit of the video camera of claim 6, in the frame read mode, the shutter pulse is forcibly input to the solid-state image pickup device at almost every intermediate point between the adjacent charge read pulses. It is possible to prevent the change rate from rising to 100% when the storage time decreases from the maximum to the opposite or vice versa, so that the change rate becomes the same as that in the field read mode.

That is, in the case of frame reading, when the charge storage time is maximum and the shutter pulse is not input to the solid-state image pickup device, the charge storage time is one frame period (1/30 papers in the case of NTSC system). The next darkest charge accumulation time is when one shutter pulse is generated in each field period, which is one field period, and the light amount change rate during that period is 100% [(5
25H-262H) / (1/60)], which is extremely large, and therefore hunting may occur. However, in the electronic iris control circuit of the video camera according to claim 6, since the shutter pulse is forcibly input to the solid-state imaging device at a substantially intermediate time point between the adjacent charge read pulse generation times, the maximum charge accumulation time is approximately one field. In the period, the charge storage time can be changed as in the field read mode, and the charge storage time can be controlled so that there is no risk of hunting.

[0022]

The present invention will be described in detail below with reference to the illustrated embodiments. FIGS. 1A and 1B show one embodiment of the present invention. FIG. 1A is a circuit block diagram of an electronic iris control circuit, and FIG. 1B is a time chart. In this example,
Although it has a characteristic configuration not shown in the conventional example shown in FIGS. 3 (A) and 3 (B), it also has a common part, and the common part has already been described, so description thereof will be omitted and only different parts will be described. To do. In addition, common reference numerals are used for common parts throughout the drawings.

In the drawing, 8 is an electronic iris control circuit, and 9 is a low-pass filter (LP) which integrates the video signal output from the sample hold circuit 3 and converts it into a DC value.
F), 11 and 12 are reference voltages V1 and V2 (V1> V2).
And the output voltage of the low-pass filter 9, the comparison circuit 11 detects whether the output voltage of the low-pass filter 9 is higher than the reference voltage V1, and the comparison circuit outputs the output voltage of the low-pass filter 9. It is detected whether it is lower than the reference voltage V2.

Reference numeral 13 is a decoder which sends an addition command signal or a subtraction command signal based on the comparison results from the comparison circuits 11 and 12. Specifically, when the comparison circuit 11 outputs a signal indicating the comparison result that the output signal of the low-pass filter 9 is higher than the reference voltage V1, the decoder 13 outputs an addition command signal. This leads to an increase in shutter speed. When the comparison circuit 12 outputs a signal indicating the comparison result that the output signal of the low-pass filter 9 is lower than the reference voltage V2, the decoder 13 outputs a subtraction command signal. This leads to a slower shutter speed. When no output is generated from either of the comparison circuits 11 and 12,
That is, when the output signal of the low pass filter 9 is lower than V1 and higher than V2, the decoder 13 does not issue an addition command or a subtraction command. The dead zone is between V1 and V2.

Reference numeral 14 is a count value designating circuit for storing a pulse count value for determining the shutter speed and for increasing or decreasing the count value based on a command from the decoder 13. Reference numeral 15 is a clock generation circuit, and in this embodiment, a clock pulse CLK is generated for each horizontal blanking period.
To occur. It should be noted that although a more complicated operation is performed in another embodiment, this will be described later. An address counter 16 counts the clock pulses generated from the clock generation circuit 15 when receiving the read signal X _SG1 , and gives addresses to the clock pulses in the order of arrival after the read signal (pulse) X _SG1 .

Reference numeral 17 denotes a clock pulse CLK generated at each horizontal blanking period, which is each accumulation start time when the charge accumulation time is changed so that the change rate of the charge accumulation time between adjacent fields is always constant. This is a ROM that stores an address in advance, and generates a pulse each time the count value of the address counter 16 matches the stored address. The pulse generated by the ROM 17, that is, the counted pulse is counted by a counter (19) described later. The address counter 16 and the ROM 17 constitute a counted pulse generation circuit 18. The counted pulse generation circuit 18 does not allow all of the clock pulses CLK to be counted by a counter (19) described later, but instead of other clocks so that only clock pulses of a preset address are counted. It plays the role of thinning the pulse.

Reference numeral 19 is a counter for counting the counted pulses output from the counted pulse generating circuit 18, and when receiving the read signal X _SG1 , the counting of the counted pulses is started and the count value is designated by the count value designating circuit 14. When it reaches a value specified by, a reset signal (carry signal) is generated. _{Reference numeral} 20 denotes a shutter pulse generation circuit, which is in a set state when it receives the read signal X _SG1, is reset by a reset signal of the counter 19, and is in the set state.
The passage of the pulse output from is permitted, and the passage of the pulse is prohibited in the reset state. The output of the shutter pulse generation circuit 20 is applied to the solid-state imaging device 2 as a shutter pulse.

Next, the operation of the electronic iris control circuit shown in FIG. 1A will be described. A voltage according to the overall brightness of the screen is output from the low-pass filter 9, and the voltage is compared with the reference voltages V1 and V2 by the comparison circuits 11 and 12, and the output voltage of the low-pass filter 9 is higher than the reference voltage V1. At the time, that is, when it is too bright, the decoder issues a command to increase the count value of the count value designating circuit 14 (the value to be counted by the counter 16), and the low-pass filter 9
When the output voltage of is lower than the reference voltage V2, that is, when it is too dark, the decoder 13 issues a command to decrease the count value of the count value designating circuit 14.

A dead zone exists between the output voltages V1 and V2, and hunting can be prevented by providing this dead zone. That is, the width of the dead zone corresponds to a unit time in which the exposure time can be changed.
If the output signal is wider than the voltage fluctuation of the DC level of the output signal, hunting can be prevented. It can be said that the wider the dead zone, the greater the hunting prevention effect, but the wider the dead zone, the worse the control sensitivity. That is, the central value of the dead zone is preferable as the value to be converged, but if it enters the dead zone, it cannot be controlled. Therefore, if the dead zone is wide, the video output becomes stable when the value largely deviates from the converged value. there is a possibility. And common sense AGC
Since the gain of is about -20 dB, the dead band width V
1-V2 is preferably about 10% of the dynamic range of the video signal. Of course, when the output voltage of the low pass filter 9 is between V1 and V2, the decoder 13 does not add or subtract the count value of the count value designating circuit 14.

By the way, the shutter pulse generation circuit 20
Gates the output pulse CLK of the clock generation circuit 15 and outputs it to the solid-state imaging device 2 as a shutter pulse.
Specifically, when the read signal X _SG1 is received, the set state is set, and the passage of the output pulse CLK is permitted, and the counter 1
6 receives a reset signal generated when the count value designated by the count value designating circuit 14 is counted, the reset state is established and the passage of the clock pulse CLK is prohibited, and the next read signal X _SG1 arrives at this prohibition. Continues until. Then, this prohibition period becomes the charge accumulation time (that is, exposure time).

The major difference of this electronic iris control circuit from the conventional electronic iris control circuit is 1H per field.
The exposure time does not change each time, but as shown in FIG. 1 (B), the exposure time is changed so that the exposure time is shortened by 10% or vice versa. That is, 1 field (1/60 second) as in the past
If the charge storage time can be shortened by only 1H each, it takes a maximum of 4 seconds to realize the optimum iris, but in the present embodiment, one field of the exposure time (1/60 seconds).
Since the change rate of is about 10%, the iris can be made almost proper in about 0.5 seconds at maximum.

Specifically, there are 262 horizontal blanking periods between the arrival of the read signal X _{SG1 and the} rise and fall of the vertical blanking signal. And
The shutter gain difference is changed by 10% in one field. Therefore, 0, 26, 50, 71
No. 90, 107, 122, 136, 149
No., No. 150, ... Are stored in the ROM 17 as addresses, and shutter pulses in other horizontal blanking periods are thinned out. Therefore, when the iris has to be changed greatly, the proper address can be quickly set. Table 1 below shows the interval between adjacent addresses of the address where the shutter pulse is generated in the left column.
Incidentally, the right column shows the numbers obtained by counting the horizontal scanning period of the shutter pulse generation timing backward from the vertical blanking start point which is the end point in each field in the present embodiment.

[0033]

[Table 1]

The inventor of the present application ensures that the shutter pulse is generated even in the vertical blanking period, and the frequency of the shutter pulse in the vertical blanking period is considerably higher than the horizontal frequency of 15734 Hz so that the shutter gain difference is large. I devised a technique to increase the dynamic range of the iris while preventing it from becoming larger than 10%.
The present invention can be applied to a device having a wide iris dynamic range as described above. FIG. 2 is a time chart when the present invention is applied to such a type of electronic iris control circuit.

In this wide dynamic range electronic iris control circuit, firstly, the operation of the clock generation circuit differs from that of the electronic iris control circuit of FIG. 1 in the following points. First, the clock generation circuit 15 uses the read signal.
_When receiving _XSG1 , first, a pulse is always generated every horizontal blanking period. Therefore, this pulse is of course 15734 Hz
Is. However, the pulse of 15734 Hz is generated during the period from the receipt of the read signal X _SG1 to the end of the vertical blanking period, the start of the next vertical scanning period, and the end of this vertical scanning period. When this vertical scanning period ends and the next vertical blanking period begins, the frequency of the generated pulse changes to, for example, 1 MHz. When the read signal X _SG1 is generated during the vertical blanking period, a pulse is generated every horizontal blanking period. The clock generation circuit 15 repeats such an operation for each field.

This is done so that the shutter pulse is generated only during the horizontal retrace period in order to prevent noise from entering the video signal of the solid-state image pickup device 2 due to the shutter pulse during the vertical scanning period. However, this is a blanking period during the vertical blanking period, and there is no risk of noise being generated in the video signal due to the shutter pulse. This is because the exposure time can be changed.
The reason why the exposure time can be changed in a short unit time is to prevent the shutter gain difference from increasing.

Secondly, the ROM 17 also stores addresses for the vertical blanking period so that the shutter pulse can be generated even during the vertical blanking period. In this case as well, the principle that the exposure time can be changed by about 10% for each field is fully adhered to.
In FIG. 2, the address means the address counter 16
, The address data 1 and 2 are two examples of the data stored in the ROM 17, and the outputs 1 and 2 are examples of the two outputs counted by the counter 19.

FIGS. 3 and 4 are for explaining a second embodiment of the electronic iris control circuit of the video camera of the present invention, and FIG. 3 is an overall circuit block diagram. In this embodiment, the shutter pulse generating circuit 20 gates the clock pulse generated by the clock generating circuit 15, and the shutter pulse generating circuit 20 receives the read signal X _SG1 when it receives the read signal X _SG1 . The operation of starting the output of the clock pulse as the shutter pulse and ending the output of the input clock pulse as the shutter pulse when receiving the carry output (reset signal) from the counter 19 is performed for each field. This point is the same as the first embodiment.

However, the counter 19 counts the clock pulse C output from the clock generation circuit 15.
The point is that it is the LK itself, which is a great difference from the first embodiment. Then, the count value counted by the counter 19 is designated by the data output from the ROM 21 which is the storage means and transmitted through the latch circuit 22. The ROM 21 receives the output of the decoder 13 and the current output to the counter 19 as address inputs, and incorporates each data to be output to the counter 19 next corresponding to each address input. In this respect, the second embodiment is the first
It is greatly different from the embodiment. FIG. 4 is a circuit block diagram showing an essential part of this embodiment, and Table 2 below is a relational table between the address input of the ROM (storage means) and the stored data.

[0040]

[Table 2]

Data stored in the ROM 21 will be described with reference to FIG. The ROM 21 receives, as address inputs, data currently output from the latch circuit 22 to the counter 19 as a signal designating a count value and a signal from the decoder 13 designating whether the brightness should be dark or bright. Next counter 1 corresponding to address input
The count value to be counted by 9 is stored as data.

For example, the output value of the latch circuit 22 is 100.
If the decoder output is 0 (“0” if dark, “1” if bright), the address input 100
The value 95 to be output next is stored for 0,
This is output, and in the next field, this value is output from the latch circuit 22 to the counter 19. When the output of the latch circuit 22 is 100 and the decoder output is 1, R
The value 105 to be output next is stored for the address input 1001 of the OM 21, and this value is output. In the next field, this value is output from the latch circuit 22 to the counter 1
9 is output.

As described above, the count value to be counted next by the counter 19 is stored as data corresponding to all cases considered as address input. Incidentally, when it is bright but not too bright and not too dark, that is, when the output of the LPF 9 is between V1 and V2,
A signal is output from the decoder 13 to the latch circuit 22 to inhibit a new latch and maintain the output as it is.
Therefore, the output of the latch circuit 22 does not change.

According to the present embodiment, since the data to be stored can be made arbitrary corresponding to the address input, it is not always necessary to keep the change rate constant. For example, when the shutter speed is slow, the change rate is low. Is 10%, but the rate of change of shutter speed can be made constant, such that the rate of change is 1% when the shutter speed is fast. However, in order to prevent hunting, it is necessary to prevent the rate of change from exceeding a certain value, for example, 10%. As described above, according to the present embodiment, the optimum shutter speed can be changed according to the shutter speed at each time.

FIG. 5 is a circuit block diagram showing the essential parts of a third embodiment of the electronic iris control circuit of the video camera of the present invention. In this embodiment, the number of comparison circuits 11 and 12 is increased,
The output of the low-pass filter 9 is evaluated in 5 levels (3 levels in the case of the second embodiment), and is one of five states: very bright, bright, normal (no need to change the brightness), dark, and very dark. It was decided which state it was in, and when it was very bright or very dark, the rate of change in shutter speed was larger than when it was bright or dark.

Therefore, the output of the decoder 13 to the ROM 21 is not 1 bit but 2 bits. That is, 00 is very bright, 01 is bright, 10 is dark, and 11 is very dark. In the ordinary case, the decoder 13 outputs a latch inhibit signal to the latch circuit 22 to inhibit a new latch. Table 3 below shows R
The relationship between the address input of the OM 21 and the stored data is shown.

[0047]

[Table 3]

As is clear from Table 3, four kinds of data are stored as the count values to be counted by the counter 19 next by the decoder output even if the latch output is the same. According to the electronic iris control circuit of such a video camera, the change rate of the brightness on the subject side is increased by increasing the change rate in the case of very bright and very dark than in the case of bright and dark. The shutter speed change rate can be changed against
The iris can be changed quickly to respond to drastic changes in brightness.

FIG. 6 is a circuit block diagram showing the essential parts of a fourth embodiment of the electronic iris control circuit of the video camera of the present invention. In the present embodiment, in the case of frame reading, one shutter pulse is forcibly input to the solid-state imaging device 2 at a time point approximately midway between adjacent read pulse generation times.

Reference numeral 23 denotes a shutter pulse compulsion circuit for generating one shutter pulse at a time point approximately midway between adjacent read pulse generation times in frame reading, and 24 receives outputs from the shutter pulse generation circuit 20 and the shutter pulse compulsion circuit 23. , A logical sum circuit that generates a logical sum output and sends it as a shutter pulse to the solid-state imaging device 2. The shutter pulse forcing circuit 23 does not generate a shutter pulse in the case of field reading.

In this way, in the case of frame reading,
The shutter pulse is forcibly input to the solid-state imaging device 2 for about one time at the time when the adjacent read pulse is generated for the following reason. 7A and 7B are time charts for explaining the reason, and FIG. 7A shows the case of field reading, and FIG. 7B shows the case of frame reading.

In the case of field reading, a charge reading pulse (ROG) is generated for each field, and the storage time is 1/60 seconds at maximum, which can be shortened in 1H steps by a shutter pulse. Then, in order to prevent hunting and to increase the control speed, the technical measures such as those of the first to third embodiments have been made, and the output of the shutter pulse generation circuit 20 of the electronic iris control circuit 8 of the video camera is obtained. The shutter pulse is sent to the solid-state image pickup device to rationally control the iris.

However, if the electronic iris control circuit 8 of such a video camera is directly adapted to frame reading, hunting may occur. That is, in the case of frame reading, when the charge storage time is the longest, it takes 1/30 seconds, and in this case, one shutter pulse is not input. 1 depending on the light intensity change from that state
It is assumed that the state has changed to a state where a book shutter pulse is generated. Then, the accumulation time at this time becomes 1/60 second. Therefore, the rate of change in light quantity at this time is 525H-262H / 1 /
60 = 100%, which is very large, and hunting naturally occurs when the rate of change is large.

Therefore, in order to make the maximum value of the light amount change rate in the frame reading the same as that in the field reading, the accumulation time is set to 1 as shown in FIG. 7B.
The shutter pulse was always generated in the vicinity of / 60 seconds.

[0055]

According to a first aspect of the present invention, there is provided a method of driving a solid-state image pickup device, characterized in that the charge storage time is changed so that the rate of change of the charge storage time between adjacent fields or adjacent frames is always constant. Therefore, according to the driving method of the solid-state imaging device of the first aspect, there is no problem as in the prior art that the change rate of the brightness in a dark place is extremely small and the change is slow, and the charge accumulation is always performed at substantially the same change rate. Control can be performed by changing the time (exposure time), and the response speed of iris control can be increased.

An electronic iris control circuit for a video camera according to a second aspect of the present invention includes an integrating circuit for integrating the output signal of the solid-state image pickup device, a comparing circuit for comparing the output signal with a reference value, and at least for each vertical scanning period. A clock generation circuit that generates a clock pulse for each horizontal blanking period, and each accumulation start point when changing the charge accumulation time so that the rate of change of the charge accumulation time between adjacent fields or adjacent frames is always constant. A counted pulse generation circuit that generates a counted pulse corresponding to the horizontal blanking period, a count value designating circuit that increases or decreases the count value based on the output of the comparison circuit, and the counted pulse in each field or each field. A counter that counts up to the count value designated by the count value designation circuit for each frame, and the charge read pulse A shutter pulse generation circuit that receives the output from the counter and allows the clock pulse output from the clock generation circuit to be output as a shutter pulse to the solid-state imaging device after the arrival of the charge read pulse and before the output of the counter. And are included. Therefore, according to the electronic iris control circuit of the second aspect, each charge start time is changed when the charge storage time is changed so that the rate of change of the charge storage time between adjacent fields or adjacent frames is always constant. Since the counted pulse generation circuit that generates the counted pulse corresponding to the horizontal blanking period is provided so that the shutter pulse may be generated only when the counted pulse is generated, there is a possibility that the shutter pulse may be generated between adjacent fields It is possible to change the charge storage time so that the rate of change of the charge storage time in step S1 is always constant. Therefore, there is no problem that the change rate of the brightness in a dark place is extremely small and the change is slow, and it is possible to control by changing the exposure time (brightness) at almost the same change rate. The response speed of iris control can be increased.

According to another aspect of the electronic iris control circuit of the video camera of the present invention, the counted pulse generation circuit counts clock pulses when a charge read pulse arrives and gives an address to the address counter, and an adjacent field or an adjacent frame. The address of the clock pulse generated at each horizontal blanking period, which is the starting point of each accumulation when the charge accumulation time is changed so that the change rate of the charge accumulation time is always constant, is stored in advance. Storage means for generating a signal each time the output address of the address counter coincides with the output address.
Therefore, according to the electronic iris control circuit of the video camera of the present invention, the charge accumulation time is changed by the storage means so that the change rate of the charge accumulation time between adjacent fields or frames is always constant. The address (number) of the clock pulse at the time of starting the storage is stored, and the pulse counted by the counter is thinned out by the storage means so that the rate of change of the charge storage time is always constant. The rate of change of can be constant.

An electronic iris control circuit for a video camera according to a fourth aspect of the present invention has a solid-state image pickup device, and adjusts the charge accumulation time by a time interval between a shutter pulse for discharging charges applied to the solid-state image pickup device and a charge read pulse. In the electronic iris control circuit of the video camera, an integrating circuit for integrating the output signal of the solid-state image pickup device, a comparing circuit for comparing the output signal of the integrating circuit with a reference value, and a horizontal return signal for at least each vertical scanning period. A clock generation circuit that generates a clock pulse for each line period, a counter that starts counting the clock pulse generated from the clock generation circuit each time each accumulation time starts, and a current count value that the counter counts. A signal that increases or decreases the count value based on the comparison result of the comparison circuit is received as an address input, and Storage means for storing, as data, the optimum count value to be counted by the counter next time corresponding to each address input, receiving the charge read pulse and the output of the counter, and receiving the charge read pulse from the counter. A shutter pulse generation circuit that outputs the clock pulse, which is the output of the clock generation circuit, as a shutter pulse to the solid-state imaging device until the carry output is received. Therefore, according to the electronic iris control circuit of the video camera of claim 4, the optimum value is always stored as a new charge storage time to be switched from the current light amount and the current charge storage time (shutter speed). Since it is stored in the means, it is possible to always control the charge storage time (shutter speed) that is optimal for the condition at each time.

In the electronic iris control circuit of the video camera according to the present invention, the size of the count value (increase / decrease rate) increased / decreased by the storage means according to the size of the difference between the video signal compared in the comparison circuit and the reference value. ) Was made different. Therefore, according to the electronic iris control circuit of the video camera of the present invention, the count value can be greatly increased or decreased when the difference between the video signal and the reference value is large. The control speed of the charge storage time when the difference from the value is large can be increased.

The electronic iris control circuit of the video camera according to a sixth aspect of the present invention, in the case of frame reading, a frame for generating a shutter pulse of one pulse input to the solid-state image pickup device at a time substantially midway between the times of generation of adjacent charge reading pulses. It is characterized by having a shutter pulse forcing circuit for reading. Therefore, according to the electronic iris control circuit of the video camera of claim 6, in the frame read mode, the shutter pulse is forcibly input to the solid-state imaging device at almost every intermediate point between the adjacent charge read pulses.
The rate of change when the charge storage time decreases from the maximum is 100.
It is possible to prevent the% from increasing and to obtain the same change rate as in the field read mode. Therefore, the electronic iris control circuit of the same video camera can be used for both field reading and frame reading.

[Brief description of drawings]

1A and 1B show an embodiment of the present invention, FIG. 1A is a circuit block diagram of an electronic iris control circuit, and FIG. 1B is a time chart.

FIG. 2 is a diagram showing an example of a time chart when the present invention is applied to an electronic iris control circuit having a wide iris dynamic range.

FIG. 3 is a circuit block diagram of a second embodiment of the electronic iris control circuit of the video camera of the present invention.

FIG. 4 is a circuit block diagram showing a main part of a second embodiment of the electronic iris control circuit of the video camera of the present invention.

FIG. 5 is a circuit block diagram showing a main part of a third embodiment of the electronic iris control circuit of the video camera of the present invention.

FIG. 6 is a circuit block diagram showing a main part of a fourth embodiment of the electronic iris control circuit of the video camera of the present invention.

FIG. 7 is a time chart in the case of field reading and frame reading for explaining the necessity of forcibly generating a shutter pulse at the time of frame reading.

8A and 8B show a conventional example of an electronic iris control circuit, FIG. 8A is a circuit block diagram of an electronic iris control circuit, and FIG. 8B is a time chart.

[Explanation of symbols]

 2 solid-state imaging device 9 integration circuit 11, 12 comparison circuit 14 count value designation circuit 15 clock generation circuit 16 address counter 17 storage means 18 counted pulse generation circuit 19 counter 20 shutter pulse generation circuit 21 storage means

Claims (6)

[Claims] 1. A method of driving a solid-state imaging device, wherein signal charges generated in a plurality of photoelectric conversion elements arranged in a matrix are transferred by a transfer unit and output, and a charge accumulation time is changed to control an accumulated charge amount. In, the change rate of the charge accumulation time (ratio between the charge accumulation time of one field or frame and the charge accumulation time of the next field or frame) when changing the charge accumulation time between adjacent fields or adjacent frames is always Driving method of solid-state imaging device characterized by changing charge accumulation time so as to be constant 2. An electronic iris control circuit for a video camera, comprising a solid-state imaging device, wherein the charge accumulation time is adjusted by a time interval between a shutter pulse for discharging charges applied to the solid-state imaging device and a charge reading pulse. An integrating circuit for integrating the output signal of the solid-state imaging device, a comparing circuit for comparing the output signal of the integrating means with a reference value, and a clock generating circuit for generating a clock pulse for each horizontal blanking period at least in each vertical scanning period. The pulse to be counted is set in correspondence with the circuit and the horizontal blanking period, which is the start point of each accumulation when changing the charge accumulation time so that the rate of change of the charge accumulation time between adjacent fields or adjacent frames is always constant. A counted pulse generation circuit that generates, a count value designation circuit that increases or decreases the count value based on the output of the comparison circuit, A counter that counts the count pulse for each field or each frame until it reaches the count value designated by the count value designation circuit, and receives the charge read pulse and the output of the counter,
A shutter pulse generation circuit that outputs the clock pulse, which is the output of the clock generation circuit, as a shutter pulse to the solid-state image pickup device until the carry output of the counter is received after the charge read pulse arrives. Electronic iris control circuit of camera 3. The count pulse generation circuit counts clock pulses when a charge read pulse arrives and gives an address to the address counter, and the rate of change of charge accumulation time between adjacent fields or adjacent frames is always constant. When the address of the clock pulse generated at each horizontal blanking period, which is the start point of each charge accumulation when changing the charge accumulation time, is stored in advance, and the address and the output address of the address counter match. 3. An electronic iris control circuit for a video camera according to claim 2, further comprising storage means for generating a signal for each. 4. An electronic iris control circuit for a video camera, comprising: a solid-state imaging device, wherein the charge accumulation time is adjusted by a time interval between a shutter pulse for discharging charges applied to the solid-state imaging device and a charge reading pulse. An integrating circuit for integrating the output signal of the image pickup device, a comparing circuit for comparing the output signal of the integrating means with a reference value, and a clock generating circuit for generating a clock pulse in each horizontal blanking period at least in each vertical scanning period. A counter that starts counting the clock pulse generated from the clock generation circuit each time each accumulation time starts, a current count value to be counted by the counter, and the count result based on the comparison result of the comparison circuit. Receives a signal to increase / decrease the value as an address input, and corresponding to each address input, Storage means for storing count value for counting the data, receiving the output of said charge readout pulse and the counter,
A shutter pulse generation circuit that outputs the clock pulse, which is the output of the clock generation circuit, as a shutter pulse to the solid-state image pickup device until the carry output of the counter is received after the charge read pulse arrives. Electronic iris control circuit of camera 5. The size of the count value increased / decreased by the storage means is made different according to the size of the difference between the video signal compared in the comparison circuit and the reference value. 4. Electronic iris control circuit for video camera described in 4. 6. A frame reading shutter pulse compulsory circuit for generating a shutter pulse of one pulse input to the solid-state image pickup device at a time point substantially midway between the generation times of adjacent charge reading pulses during frame reading. Item 2. Electronic iris control circuit for video camera according to item 2, 3, 4 or 5.