JP3134585B2 - Electronic iris control circuit and camera having the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic iris control circuit, and more particularly to an electronic iris control circuit for detecting an average value of a video signal based on signal charges accumulated in a plurality of pixels of a solid-state imaging device and sequentially transferred, and using one or a plurality of comparison circuits. Comparing the comparison reference value with the detected value of the average value of the video signal to detect which of the plurality of divided areas obtained by dividing the detected value between the highest value and the lowest value. An electronic iris control circuit that controls the accumulation time in each pixel by controlling the timing of transmitting a shutter pulse for discharging the signal charge from each pixel of the solid-state imaging device based on the detection result; and Related to the equipped camera.

[0002]

2. Description of the Related Art In general, a solid-state image sensor, for example, a CCD type solid-state image sensor, sweeps signal charges accumulated in each photoelectric conversion element in the solid-state image sensor to an overflow drain region or a semiconductor substrate side by applying a shutter pulse. The exposure time can be changed by adjusting the charge accumulation time in the field period by applying a shutter pulse.

Incidentally, the control of the charge accumulation time by the shutter pulse is performed in units of 1H (horizontal cycle). This is because the application timing of the shutter pulse is limited to the horizontal retrace period. The reason why the application timing of the shutter pulse is limited to the horizontal retrace period is to prevent noise from entering the video signal.

[0004] Some video cameras using such a solid-state image sensor utilize its electronic shutter function for iris control. FIG. 2A shows such an electronic iris control circuit, and FIG.
4 is a time chart for explaining the operation of the electronic iris control circuit. In the drawing, 1 is a lens, 2 is a solid-state imaging device, 3 is a sample-and-hold circuit for taking out the output of the solid-state imaging device 2, 4 is an AGC circuit, 5 is a gamma correction circuit, 6
Denotes a white clip circuit, and 7 denotes a black clip circuit. Reference numeral 8a denotes a conventional example of an electronic iris control circuit, which comprises a low-pass filter 9 for integrating the output of the sample hold circuit 3, comparison circuits 10a and 10b, and a shutter control circuit 10.

[0005] The low-pass filter 9 serves to detect the overall (average) brightness of the screen by integrating the output of the sample-and-hold circuit 3, and to compare the comparison circuits 10a and 10a.
0b is the brightness detection value and a reference value V different from each other.
1 and V2, and if the detected value is greater than V1,
If the output of the low-pass filter 9 is higher than the reference value V1, the shutter control circuit 11 increases the shutter speed, and if the output of the low-pass filter 9 is lower than V2, the shutter speed is increased. Works to reduce speed. And V2 lower than V1
If it is higher, the shutter speed will not change. V
_BLK is a vertical blanking signal, X _SG1 is a read signal (ROG), HD is a horizontal synchronization signal, X _SUB (1) to
(N) is a shutter pulse for commanding sweep-out in each of the other examples.

The exposure time of the solid-state imaging device is the longest in the case of X _SUB (1), and X _SUB (2), (3), (4),.
It is possible to make the length shorter in units of the horizontal cycle (IH). The exposure time is 1 after the generation of the read signal _XSG1.
This is the time from the time when the last shutter pulse among the shutter pulses generated in the H cycle is generated to the time when the next read signal _XSG1 is generated. Such an electronic iris control circuit controls the generation of the shutter pulse so that the charge accumulation time is short when the image is too bright, and is long when the image is too dark. Therefore, the brightness of the screen is substantially stable, that is, the video signal can maintain a constant luminance level.

[0007]

FIG. 2 (A)
In the conventional electronic iris control circuit shown in FIG. 2, as shown in FIG. 2B, the comparison circuits 10a and 10b always operate, and the output of the low-pass filter 9 is output regardless of the vertical blanking period or the vertical effective period. If there is a change, the comparison circuit 10
a, the output of the comparison circuit 10b could change. This change in the output is a large and drastic change in the amplitude between Vcc (for example, 5 V) and 0 V, and has a very large adverse effect on the weak video signal due to crosstalk, causing noise on the screen and deteriorating the image quality. Was a factor.

The present invention has been made to solve such a problem, and it is intended to prevent a change in the output of a comparison circuit from adversely affecting a video signal during a vertical effective period, thereby preventing the image quality from deteriorating. Aim.

[0009]

An electronic iris control circuit according to a first aspect of the present invention is characterized in that the comparison circuit is operated only during a vertical blanking period. Claim 2
A camera according to claim 1, further comprising an electronic iris control circuit according to claim 1. The electronic iris control circuit according to claim 3 is a delay circuit for receiving a vertical blanking signal and delaying the same by an integer multiple of a horizontal period, and an enable for sending an enable signal having a certain pulse width from an output of the delay circuit to a comparison circuit. It has a signal generation circuit. A camera according to a fourth aspect is provided with the electronic iris control circuit according to the third aspect.

[0010]

According to the electronic iris control circuit of the first aspect and the camera of the second aspect, since the comparison circuit operates only during the vertical blanking period, there is a possibility that the output of the comparison circuit will change during the vertical effective period. Absent. Therefore, there is no possibility that the output video signal of the solid-state imaging device is adversely affected by the comparison circuit during the vertical effective period, and there is no possibility that the image quality is reduced.

Therefore, it is possible to prevent the image quality from deteriorating due to the output of the comparison circuit. According to the electronic iris control circuit according to the third aspect and the camera according to the fourth aspect, the vertical blanking period is delayed by an integer multiple of the horizontal period by the delay circuit, and the pulse is generated by the enable signal generation circuit. As a result, it is possible to operate the comparison circuit only during the vertical blanking period.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electronic iris control circuit according to the present invention will be described in detail with reference to the illustrated embodiments. 1A and 1B are diagrams for explaining one embodiment of the electronic iris control circuit of the present invention, wherein FIG. 1A is a circuit diagram and FIG. 1B is a time chart. The electronic iris control circuit of the present embodiment is different from the electronic iris control circuit of FIG. 2 only when the comparison circuits 10a and 10b receive an enable signal.
Then, a pulse is generated at a specific time in the vertical blanking period by the delay circuit 12 and the NAND circuit NAND, thereby
It is greatly different in that it is applied as an enable signal to 0a and 10b, however, it is common in other points, and the common points have already been described, so the description is omitted, and only the differences are described. I do.

In FIG. 1, reference numerals 10a and 10b denote comparison circuits configured to operate only when an enable signal is received. Reference numeral 12 denotes a delay circuit in which four flip-flops F / F are continuously connected. The delay circuit 12 receives the horizontal synchronization signal HD as a clock pulse and delays the vertical blanking signal V _BLK . Specifically, the delay circuit 12 obtains a signal obtained by delaying the vertical blanking signal by three horizontal periods from the first horizontal synchronization signal HD after the start of the vertical blanking period.

The NAND is a NAND circuit which receives an output signal of the delay circuit 12 and a signal obtained by inverting an output signal of the flip-flop F / F immediately before the last stage, and has an enable signal having a pulse width of one horizontal cycle. Occurs. NAND circuit N
The output of the AND is input to the comparison circuits 10a and 10b as an enable signal. The comparison circuits 10a and 10b can operate only during a period in which the enable signal is received.

According to such an electronic iris control circuit, since the comparison circuits 10a and 10b operate only when receiving the enable signal generated only during the vertical blanking period, the output signals of the comparison circuits 10a and 10b become vertical. It does not change during the validity period. Therefore, it is possible to completely eliminate the possibility that the video signal is adversely affected by the crosstalk due to the change in the output signals of the comparison circuits 10a and 10b, noise appears on the screen, and the image quality deteriorates.

It should be noted that there is no restriction that the enable signal must be generated at a time 3H later than the start of the vertical blanking period within the vertical blanking period. What is necessary is just to prevent the comparison circuits 10a and 10b from operating due to the generation of the enable signal during the vertical effective period.

[0017]

According to the electronic iris control circuit of the camera of the first or second aspect, the comparison circuit is operated only during the vertical blanking period. Therefore, according to the electronic iris control circuit of the camera of claim 1 or claim 2, since the comparison circuit operates only during the vertical blanking period, the output of the comparison circuit may change during the vertical effective period. There is no. Therefore, there is no fear that the output video signal of the solid-state imaging device is adversely affected by the comparison circuit during the vertical effective period. Therefore,
It is possible to prevent image quality deterioration due to a change in the output of the comparison circuit.

According to a third or fourth aspect of the present invention, the electronic control circuit for a camera receives a vertical blanking signal and delays the signal by an integral multiple of a horizontal period, and a certain pulse width from an output of the delay circuit. And an enable signal generation circuit for generating a pulse having the same.
Therefore, according to the electronic iris control circuit of claim 3 or claim 4, the vertical blanking period is delayed by an integer multiple of the horizontal period by the delay circuit, and the pulse is generated by the enable signal generation circuit. By applying the enable signal to the comparison circuit, the comparison circuit can be operated only during the vertical blanking period.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams for explaining an embodiment of an electronic iris control circuit of the present invention, in which FIG. 1A is a circuit block diagram, and FIG. 1B is a time chart showing an operation. .

FIGS. 2A and 2B are diagrams for explaining a conventional example of an electronic iris control circuit, and FIG. 2A is a circuit block diagram;
(B) is a time chart showing the operation.

[Explanation of symbols]

2 ... solid-state imaging device, 8 ... electronic iris control circuit, 9 ... low-pass filter, 10a, 10b ... comparison circuit, 12 ... delay circuit, NAND ... enable signal generation circuit

Claims (4)

(57) [Claims] An average value of a video signal based on signal charges accumulated in a plurality of pixels of a solid-state imaging device and transferred sequentially, and a comparison reference value and an average value of the video signal are detected by one or more comparison circuits. The solid-state imaging device detects which of the plurality of divided areas obtained by dividing the detected value by comparing the detected value with the highest value and the lowest value, and based on the detection result. In an electronic iris control circuit for controlling the accumulation time in each pixel by controlling the timing of transmitting a shutter pulse for discharging the signal charge from each pixel, the comparison circuit is operated only during a vertical blanking period. Electronic iris control circuit characterized by comprising 2. A solid-state image sensor and a plurality of pixels of the solid-state image sensor which are accumulated and sequentially transferred.
The average value of the video signal due to the
Number of comparison circuits
Value is compared with the detected value, and the detected value is
To which of the multiple divided areas obtained by dividing between the values
The solid-state imaging based on the detection result.
A shutter for discharging the signal charge from each pixel of the element
-By controlling the pulse transmission timing,
Control the accumulation time in the pixel, and
Operating the comparison circuit only during the vertical blanking period
And an electronic iris control circuit configured as described above. 3. An average value of a video signal based on signal charges accumulated in a plurality of pixels of a solid-state imaging device and sequentially transferred, and one or a plurality of comparison circuits calculate a comparison reference value and an average value of the video signal. The solid-state imaging device detects which of the plurality of divided areas obtained by dividing the detected value by comparing the detected value with the highest value and the lowest value, and based on the detection result. An electronic iris control circuit that controls the accumulation time in each pixel by controlling the timing of sending a shutter pulse that causes the signal charge to be discharged from each pixel, receives a vertical blanking signal, and multiplies it by an integer multiple of the horizontal period A delay circuit for delaying, and an enable signal generating circuit for generating a pulse having a certain pulse width from an output of the delay circuit in a vertical blanking period. An electronic iris control circuit, wherein an output pulse of the enable signal generation circuit is applied as an enable signal to the comparison circuit. 4. A solid-state image sensor and a plurality of pixels of the solid-state image sensor, which are accumulated and sequentially transferred.
The average value of the video signal due to the
Number of comparison circuits
Value is compared with the detected value, and the detected value is
To which of the multiple divided areas obtained by dividing between the values
The solid-state imaging based on the detection result.
A shutter for discharging the signal charge from each pixel of the element
-By controlling the pulse transmission timing,
Electronic iris control circuit for controlling the accumulation time in pixels
And receives the vertical blanking signal and divides it into the horizontal
Circuit for delaying an integer multiple of the period, and whether the output of the delay circuit
Pulse with a certain pulse width during the vertical blanking period
And an enable signal generation circuit generated in the
And an output pulse of the enable signal generation circuit.
It is applied as an enable signal to the comparison circuit.
Camera and an electronic iris control circuit, comprising the the