JPS62200312A - Picture signal amplifying circuit for focus detector - Google Patents

Abstract

PURPOSE:To detect stably the focus even if an object is dark, by amplifying the picture signal from a self-scanning type image sensor to such a degree of amplification that a ratio of a monitor signal to a reference voltage is fixed and by performing an arithmetic processing. CONSTITUTION:The luminance of the object is detected by a light receiving means 1 for monitor. A monitor circuit 2 is set to a prescribed level by a storage electrode reset pulse of the image sensor and generates a monitor signal which falls at a speed corresponding to the luminance of the object simultaneously with extinction of the reset pulse. A comparing circuit 4 generates an input signal of a shift pulse generating means 3 when the monitor signal is lower than a reference voltage Vr1, and a timer means 5 generates the input of the means 3 if the monitor signal is not lower than the voltage Vr1 a prescribed time after the generation of the reset pulse. A monitor signal VM from the circuit 2 is stored in a storage means 6 at the same timing as the shift pulse. An amplifying part 7 amplifies the picture signal form the image sensor in accordance with an amplification degree G given by a formula, and thus, the focus is stably detected even if the object is dark.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an image signal amplification circuit for a focus detection device.

(Prior art) Conventionally, the focus detection device of a camera was disclosed in Japanese Patent Application Laid-Open No. 10151-1983.
As is known from Publication No. 6, the focus of the camera is detected by amplifying the image signal from the charge-coupled device and performing arithmetic processing. A monitor signal from a monitor circuit in the coupling element is compared with a reference voltage, and the degree of amplification of the image signal is changed in several stages according to the result.

For example, the amplification degree was changed by 2 times, such as 1 times, 2 times, 4 times, and 8 times, and there was no amplification degree in between.

However, with this focus detection device, the amplification degree of the image signal is changed stepwise, so when performing focus detection on a subject with slightly low contrast, focus detection will be incorrect if the subject is so bright that the amplification degree of the image signal is exactly double. However, if the subject becomes slightly brighter than that and the amplification degree of the image signal becomes 1x.

If the amplification is insufficient, focus detection cannot be performed correctly, and focusing cannot be achieved by focus adjustment.

(Objective) It is an object of the present invention to provide an image signal amplification circuit for a focus detection device that eliminates the above-mentioned drawbacks and can smoothly change the amplification degree of the image signal and stabilize focus detection even when the subject is dark. .

(Structure) The present invention relates to a focus detection device that detects the focus of a camera by processing an image signal from a self-scanning image sensor having a storage electrode and an analog shift register for transferring stored charges. As shown in FIG. 1, the apparatus includes a monitor light receiving means 1, a monitor circuit 2, a shift pulse generating means 3, a comparison circuit 4, a timer means 5, a storage means 6, and an amplifying section 7.

The brightness of the subject is detected by the monitor light receiving means 1,
A monitor circuit 2 generates a monitor signal that is set to a predetermined level by a reset pulse that resets the storage electrode of the image sensor, and is reduced at a speed corresponding to the brightness of the subject at the same time as the reset pulse disappears by the output signal of the monitor light receiving means 1. Occur. The shift pulse generating means 3 generates a shift pulse to shift the charge of the storage electrode to the analog shift register in response to a predetermined input signal, and the comparator circuit 4 generates a shift pulse when the monitor signal from the monitor circuit 2 falls below a predetermined reference voltage. The shift pulse generating means 30 generates an input signal. When the monitor signal does not drop to the reference voltage even after a predetermined period of time has elapsed since the generation of the reset pulse, the timer means 5 generates an input signal for the shift pulse generating means 3, and the storage means 6 stores the shift pulse and the input signal. The monitor signal from the monitor circuit 2 is stored at approximately the same timing. Then, the amplification section 7 converts the image signal from the image sensor into a relationship between the monitor signal VM stored in the storage means 6 and the reference voltage rl (Vrl) such that G=-- (K is an arbitrary constant). Amplify with the amplification degree G.

Next, examples of the present invention will be described.

FIG. 2 shows an embodiment of a focus detection device to which the present invention is applied.

When the ST/TO signal sent to the microcomputer (CPU) 11 pulse generation circuit 12 changes from H (high level) to L (low level), the pulse generation circuit 12 generates a reset pulse φR to generate a self-scanning image. sensor
Send to 13. This image sensor 13 uses a charge-coupled device and receives light from the subject through the camera's photographing lens and focus detection optical system, and the storage electrode is reset by the reset pulse φR and output from the monitor circuit. Voltage vM0 and reference voltage vref are set to predetermined voltages. When the reset pulse φR disappears, the output voltage VMO of the monitor circuit decreases at a speed corresponding to the brightness of the subject, and the reference voltage Vref maintains a substantially constant voltage. The signal processing circuit 14 uses the output voltage Vpit o of the monitor circuit as a reference voltage Vref.
When the output voltage VM o of the monitor circuit exceeds the first reference voltage, the AGCE signal to the pulse circuit 12 is set to H and the integration of the charge-coupled device 13 is completed. is notified to the pulse generation circuit 12.

When the AGCE signal becomes H, the pulse generation circuit 12 sends a shift pulse φT to the charge-coupled device 13, and
PUII K IE multiplication signal sending Also informs the CPUI 1 that the integration of the charge-coupled device 13 has ended. Charge record/
The combining element 13 transfers the charge of the storage electrode to the analog shift register by the shift pulse φT, and the pulse generating circuit 12
The charges are sequentially transferred from the analog shift register to the image signal V by the transfer pulses φ1 and φ2 that re-run 7 times from
o Lightning voltage and send it to the signal processing circuit 14. Signal processing circuit 1
4, the image signal vo is amplified to a level suitable for the input terminal of the Ω converter 15 in the CPU 11 and sent to the Ω converter 15 as a VOA signal.

The pulse generating circuit 12 still generates a signal A synchronized with the voA signal.
Send DS to CPU II. Pulse generation circuit 12 υIE
The CPU II receiving the signal synchronizes with the ADS signal and outputs the VOA.
The signal is converted from analog to digital by the Ω converter 15 and stored in an internal memory, and the data in this memory is processed to detect the focus of the camera and determine the amount of defocus of the photographing lens.

FIG. 3 shows the structure of the charge-coupled device 13. As shown in FIG.

The charge-coupled device 13 includes a monitor photodiode 1 near the photodiode array 16 for detecting subject brightness.
It has 7. Further, in the charge coupled device 13, the monitor circuit includes a monitor photodiode 17 and field effect transistors 18, 19 . The reference voltage circuit used for generating a reference voltage is composed of a field effect transistor 22, a capacitor 23, and a buffer amplifier 24. Further, the image signal output circuit includes a field effect transistor 25, a capacitor 26, and a buffer amplifier 27.

When the reset pulse φR is input to this charge-coupled device 13, the charge on the storage electrode 28 is reset, and
Field effect transistor 19.22 is turned on and capacitor 20.23 is charged to a predetermined voltage by power supply voltage VDD. The voltage of this capacitor 20.23 is outputted as a monitor signal vM and a reference voltage Vref via buffer amplifiers i21 and i24. Reset pulse φ
R disappears. ! :, food diode 1 for mo=p-
The charge in the capacitor 20 is discharged by the photocurrent flowing through the capacitor 7, and the voltage of the monitor signal VMO decreases. Here, since the photocurrent flowing through the monitor photodiode 17 increases or decreases in accordance with the brightness of the subject, the voltage drop rate of the monitor signal VMO corresponds to the brightness of the subject. The photodiode array 16 receives light from an object, and a photocurrent flows through the photodiode array 16, and charges are accumulated in the storage electrode 28 due to this photocurrent. When the shift pulse φT is input, the shift gate 29 is turned on by the shift pulse φT, and the charge on the storage electrode 28 is transferred to the analog shift register 30. The analog shift register 30 transfers the charge and locks φ1
．． φ2Vc is sequentially transferred to discharge the capacitor 26, and the voltage is transferred to the image signal Vo via the buffer amplifier 27.
is output as

The field effect transistor 25 is reset by being turned on by the transfer pulse φ1 and charging the capacitor 26 to a predetermined voltage. In the photodiode array 16, a few pittles on the side near the output end for more than 10 bits are shielded from light by an aluminum electrode, etc., and the image signal from this light shielding part is used as a reference signal for the darkness level when amplifying the image signal v0. be done.

FIG. 4 shows the configuration of the pulse generating circuit 12, and FIG. 6 shows a timing chart of this embodiment.

When the power of this embodiment is turned on, the π signal output from the ICCPU II resets the flip-flops SRI, SR2 and flip-flops FF3, FF7, and also resets the flip-flop FF5 via the inverter INVIO1NOR gate G11. Also, flip-flop FF4 is set. When the ST/TO signal sent from CPU 1 changes from H to L, this signal is applied to the input terminal SIR of the shift register SRI, and the clock φ is divided into 1/16 by the 7 lip-flop FF2 and the counter CNT. are sequentially shifted in shift register SRI. NAND game) G3
The ST/To signal is inverted by the inverter INV1 and inputted, and the output signal from the fourth bit output terminal QD of the shift register SRI is inputted to the NAND.
The output signal of the gate G3 is inverted by the inverter INV3 and sent to the stain coupling element 13 as a reset pulse φR. A signal from the third bit output terminal QC of the shift register SRI is input to the NAND gate G2, and a signal from the fourth bit output terminal Q of the shift register SRI O is input after being inverted by the inverter INV2.
The output signal of G2 is inverted by the inverter INV4 and becomes the φR8 signal.

This φR3 signal is used as a reset pulse φ as shown in FIG.
It is generated 2 to 3 clocks later than R by the clock of the shift register SRI, and the end of the pulse coincides with the reset pulse φR. f kneepalsteal. NOR Kate Gl, G
The R-S Fritz FF7, which is composed of NAND gates G6.4, is reset by the φR3 signal.
G8 is a NOR gate) Opened by the output signal of Gl 0 Here, the φR8 signal is output from the reset pulse φR is the reset pulse φR, which is output from the charge coupled device 13 when the charge coupled device 13 is reset. Even when the reset pulse φR is applied to the charge-coupled device 13, there is a time delay before the reference voltage Vref and the monitor signal vMo reach a predetermined value, and as will be described later, these signals pass through the signal processing circuit 14 and are converted into an AGCE signal. earlier than the time delay that occurs before reaching the NAND gate G8 (if the NAND gate G8 is opened, the AGCE signal before being reset by the reset pulse φR will be
Since the integration end signal is output immediately after being input from D gate G8, AGCE, which is the input signal to NAND gate G8, is output after reset pulse φR is output.
This is to allow the NAND gate G8 to open after a period of time has elapsed for the signal to properly enter the reset state.

NAND game) The output signal of G3 is set as a child signal to flip-flop FFI.
The IE multiplied signal, which is the output signal of , is set to H. The clock φ supplied from the CPU II is frequency-divided by 1/2 by the D flip-flop FF2, and is input to the clock input terminal CK of the shift register SR2 and the counter CNT. The output signals of the third to sixth bit output terminals Q3 to Q6 of the counter CNT are input to the NOR gate (G9), and the output signals are input to the NOR gate (G9).
The output signal of 9 is transferred to the charge coupled device 13 as a transfer pulse φ1.
It is inverted by an inverter INV7 and sent to the charge-coupled device 13 as an inverted pulse φ2. Still, the pulse φ2 from the inverter INV7 is sent to the CPUI 1 as an ADS signal, and the output signal from the signal processing circuit 14 (the image signal Vo from the charge-coupled device 13 is amplified to a level suitable for the input voltage of the Ω converter 15). It is used as a synchronizing signal when converting the signal vOA) from analog to digital.

After the reset pulse φR disappears, the charge-coupled device 13 stores a charge corresponding to the subject brightness in the photodiode array 16 in the storage electrode 28, and at the same time, the monitor photodiode 17 lowers the output voltage VMO of the monitor circuit, which will be described later. When this voltage VMO exceeds the first reference voltage, the signal processing circuit 14 changes the AGCE signal from L to H. This AGCE signal passes through G8 (NOR game) which is opened by the output signal of Gl
It is applied to the input terminal SIR of the shift register SR2 via the gate G7 and the inverter INT5. When the shift register SR2 sequentially shifts this human input signal to the third bit as shown in FIG. 6, the output signal from the third bit output terminal QC changes from H to L. This signal resets the R-S flip-flop FF7 and
Gate G6. Close G8. Therefore, the shift register SR2 changes when the human input signal at the input terminal SIR changes from L to H.
This signal is sequentially shifted. The output signals of the first to third bit output terminals QA, QB, and QC of the shift register SR2 are shifted by the synchronization amount of the input clock of the shift register SR2, and become pulses whose width is three cycles of the coterie cuff lock.

The output signal of the output terminal QB of the shift register SR2 is inverted by the inverter INV6 and sent as a shift pulse φT to the charge-coupled device 13.
8 charges are transferred to analog shift register 30.

The output signal of the output terminal 4 of the shift register SR2 is inverted by the inverter INV8 and applied to the reset terminal R of the counter ○J, so that the counter is reset. Since the counter CNT is reset earlier than the output of the shift pulse φT by one cycle of the input clock of the shift register SR2, the transfer pulse φ to the charge-coupled device 13 is
1 becomes H before the shift pulse φT is output.

Transfer pulse φ1. Even if the shift pulse φT is sent to the charge-coupled device 13 during the charge transfer to the analog shift register by φ2, the transfer pulse φ1 must become H before that, and the transfer pulse φ1 is transferred from the seed electrode to the analog shift register by the shift pulse φT. During the charge transfer, the analog shift register transfer pulse φ1. The charge transfer by φ2 is always stopped and the charges of each bit are never mixed up.

Input terminal SIR of shift register SR2, output terminal Tin-
The signal of QB is input to NOR gate G5, and the output signal of NOR gate G5 is a shift pulse φ as shown in FIG.
It becomes a slightly wider pulse at almost the same timing as T,
It is sent to the signal processing circuit 14 as an AGC-S/H signal and becomes a sample hold pulse for storing the monitor circuit output voltage at the end of integration of the charge coupled device 13.

The output signal from the output terminal QB of the shift register SR2 is outputted as a shift pulse φT via the inverter INV6 as described above, and is also sent to the R-S flip-flop FF.
It is applied to the reset terminal R of I to reset the R-S flip-flop FFI and change the IE multiplied signal from H to L. C.P.
UII knows that the integration of the charge-coupled device 13 is completed because the IE multiplied signal has changed from H to L, and the signal processing circuit 1
4 (a signal obtained by amplifying the image signal V from the charge-coupled device 13) voA, preparations are started for analog/digital conversion. CPU 1 is sent at the same timing as the transfer pulse φ2, and when the ADS signal changes from H to L, the converter 15 in CPU II
The input voltage, ie, the image signal VOA, is instructed to be converted from analog to digital.

If the IE multiplied signal does not change from H to L even after a predetermined time (referred to as the first reference time) after the CPU II changes the ST/To signal from H to L, in other words, the brightness of the subject is dark and the output voltage of the monitor circuit The output voltage Vy1 of the monitor circuit remains low even after the first reference time has elapsed due to the slow decreasing speed of VMO.
If o does not exceed the first reference voltage, CPU II
Change the T/To signal from L to H.

This completion/TO signal is applied to NAND gate G6,
AND gate G6 is opened by the output signal of R-S flip-flop FF7. Therefore, when the ST/To signal changes from L to H, a foot pulse φT and an AGC-S/H pulse are generated by the same operation as when the above-mentioned AGCE signal is applied to the NAND gate G8. 13 integrals are completed.

Note that CPU 1 outputs the IE multiplication signal H before the first reference time elapses.
If the image signal voA becomes L from
After all bits of analog/digital conversion are completed, the η TO signal is set to H. At this time, the output signal of the R-S flip-flop FF7 has already become L and the NAND game) G6
is closed, and input terminal SIR of shift register SR2
No signal is transmitted to

The CPU II sets the LL terminal to H when the IE multiplied signal does not change from H to L even after a second reference time shorter than the first reference time has elapsed. At this time, the two terminals of the pulse generation circuit 12 are set to the pulse φR (pulse obtained by inverting IJ set Hapal 1) from the NAND gate G3, and the non-inverted output signal and the inverted output signal are used to switch the analog switch. (transfer game)) AS50 opens and analog switch AS51
Since it is closed, it is already functioning as an input terminal. When the LL terminal becomes H, the D flip-flop FF
4 and NAND gate G10, only the rising edge of the signal at the LL terminal is made into a short pulse signal. This pulse resets the D flip-flop FF3 and closes the analog switch AS50.
By opening, the LL terminal of the pulse generation circuit 12 changes from an input terminal to an output terminal. Further, the output pulse of the NAND gate G10 is applied to the clock input terminal CK of the D flip-flop FF5 via the inverter INV9. At this time, if H is input as an LLC signal from the signal processing circuit 14 to the data terminal of the D flip-flop FF5, the non-inverted output signal of the D flip-flop FF5 becomes H, and this signal is passed through the resistor R50 to the transistor Q5.
0 pace, transistor Q50 is turned on. An auxiliary light source is connected to the collector of the transistor Q50, and when the transistor Q50 is turned on, the auxiliary light source lights up and illuminates the subject. The inverted output signal of D flip-flop FF5 is sent to analog switch AS51.
is sent to CPU II via. The CPU II knows whether the auxiliary light source is turned on based on the inverted output signal (LL terminal voltage) of the D flip-flop FF5. When the auxiliary light source is turned on, the CPU 1 sets a third reference time that is longer than the first reference time. When the auxiliary light source is turned on and the IE multiplied signal from the pulse generation circuit 12 does not reach the L level even after the third reference time has elapsed, the CPU II is ST/T.

The signal is changed from L to H17C to end the integration of the charge coupled device 13. Also, the ST/To signal from CPUI 1 is D
The output signal of the flip-flop FF5 passes through the NMD gate G12, which is opened, and is applied to the set terminal S of the R-S flip-flop FF6, setting the R-S flip-flop FF6 and causing its inverted output signal to become L!
+ is sent to the signal processing circuit 14 as an OFF SET signal. Then, the pulse output from the NAND gate G3 is applied to the reset terminal R of the D flip-flop FF5 via the inverter INVII and the NOR gate G11, and the D flip-flop FF5 is reset.

FIG. 5 shows the configuration of the signal processing circuit 14.

Image signal V sent from the charge coupled device 13.

The reference voltages Vr e f are respectively applied to the buffer amplifiers B2. It is input to Bl. Buffer amplifier B2.

The difference between the output signals of B1 and B1 is calculated by a differential amplifier composed of resistors R1 to R4 and an operational amplifier A1. An offset voltage of an intermediate potential VD between the power supply voltage (10V) and the ground potential (GND) is applied to this differential amplifier. Therefore, the output voltage VOAI of operational amplifier A1
If R3=R1 and R4=R2, then VOAI=V
D (Vref - Vo ) 0°1 - (1)
becomes. The output signal of operational amplifier A1 is applied to the non-inverting input terminal of operational amplifier A2, while the output signal of analog switch A
SI, resistor R5, capacitor C1 and buffer amplifier B
It is also applied to the sample and hold circuit composed of 3. The analog switch ASI outputs the sample hold signal S/H sent from the CPU II to the inverter INV2.
1. It is applied via INV22 and turned on/off. When the data of the part of the image signal from the CPU II that is blocked by the aluminum electrode of the photodiode array 16 (dark data) is being sent, the analog switch ASI is turned on, and the dark data is transferred to the capacitor CI. It is held and becomes the output voltage of buffer amplifier B3. The output voltage V of the buffer amplifier B3 is applied to the resistor R6. When the voltage difference between B3 and the output signal VOAI of the operational amplifier A1 is added and the current flowing through the resistor R6K is 11, the following equation is obtained. Since a current approximately equal to 11 flows through the collector of transistor Q2, the voltage VBEQ2 between the base and emitter of transistor Q2O is generally expressed by the following equation.

k: Boltzmann constant q: Electron charge T: Absolute temperature coefficient s: Reverse saturation current resistor R12 connected to the output terminal of the buffer amplifier B1
, R13, and R14K are constant current circuits constituted by transistors Q1o to Q16 and variable resistor VRI, through which a constant current flows, and a voltage drop occurs in each resistor R12, R13, and R14. The voltage generated by resistor R12 is
The reference voltage Vrl is the reference voltage Vrl, the voltage generated by the resistor R14 is the second reference voltage vr2, and the voltage generated by the resistor R13 is the third reference voltage vr3. The first reference voltage is applied to the non-inverting input terminal of operational amplifier A3. Resistor R7
If the current flowing through is 12, then it becomes. Since a current approximately equal to 12 flows through the collector of the transistor Q4, the voltage VBEQ between the base and emitter of the transistor Q4 is as shown in equation (3). The monitor circuit output voltage VM sent from the charge-coupled device 13 is inputted via the buffer amplifier B6 and resistor R11 to a sample-and-hold circuit composed of an analog switch AS2, a resistor R8, a capacitor C2, and an operational amplifier A4. The AGC-S/H signal output from the pulse generation circuit 12 is sent to the control gate of the analog switch AS2. Since the AGC-S/H signal is output at approximately the same timing as the shift pulse φT, the sample and hold circuit samples and holds the monitor circuit output voltage immediately after the integration of the charge coupled device 13 is completed. If the difference between this sampled and held voltage and the reference voltage is VAGC, the current i3 flowing through the resistor R9 is as follows. Transistor Q6. Q7. The collector current of Q8 is almost the same as that of i3, so the transistor Q
The voltage between the base and emitter of 8, Vn E Q8, is (3)
Similarly to Eq. From equations (3) and (5) σ, the base-emitter voltage VBEQ9 of transistor Q9 is: VRIG9 ” VRIG2 +VBEQ4- VBE
It becomes Qs. Next, when the voltage across the resistor RIO is VRIG, the current i4 flowing through the resistor RIO is as follows. The voltage VBBQ9 between the base and emitter of the transistor Q9 is determined as follows in the same manner as in equation (3).If 14 is obtained from equation (10), it becomes as follows. (1
Substituting equation (8) into equation (1) yields. Therefore, VRI
O is, and substituting equations (2), (4), and (6) into equation (13) yields RIO. Here, (VOB a VOAI) is VAN
, R9/R7=. Since VRIO/VIN is the amplification degree of this amplification section, if this is G, then the following equation is obtained.

The second reference voltage Vrz is applied to the non-inverting input terminal of operational amplifier A5. Operational amplifier A5 constitutes a first limiter circuit together with diode DI.

The monitor circuit output voltage vMo from the charge-coupled device 13 is connected to the inverting input terminal of the operational amplifier A5.
is applied via the resistor R11.

When the monitor circuit output voltage does not fall to the second reference voltage, the first limiter circuit lowers the second reference voltage vr2.
A voltage equal to is input to the analog switch AS2 of the sample and hold circuit.

The first reference voltage Vr1 is applied to the non-inverting input terminal of the operational amplifier A6, and the operational amplifier A6 constitutes a second limiter circuit together with the diode D2. Stage amplifier A6
The monitor circuit output voltage VM o from the charge-coupled device 13 is connected to the 0 inverting input terminal of the buffer amplifier B6 and the resistor R11.
is applied via. The monitor circuit output voltage is the first
When the reference voltage exceeds the reference voltage, the second limiter circuit
A voltage equal to the reference voltage Vrl of is input to the analog switch AS2jC of the sample and hold circuit. Therefore, the output of the sample and hold circuit is a held voltage between the second reference voltage and the first reference voltage.

The voltage at the connection point between the output terminal of the operational amplifier 6 and the diode D2 is approximately near OV when the monitor circuit output voltage is within the first reference voltage, and the AGCE signal to the pulse generation circuit 12 is set to L. When the monitor circuit output voltage begins to drop at the same time as the reset pulse φR disappears and exceeds the first reference voltage, the voltage at the connection point becomes approximately the reference voltage vref minus the first reference voltage Vri, and the AGCE signal changes. It becomes H. This signal is sent to the pulse generating circuit 12, and as mentioned above, a shift pulse φT is generated.
etc. to complete the integration of the charge-coupled device 13. The resistors R17 and R18 and the Zener diode ZD2' are used to match the output voltage of the operational amplifier A6 and the input level of the pulse generating circuit 12.

The third reference voltage is applied to the inverting input terminal of the comparator A7, and the monitor circuit output voltage VM o of the charge-coupled device 13 is applied to the non-inverting input terminal of the comparator A7 via the buffer amplifier B6.

When the monitor circuit output voltage exceeds the third reference voltage, the output signal of comparator A7 becomes L, and this signal becomes LL.
It is sent to the pulse generation circuit 12 as a C signal. As mentioned above, the pulse generation circuit 12 checks the state of the LLC signal using the signal from the CPU II to the LL terminal, and turns on the auxiliary light source.
Turn off the lights. Resistors R15, R16 and Zener diode ZDI are used to match the output voltage of comparator A7 to the level of pulse generating circuit 12.

First, second, and third reference voltages Vrt l Vr2+ V
The magnitude relationship of r3 is Vr 1 > Vr 2 > Vr 3
It is set so that The second reference voltage essentially limits the minimum value of VAGC in equation (15),
In this example, Vrl is 3V and Vrz is 375mV.
By setting υ to have a maximum amplification factor of 8 times, VR in equation (13) can be kept constant while the monitor circuit output voltage is between Vrl and Vrz. . Since the relationship between the second and third reference voltages, the first reference time T1, and the second reference time π is T2 Vr3 TI Vr2, the relationship between the monitor circuit output voltage and Vr2 is expressed as φT. You can know when the second reference time has arrived before the output is output. So T2/Tl =
If it is 0.1, Vr3 will be 37.5 mV.

Resistor R19, transistor Q17. A constant current flows through the resistor R20 by the bias current circuit composed of Q18. A constant voltage VR2° is generated across the resistor R20, and a voltage added to the intermediate voltage VD as an offset voltage is applied to one end of the resistors R, ], O via a buffer amplifier B5. The CPU II converter 15 is at ground potential (
GND) to the intermediate potential VD is divided into 256 bits by 8 bits.

Normally, objects have bright and dark parts, and the dark parts are not completely black.

Therefore, when looking at the image signal from the charge-coupled device 13, the signal from the dark part of the object is usually much higher than the signal from the aluminum covered part of the photodiode array. Therefore, by adding an offset voltage to the image signal VOA to the Ω converter 15 so as to match the level of the image signal corresponding to the dark part of the object to the lower limit of the manual power range of the AD Ω converter 15, the increase rate of the amplification section can be adjusted to Therefore, the range of the Ω converter 15 can be used effectively. VR20 is used as its offset voltage.

The analog switch AS3 is connected to the pulse generation circuit 12.
The FF SET signal is applied via the inverter INV24, which turns on when the OFF SET signal is L, shorting both ends of the resistor R20 and setting the offset voltage to Ov.

The OFF SET signal is output as L from the pulse generation circuit 12 when the auxiliary light source is turned on and the aforementioned third reference time has elapsed. When the 0FFSET signal becomes L under these conditions, the image signal from the charge-coupled device 13 is extremely small, and if the offset voltage continues to be applied, even if the amplification factor of the amplification section in this embodiment is maximized, Since the output signal VOA cannot have sufficient amplitude and level, most of it will be in the offset voltage mentioned above.
An input signal that satisfies the cooling converter 15 cannot be obtained. Therefore, in such a case, the portion hidden by the offset voltage is input to the D converter 15 as the offset voltage Ov. This makes it possible to focus even on low-brightness subjects.

FIG. 7 shows a part of the processing flow of CPU II.

When the power is turned on, the CPU 1 sets the R signal to L in step S1 to reset the pulse generation circuit 12, and in step S2 sets the S T/T O signal to L to cause the pulse generation circuit 12 to generate a reset pulse φR, etc. Let them do it.

Next, the CPU II sets the LL terminal as an output terminal in step S3, sets the LL terminal to L in step S4, and checks whether 10 m5 (second reference time) has passed since ST/To becomes L in step S5. Find out whether or not. If the second reference time has not elapsed, the process proceeds to step S6 to check the IE multiplication signal, and if the IE multiplication signal is L, the process proceeds to step S7.
If the IE multiplication signal is H, the process returns to step S5.

If the second reference time has elapsed in step S5, the process proceeds to step S8, where the LL terminal is set to H and the pulse generating circuit 1
Step 2 sets the output terminal of the LL terminal, etc., sets the LL terminal as an input terminal in step S9, and proceeds to step S10.
Check the IE times signal. If this IE multiplied signal is L, the process proceeds to step S7, but if the IE multiplied signal is H, step Sll is reached.
Check the LL terminal. If the subject is of high brightness and the LL terminal is H, it is checked in step Sll whether 100m5 (first reference time) has passed since the ST/To signal became L, and the first reference time is determined. If not, step S
Return to IO. If the first reference time has elapsed, step S1
At step 3, the ST/TO signal is set to H, causing the pulse generating circuit 12 to generate a shift pulse φT, etc., and the process returns to step SIO.

If the object is of low brightness and the LL terminal is L in step Sll, it is checked in step S14 whether 200 m5 (third reference time) has elapsed since ST/To became L, and the third If the reference time has not elapsed, the process returns to step SIO. If the third reference time has passed, step S
At step 13, the ST/To signal is set to H, causing the pulse generator 12 to generate a shift pulse φT, etc., and the process returns to step SIO.

When the process proceeds to step S7 with the IE double signal L, it is possible to accept interrupts for analog/digital conversion, and in step S15, the C
Set the CD counter CD to 1. Next step S16
The ADS signal is checked, and if the ADS signal is H, the ADS signal is checked repeatedly. When the ADS signal becomes L, the process proceeds to step S17, where it is checked whether the CCD counter CN is 8 or not.
If the CCD counter CN is not 8, it is checked in step S18 whether the CCD counter CN is 15 or more. The photodiode array 16 of the charge-coupled device 13 has four output terminals.
The bits are dummy and the next 10 bits are shielded from light by aluminum electrodes.If the CCD counter CN is not 15 or more, the process proceeds to step S21, where the CCD counter CN is incremented, and in step S22, the CCD counter becomes 1.
Check whether it is 28 or more. CCD counter CN is 128
If not, the process returns to step S16, and when the CCD counter CN reaches 8, steps S17 to S25
and wait for about 20 μs. Next, in step S26
By setting the /H signal to L and waiting for approximately 50 μs in step S27, and setting S/H to H in step 828, the signal processing circuit 14 is caused to sample and hold the light shielding portion data from the charge-coupled device 13, and the process proceeds to step S21. move on. Further, when the CCD counter CN becomes 15 or more, step S1
8, the process proceeds to step S19 and waits 20 to 28 μs after the ADS signal becomes L. In step S20, the image signal VoA from the signal processing circuit 14 is converted from analog to digital by the 0 converter 15 and stored in the memory, and step S
Proceed to step 21. When the CCD counter CN reaches 128,
Proceeding to step S23, interrupts for analog/digital conversion are prohibited, and ST/T is performed in step S24.

Set the signal to H. Further, the CPU 1 outputs a free-run pulse φ to the pulse generating circuit 12, performs arithmetic processing on the data in the memory, and detects the focus of the camera.

(Effects) As described above, according to the present invention, the monitor signal from the monitor circuit is stored at almost the same timing as the shift pulse of the self-scanning image sensor, and the monitor signal vM stored in this storage means is used as a reference. Since the image signal is amplified, the amplification degree of the image signal changes smoothly even when the subject is dark, making focus detection stable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of a focus detection device to which the present invention is applied, and FIG. 3 is a diagram illustrating the configuration of a charge-coupled device in the same embodiment. 4 and 5 are block diagrams showing the respective configurations of the pulse generation circuit and signal processing circuit in the same embodiment, FIG. 6 is a timing chart of the same embodiment, and FIG. 7 is a block diagram showing the configuration of the pulse generation circuit and signal processing circuit in the same embodiment. 3 is a flowchart showing a part of the processing flow of FIG. 1... Monitor light receiving means, monitor circuit, 3...
Shift pulse generating means, 4... Comparison circuit, 5... Timer means, 6... Storage means, 7... Amplifying section. Engraving of drawings (no change in content) Side (Figure 7 Procedure amendment (method) % formula % 1 Indication of incident Patent application No. 42849 of 1988 2 Name of invention Image signal amplification circuit of focus detection device 3 Correction Relationship with the case involving a person who does
Address: 4-5-4-6 Kyodo, Setagaya-ku, Tokyo Drawing subject to correction Surface 7 Contents of correction

Claims (1)

[Claims] In a focus detection device that detects the focus of a camera by processing an image signal from a self-scanning image sensor having a storage electrode and an analog shift register for transferring stored charge, the focus detection device includes a monitoring light receiving means for detecting the brightness of a subject; , a monitor circuit that generates a monitor signal that is set to a predetermined level by a reset pulse that resets the storage electrode of the image sensor and that decreases at a speed corresponding to the brightness of the subject at the same time as the reset pulse disappears by the output signal of the monitor light receiving means; , shift pulse generating means for generating a shift pulse for shifting the charge of the storage electrode to the analog shift register in response to a predetermined input signal; a comparator circuit that generates an input signal for the generation means; and a timer that generates an input signal for the shift pulse generation means when the monitor signal does not drop to the reference voltage even after a predetermined period of time has elapsed since the generation of the reset pulse. storage means for storing the monitor signal from the monitor circuit at substantially the same timing as the shift pulse; and storage means for storing the monitor signal from the monitor circuit at substantially the same timing as the shift pulse, and storing the image signal from the image sensor into the monitor signal V_M stored in the storage means and the reference voltage Vr_1. On the other hand, G=K・V
Amplification degree G in the relationship r_1/V_M (K is an arbitrary constant)
An image signal amplification circuit for a focus detection device, comprising an amplification section for amplifying the image signal.