JPS62163009A - Auto focusing device - Google Patents

Abstract

PURPOSE:To permit auto focusing with high accuracy by setting the gain and offset value of an amplifier by the combination of the output signals from contrast detecting means and average value detecting means. CONSTITUTION:The gain of the amplifier A11 is set by controlling paired analog switches As1, As2, As3 and As4, As5, As6 according to the outputs of G output terminals G1, G2, G3 of a central processing unit AF CPU 21 for auto focusing. The AF CPU 21 calculates the value of C/L and determines the offset voltage of the output amplifier A11 for a photodetector of a charge accumulation type (CCD). The AF CPU 21 sets the output terminals 1-4 of Vs in accordance with the determined value of Vs and sets the offset voltage of the output amplifier A11 for the CCD. The set offset value is impressed through a buffer amplifier A10 to the other terminal of the resistance gamma of the (+) input of the amplifier A11 by turning-on of any among the analog switches As7-As10. The gain of the output amplifier A11 for the CCD is thus determined by the signal L indicating luminance and the signal C indicating contrast.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to an autofocus device that can be used in various cameras, and in particular, to an autofocus device that can perform highly accurate autofocus even for subjects with low contrast and brightness. Regarding the autofocus device used.

(Prior Art) There is an autofocus system that uses a charge storage type light receiving element (hereinafter referred to as rCCDJ) that receives light from a subject that has passed through a photographic lens. In such an autofocus device, since the output of the COD is converted into a digital signal and used for calculation, the output level of the CCD is set to a predetermined level suitable for human power of an analog-to-digital converter (hereinafter referred to as "notification converter"). The amplitude must be within a certain range, and the amplitude must be greater than a certain level.

However, as shown in Figure 2(a), the output level of the CCD is at an appropriate level depending on the subject.
In cases where the contrast is small and the shift is small, or when the contrast is small (Fig.
As shown in a), the overall output of the CCD may be small. In such cases it is impossible to detect the focus.

(Purpose) The purpose of the present invention is to measure the contrast and brightness on the CCD before AD converting the output of the CCD, which is a light receiving element for autofocus, and to adjust the output of the CCD based on the contrast and brightness information signals. To provide an autofocus device that performs amplification and offset to obtain the contrast and level necessary for calculation, and performs highly accurate autofocus even for subjects for which conventional calculations have been difficult.

(Structure) As shown in FIG. 1, the present invention includes a load-accumulating type light-receiving element 11 at 7 that receives the light of the subject that has passed through the engraving lens; A drive circuit 12 for driving, at least two monitor photodiodes 13 for monitoring the charge accumulation state of the light receiving element 11, a monitor signal forming means 15 generated by the monitor photodiodes 13, and at least two monitors formed. At least two monitors formed of a contrast detection means 16 for checking a difference in signals and outputting a signal according to the difference, an amplifier 17 with variable gain and offset for amplifying the luminance signal from the light receiving element 11; Average value detection means 18 outputs a signal according to the average value of the signal, and when the output of the average value detection means 18 reaches a predetermined level, the light receiving element 11
A transfer pulse generating means 19 generates a pulse to transfer the accumulated charges of to the shift register, and when the output of the average value detecting means 18 does not reach a predetermined level even after charge accumulation has elapsed for a predetermined time, a transfer pulse is generated. It has a timer 20 for generating a transfer pulse from the generating means 19, and sets the gain and offset values of the amplifier 17 by a combination of the output signal of the contrast detecting means 16 and the output signal of the average value detecting means 18. Features.

Embodiments of the autofocus device according to the present invention will be described below with reference to FIGS. 2 to 7.

In FIG. 4, C
As is well known, the CD is a photodiode array 111.
, a storage electrode 112, a shift gate 113, and a CCD analog shift register 114, and is configured to receive light from a subject that has passed through a photographic lens. Near the photodiode array 111, a CCD
Two monitor photodiodes 13a monitor the charge accumulation state in 11.

13b is arranged. The CCD 11 is driven by a drive circuit 12 based on instructions from an autofocus central processing unit (hereinafter referred to as "CPU J").

Ql and Q3 are turned on when the reset pulse φR from the 1 drive circuit 12 is at H level, and the capacitors C1 and C
2 to the power supply voltage Vdd. Q2 and Q4 are monitor photodiodes 13
This is a useless transistor in which a and 13b are set to approximately zero bias. When light enters the CCD 11, a photocurrent flows through the monitor photodiodes 13a and 13b, discharges the capacitors CI and C2, and discharges the transistors Ql and Q3.
It is designed to lower the source voltage of the Monitor photodiodes 13a, 13b.

Capacitors C1, C2, transistors Ql, Q2
, Q3゜The part including Q4 is the monitor signal forming means 15
It consists of This monitor signal forming means 15 outputs the source voltages of the transistors Ql and Q3, respectively, to the monitor photodiode 13a,
13b, and these two monitor signals are sent to the Banfa amplifier AI + A2.
It is output to the outside of CCDII through . Analogon 7
+-L/ output of sister 1171) is input to floating gate transistor Q5, and transistor Q5
charges the capacitor C3 in accordance with the signal from the shift register 11.1. The terminal voltage signal of capacitor C3 is
It is outputted to the outside as a luminance signal of the CCD 11 via the buffer amplifier A3.

Each output of the buffer amplifiers AI and A2 is further connected to a buffer amplifier A4. Two monitor signals VMI via A5
, VM2 are input to the contrast detection means 16 and the average value detection means 18. Contrast detection means J
6 is two arithmetic intensifiers A6. It has an absolute value differential amplifier 23 having A7, and is configured to obtain a difference signal VIMI -M21 between the absolute values of the two monitor signals VM s + VM 2 by this absolute value differential amplifier 23. . The contrast detection means 16 also includes three comparators CPI and C which receive the difference signal of the absolute value as a comparison input.
It has F2 and CF2. This each comparator CPI
, CF2, and CF2 are applied with reference voltages Vt+ + Vt2+ Vt3 obtained by dividing the power supply voltage VDD by resistors R11, R12, R13, and R14, respectively. The relationship between this reference voltage Vt and +Vtz r Vt3 is as follows: Vt 3 = 2 Vt 2 = 4 Vt
It has become l. Each comparator CPI, CF2
The output of CF2 is input to the AFCPU 21 as a contrast detection signal C.

The average value detection means 18 includes a breadth amplifier A8 and a two-piece converter CP4, CF2, CF2.
I have it. The buffer amplifier A4. The monitor signals Vold and VM2 from A5 are input to the operational amplifier A8 to perform the calculation of (VM1+VM2)/2, that is, the average value of the two monitor signals VM1 and VM2. This average value signal VM is applied to each comparator CP4.
, CF2, CF2 and transfer pulse generation means 1
The signal is input as a comparison signal to a comparator CP7 included in 9. Each of these comparators CP4, CF2,
CF2, CF2 has power supply voltage VDD connected to resistor R15.
, R16, R17, R18, and R19, reference voltages vS, l VS2 r VS3 t Vsa are applied, respectively. This reference voltage Vs+ r VS
The relationship between 2 + VS31Vs4 is VDD VS4:2(VDD -VS3):4(VD
D VS2 ) = 8 (VDD - Vss ). Each comparator CP4, CF2, C
The output of F2 is input to the AFCPU 21 as an average value signal, and the output of the comparator CP7 is input to the AFCPU 21 via an OR circuit 25 as an integration end signal.

AFCPU 21 outputs a signal from the φR terminal. This signal is applied to the drive circuit 12 and the CC
It is converted into a pulse at a level that resets DII. Further, the signal from the φR terminal is also applied to the timer 20 to start the timer 20. The timer 20 is set for a predetermined time from the start, for example, 100m5.
If VM < VS 4 does not hold even after the elapse of time, a signal is output, and this signal is manually input to the AF'' CPU 21 via an OR circuit 25 as an integration end signal.
The timer 20 may be one in which a register in the AFCPU 21 is used as a counter to operate the timer, and it is not necessarily necessary to provide a single timer.

The OR circuit 25 generates a pulse φT for transferring the accumulated charge of the CCD 11 to the shift register 114 via the drive circuit 12 when the output of the average value detection means 18 reaches a predetermined level together with the comparator CP7. A transfer pulse generating means 19 is configured. This transfer pulse generating means 19 also generates a transfer pulse when a signal is generated from the timer 20.

CCD 11 outputted via the buffer amplifier A3
The output of is sent to operational amplifier All through buffer amplifier A9.
is input. Operational amplifier All is a central component of amplifier 17 with variable gain and offset.

The amplifier All has resistors connected in pairs at both input terminals, and analog switches As1r AS2 + AS3 and AS4 r A also arranged in pairs.
The gain can be switched by selecting with ss t As6. Each of the analog switches described above is selectively operated by the gain output G of the AFCPU 21. The amplification rrA11 is also an analog switch AS7 + Ass + AS9 + As+.

An offset voltage set by selective operation of the buffer amplifier Alo is applied via the buffer amplifier Alo. Each of the analog switches described above is selectively operated by the offset setting output Vs of the AFCPU 21.

The AFCPU 21 receives the output signal C of the contrast detection means 16 and the average value detection means 1, as will be explained in detail later.
A signal G r Vs is used to set the gain and offset values of the amplifier All by combining the 8 output signals.
It is designed to output .

The luminance signal from the amplifier All is converted into a digital signal by the Ω converter 27, and is provided for calculation distance measurement in the AFCPU 21.

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 and 5 to 7.

Now, when the reset signal φR is output from the AFCPU 21, this signal is sent to the drive circuit 12.
is converted into a level pulse that resets the CCDII
Furthermore, the reset timer 20 is started by the reset signal φR. Reset pulse φR CCD1
1, CCDII is reset, and at this time, the outputs of the buffer amplifiers Al and A2, which are the outputs of the monitor photodiodes 13a and 13b, are approximately equal to the power supply voltage V.
It becomes DD.

When the reset pulses change from "H" to rLJ, the reset is canceled and the CCDII starts integrating.

The charge storage part of the CCD 11 has two photodiodes 1.
3a, 13b is monitored and buffer amplifier A
l.

Monitor signal VMI and buffer amplifier A2.A4 are output via A4. The monitor signal VM 2 outputted via A5 is input to the contrast detection means 16 and the average value detection means 18 .

The contrast detection means 16 performs a calculation increase "f%5A6-A".
7 to obtain a difference signal VIMI-M21 between the absolute values of the two monitor signals,
This is applied to each comparator CPI, CF2, CF2
to use human power.

The average value detection means 18 calculates the average value VM of the monitor signals VMI and VM2 using the operational amplifier iA8, and applies this to each of the comparators CP4, CF2, CF2, CF.
2. Manpower. A comparator CP7 included in the transfer pulse generating means 19 compares the average value vM with the reference voltage VS4, and when VM < VS 4, its output becomes r.
The signal is inverted from LJ to HJ, and an integration end signal is applied to the AFCPU 21 and the CCD drive circuit 12 through the OR circuit 25.The drive circuit 12 receives the integration end signal and converts the charge of the storage electrode 112 to the CCD analog shift register 114.
The shift pulse φT to be transferred to the shift gate 11
Add to 3.

On the other hand, upon receiving the integration end signal, the AFCPU 21 reads the outputs of the comparators CP4, CF2, CF2 and the comparators CPI, CF2, CF2. Comparators CP4, CF2, CF2
The output is as shown in Table 1 depending on the value of the average value VM of the monitor signal.

Table 1 Assuming that each comparator CP4, CF2, CF2 is treated as a binary number, CF2 is 2. CF2 2
, CF2 is 2°, then NO, 1 to 4 in Table 1 are 7.3, 1., respectively in decimal notation. It becomes O. This value plus 1 is added to the AFCPU 21 as a signal.

The AFCPU 21 uses this signal as the gain of the amplifier 17 determined by the brightness.

Next, the outputs of the comparators Cpl, CF2, and CF2 included in the contrast detection means 16 are as shown in Table 2 depending on the value of the difference VIMI-M21 between the absolute values of the monitor signals.

Table 2 Assuming that each comparator CPI, CF2, and CF2 are handled together, CPI is 22, CF2 is 21, and C
If F2 is 2°, No. 1 to 4 in Table 2 are 7.3 and 1.0, respectively, in decimal notation. Add 1 to this value as signal C and add it to AF CPU 21.
Let the signal C of PU 21 c, : be the gain of the amplifier 17 determined by the contrast.

The AFCPU 21 compares the signal R with the signal C, and sets the gain G of the output amplifier All of the CCD 11 to the value of the signal C if L>C. On the other hand, if L<C, the gain G of the amplifier All is set to the value of the signal.

Based on the value of gain G obtained in this way, AFCPU
For II, set G output terminals 1 to 3 as shown in Table 3, and
Set the gain of the CD output amplifier All.

Table 3 Specifically, each G output terminal Gl, G2 of MCPU 21
゜Each analog switch As that forms a pair according to the output of G3
s + Asz + As3 and AS4 + Ass
+ Amplifier A by controlling AS6 as shown in Table 4
A gain of ll is set.

Table 4 Furthermore, the AFCPU 21 calculates the value of 9t and determines the offset voltage of the output amplifier All of the CCD. C/L=
When Vs is set, when Vs<1, VS=1, and when vs>1, vs is set to the value of SI.

Based on the VSO value thus obtained, the AFCPU 21 sets the output terminals 1 to 4 of VS as shown in Table 5, and
Set the offset voltage of output amplifier All of D.

Table 5 Here, VAV is the average voltage of the multiplier All when the gain of the CCD output amplifier A11 is 1 and the integration end signal is output from the comparator CP7, as shown in FIG. ,AD'! Adjusted to 1/2 of the IA 270 input terminal range.

The offset voltage set as shown in Table 5 above is the analog switch AS? When any one of As+o is turned on, the amplifier A is turned on through the buffer amplifier A4o.
It is applied to the other end of the (g) input resistor r of ll.

In this way, by determining the gain of the output amplifier All of the CCD based on the signal C representing brightness and the signal C representing contrast, a voltage suitable for Ω conversion and an amplitude of You can get a big signal. For example, FIG. 2(a) shows the CCD output obtained when the object is bright but has low contrast, and the output voltage VAv is sufficient, but the amplitude is small and unsuitable for Ω conversion. Therefore, Ω
Amplification to get suitable amplitude for conversion? 3 Increase the gain of Al l to amplify the above output signal. As a result, the second
As shown in Figure (b), although the amplitude of the output signal becomes sufficiently large, the voltage also increases and exceeds the input range of AD conversion. Therefore, as described above, by controlling the offset voltage of the amplifier All, the 24th (c
), we obtain an output signal in which only the amplitude is large and the voltage level does not change. In addition, Figure 2 (
Fig. 2(c) shows the case where the offset voltage VS is set to VDD -1/2 VA v and the amplification is doubled. Indicate the case.

By the way, if the brightness of the subject is extremely low and VM < VS 4 does not hold even after 100 m5 has passed since the start of integration by the CCD 11, the timer 20 outputs an integration end signal, which is input to the AFCPU 21 and the CCD drive circuit 12. . The subsequent operation is the same as the operation after outputting the integration end signal described above. Note that under the condition that the integration end signal is output from the timer 20, the voltage level of the output of the CCD 11 is the average level of the input range suitable for Ω conversion, as shown in FIG. 3(a). It is much lower than VAV and has a much smaller amplitude, so it cannot be used for AD conversion. Therefore, according to the gain and offset control operation of the amplifier All based on the signal R and signal C described above,
In this case, the gain is increased while leaving the offset voltage as is.

Figure 3(b) shows an example in which the output of CCD 11 is amplified four times by increasing only the gain of amplifier All in this way, and both the output voltage level and amplitude are suitable for Ω conversion. You can see that it will become something like that.

Note that the number of division stages of the signal C according to contrast and the signal C according to brightness may be set arbitrarily;
The number of control stages for the gain and offset of the output amplifier may also be set arbitrarily. Also, at least two photodiodes are required to monitor the charge accumulation state of the CCD, and if the number of these diodes is increased, for example to three or four, the contrast information signal and brightness information signal can be more accurately detected. Obtainable.

(Effects) According to the present invention, at least two monitor photodiodes are provided to monitor the charge accumulation state of the light-receiving element, and the light-receiving element is output from the light-receiving element according to the contrast information signal and brightness information signal of the subject obtained by the diodes. Since the gain and offset of the amplifier that amplifies the signal is controlled, even for M objects with low contrast and brightness, it is possible to obtain an output signal suitable for Ω conversion for use in calculations. Highly accurate autofocus can be performed even for objects for which distance calculation is difficult.

[Brief Description of the Drawings] Fig. 1 is a functional block diagram showing the basic configuration of the autofocus device according to the present invention, Fig. 2 is a waveform diagram for explaining the operating principle of the inventive device, and Fig. 3 is the same. FIG. 4 is a circuit diagram showing an embodiment of the autofocus device according to the invention, FIG. 5 is a flowchart showing the operation of the same embodiment, and FIG. Similarly, FIG. 7 is a timing chart showing the operation in a case different from that shown in FIG. 6, and is a timing chart showing the operation of the above embodiment. 11... Light receiving element, 12... 1 drive circuit, 13...
・Monitor photodiode, 15...Monitor signal forming means, 16...Contrast detection means, 17...Amplifier, 18...Average value detection means, 19...Transfer pulse generation means, 20... timer. zuJ [Tsum(a,) (3) (C)Uσ
Measure (p) Maximum θ measure 70 Procedural amendment dated March 12, 1985 1, Indication of case Patent Application No. 4854 of 1988 2, Title of invention Autofocus device 3, Person making the amendment Case and Relationship Patent applicant name (674) Ricoh Co., Ltd. 4, Agent
Address: 4-5-4-5 Kyodo, Setagaya-ku, Tokyo, "Detailed Description of the Invention" section of the specification subject to amendment and drawings (1) "Signal C" in line 8, page 15 of the specification. ” was changed to “signal”. (2) Change "Signal L" in the first O line of the same page to "Signal C". (3) Figure 5 of the drawing is revised as attached.

Claims (1)

[Scope of Claims] A charge accumulation type light receiving element that receives light from a subject transmitted through a photographic lens; a drive circuit that drives the light receiving element; and at least two devices that monitor the charge accumulation state of the light receiving element.
a monitor photodiode; a monitor signal forming means produced by the monitor photodiode; a contrast detecting means for checking a difference between at least two monitor signals formed and outputting a signal corresponding to the difference; an amplifier with variable gain and offset for amplifying the luminance signal from the monitor; an average value detection means for outputting a signal corresponding to the average value of the at least two monitor signals formed; transfer pulse generating means for generating a pulse for transferring the accumulated charge of the light receiving element to the shift register when the charge is accumulated; and a timer for generating a transfer pulse from the transfer pulse generation means, and is characterized in that the gain and offset values of the amplifier are set by a combination of the output signal of the contrast detection means and the output signal of the average value detection means. autofocus device.