JPS6255754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging device, and in particular, when an image is scanned by a solid-state imaging device, a dark current signal generated inside the solid-state imaging device and the dark current signal are detected by the solid-state imaging device. A differential circuit subtracts the dark current signal from the scanning signal to obtain an imaging signal for the image, and an integral time control circuit outputs the solid-state imaging signal based on the level of the imaging signal. The present invention relates to further improvements in an imaging device designed to control the image signal integration time of an element.

In recent years, solid-state imaging devices such as charge-coupled devices (CCDs) have come to be used in various fields, but the output of solid-state imaging devices such as CCDs contains noise components due to internal dark current. As a result, the inherent performance of the element was often not fully demonstrated. Therefore, in an imaging device using a solid-state imaging device, it is necessary to detect the noise component caused by the dark current as described above and remove it from the output.
This has already been proposed. For example, a part of the light-receiving section of a solid-state image sensor is shielded from light so that a dark current component inside the image sensor is obtained by the light-shielding section, and the obtained dark current component is held and subsequently shielded. Techniques have already been proposed in which so-called dark current compensation is performed by subtracting dark current from the scanning signal obtained by a light receiving section.

On the other hand, in order to expand the dynamic range of solid-state image sensors with respect to the luminance of incident light, it is necessary to control the charge accumulation time, that is, the integration time of the optical signal, and this has already been done. Proposed. For example, it is possible to detect a specific level, such as a peak level, of a scanning signal obtained from a solid-state image sensor and find out what kind of relationship this has with a predetermined voltage range, that is, whether it falls within the voltage range or not. The scanning signal is determined by determining whether it is above or below this, and if it is above this, the integration time is made shorter, and if it is below this, it is made longer. Techniques have already been proposed for controlling the integration time so that the peak level falls within the predetermined voltage range.

However, when the two techniques of dark current compensation of the scanning output from the solid-state image sensor and control of the signal integration time based on the level of the scanning signal are used in combination, the following disadvantages may occur. There may be concerns. That is, for example, when an optical signal is being integrated by a solid-state image sensor under the longest integration time that can be controlled by an integration time control circuit, the intensity of light incident on the light receiving section suddenly and extremely increases. In such a case, the intensity of light leakage from the light receiving part to the light shielding part increases, and the amount of accumulated charge in the light shielding part increases extremely.
When reading the scanning output from the solid-state image sensor, the dark current signal of the scanning output that is subsequently read out because the level of the dark current signal held by the dark current signal holding circuit increases extremely. After the dark current component is removed by the compensation (or removal) circuit (usually this is a differential circuit), the level of the scanning signal becomes very low, which causes the level of the scanning signal detected by the peak detection circuit to be very low. Because the peak level decreases, the signal integration time of the solid-state image sensor would normally have to be changed to a shorter time, but there was a concern that the signal integration time would remain fixed at the longest integration time mentioned above. be. Of course, the risk of such inconvenience is not limited to cases where a light-shielding part for detecting dark current components is provided in a part of the light-receiving part of a solid-state image sensor. Even when trying to compensate for dark current by detecting charges generated inside an analog shift register as a dark current component, a so-called blooming phenomenon occurs due to a sudden increase in the brightness of light incident on the light receiving section. The outflow charge due to diffusion at this time causes the CCD analog shift.
If the CCD analog shift register itself flows into the register, or the photoexcitation at this time generates charges within the CCD analog shift register itself, resulting in a significant increase in the dark current charge. In addition to the above-mentioned method based on the peak level of the scanning signal, there are also methods for determining whether the integration time is appropriate, such as based on the average level of the scanning signal. or alternatively, for example, US Pat. No. 4,004,852
The same problem can occur in the case of a method based on the count value of "1" or "0" after the binarization processing of the scanning signal as disclosed in No. This is a fatal defect that inevitably occurs when two techniques are used in combination: dark current compensation of the scanning output of the solid-state image sensor and control of the signal integration time based on the level of the scanning signal.

Generally, in the case of an imaging device using a solid-state imaging device, the control range of the signal integration time of the solid-state imaging device is determined in advance by assuming the brightness conditions where the imaging device will be used, and then determining the minimum and maximum brightness levels. The upper and lower limits are usually determined according to the brightness level, but the phenomenon that the level of the scanning signal is still too low even when the integration time is controlled to the upper limit, that is, the maximum time, is In addition to situations in which the brightness is so low that it is not suitable for use with the imaging device, there are also cases in which the brightness is extremely high, as described above, and as a result, the signal level of the dark current component becomes extremely high. In many cases, the device finds itself in a situation where the signal is increasing, and in the latter case, by switching the signal integration time of the solid-state image sensor to a shorter time side, the device can again generate an appropriate scanning signal. Therefore, in this respect, as mentioned above, there are two methods: dark current compensation of the scanning output of the solid-state image sensor and control of the signal integration time based on the level of the scanning signal. When using a combination of technologies, certain considerations are required.

The present invention has been made in view of the above-mentioned circumstances, and has two functions: dark current compensation of the scanning output from the solid-state image sensor and control of the image signal integration time based on the level of the scanning signal. An imaging device that uses a combination of techniques, specifically, when scanning an image with a solid-state imaging device, a dark current signal generated from the solid-state imaging device inside the solid-state imaging device; A differential circuit subtracts the dark current signal from the scanning signal to obtain an imaging signal for the image, and an integral time control circuit outputs a scanning signal containing the imaging signal based on the level of the imaging signal. As an imaging device configured to control the image signal integration time of the image sensor, it is possible to detect images that are seen when the incident light brightness increases rapidly under a relatively long image signal integration time, as described above. It is an object of the present invention to provide a more advantageous improvement that can surely eliminate the fear of inconvenience that signal integration time control progresses to an unfavorable state and maintain good image signal integration time control even in such a situation. With this objective in mind, the imaging device of the present invention provides the above-mentioned difference while the image signal integration time of the solid-state image sensor is adjusted to the longest controllable integration time by the integration time control circuit. By detecting that the level of the imaging signal from the dynamic circuit has fallen below a predetermined level, the integration time of the image signal of the solid-state imaging device to be set by the integration time control circuit is reduced to a shorter integration time. This device is characterized by being equipped with a reset circuit for resetting.

According to the embodiments of the present invention described below,
The level of the imaging signal from the differential circuit is adjusted to the predetermined level while the reset circuit is adjusted to the longest controllable integration time of the image signal of the solid-state image sensor by the integration time control circuit. When the level of the image signal remains below the level for a predetermined period of time, the image signal integration time of the solid-state image sensor to be set by the integration time control circuit is reset to a shorter integration time as the predetermined time elapses. However, this is because the sudden increase in the brightness of the incident light is instantaneous, and therefore the brightness of the incident light returns to its original level during the next image scan. There are often cases where it seems that
This was devised from the perspective that in such cases it would be better not to change the integration time unnecessarily, and it is especially useful for the above-mentioned fluctuations in incident light brightness. It is.

According to another embodiment, the reset circuit is configured to control the differential signal while the image signal integration time of the solid-state image sensor is adjusted to the longest controllable integration time by the integration time control circuit. The solid-state image sensor to be set by the integral time control circuit when the level of the imaging signal from the circuit is lower than the predetermined level and at this time, the illuminance level of the image is equal to or higher than the predetermined level. It is disclosed that the image signal integration time of the image signal is configured to be reset to a shorter integration time. The level of development is too low.
There are two situations in which the intensity of the incident light is so low that it is unsuitable for use with an imaging device, and another in which the intensity of the incident light is extremely high.
As a result, in view of the fact that the signal level of the dark current component can occur in the same way in both states, such as when the signal level of the dark current component is extremely increased, the difference between these states can be distinguished, and the integration time can be calculated only in the latter case. This is very useful in that a proper scanning signal can be obtained by resetting the .

Incidentally, according to the embodiment, the above-mentioned shorter integration time to be reset by the above-mentioned reset circuit is the shortest controllable integration time or a relatively short time close to this; Considering that the above-mentioned inconvenience is likely to occur when the luminance increases extremely, it would be most effective to use the shortest integration time. However, it goes without saying that this is by no means absolute, and is determined as appropriate depending on the purpose of use of the imaging device.

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, Figure 1 shows the incident light intensity on the solid-state image sensor and its corresponding signal integration time, that is, the accumulation time (here, for example, in 8 steps from t ₁ to t ₈ , t ₁ is the shortest and t ₈ is the longest). This shows the relationship with the image signal output. U _MAX and U _MIN are the upper and lower limits of a predetermined appropriate range set for the peak value of the image signal output, and if the peak value of the image signal output exceeds these upper and lower limits, that is, the upper limit is reached. The accumulation time ( _t1 to _t8 ) is controlled so that when it exceeds the lower limit or falls below the lower limit, it returns to the appropriate range.

Next, Figure 2 schematically shows the relationship between the fluctuations in the dark current signal level caused by the outflow of excess charge due to blooming or the wrap-around of light, and the resulting fluctuations in the output after dark current compensation. It is.

A and B are signal waveform diagrams when the solid-state image sensor outputs image information in time series, and D ₁ to _{D 3} are outputs S ₁ to _{S 5} of the dummy pixel section for dark current signal detection.
... is the output of the photosensitive pixel section. Dummy pixel section D ₁
~ D ₃ : A is the case where no blooming or light leakage occurs, and B is the case where these occur.
It is. C and D are the differential outputs obtained by subtracting the dark current signal components obtained by the dummy pixel sections D ₁ to _{D 3} from the image information including the dark current components obtained by the photosensitive pixel sections S ₁ to S ₅ . It is a signal waveform diagram. C is an output waveform that corresponds to the true image, and D is an output waveform that does not accurately correspond to the true image due to an increase in the dark current signal. In D, due to an increase in the dark current component, the peak value of the differential output signal becomes the lower limit of the above-mentioned appropriate range U _MI
Since the _accumulation time control circuit determines that the image signal level is low, it further lengthens the accumulation time, and therefore the exposure amount (integral amount) of the photosensitive pixel area further increases and the dummy The amount of excess charge flowing into the pixel area due to blooming or the amount of light entering the pixel area further increases, and as a result, the level of the differential output signal continues to decrease, and the accumulation time becomes longer. Ultimately, it is fixed at the longest accumulation time t ₈ shown in Figure 1, and the differential output signal is also permanently fixed (latched) at a level such that its peak value is less than U _MIN shown by the broken line at t ₈ . That will happen.

Next, an embodiment of the present invention aimed at preventing such inconvenience will be described.

FIG. 3 shows an embodiment of the present invention,
In the figure, SP is a solid-state image sensor such as a CCD photo diode array, and S ₁ to _{S o} are light-sensitive pixel parts D ₁ and D ₂ each consisting of n pixels, which are shielded from light by, for example, a mask MS for detecting dark current. This is the dummy pixel section. FA ₁ , FA ₂ ..., FA _n (m=n+2) integrates the charges stored in the photosensitive pixel sections S ₁ to S _o and the dummy image sections D ₁ and D ₂ by setting the clear signal ICG to high level. The integral clear gates FB ₁ , FB ₂ , ... FB _n for clearing are the charges stored in the photosensitive pixel sections S ₁ to _{S o} corresponding to the integral amount of the incident light and the dummy pixel sections D ₁ , D _{2 .} These are charge transfer gates for transferring charges corresponding to the dark current stored in the charge transfer analog shift registers CA ₁ to CA ₂ m. Analog shift register CA ₁ ~
The output charge of CA ₂ m is the resistor R ₁ , R ₂ , R ₃ and FET
Through a charge voltage conversion circuit consisting of FC ₁ and FC ₂ ,
Output as voltage information.

_AG1 is an analog gate for extracting only the signals obtained by the dummy pixel sections _D1 and _D2 from the output of the solid-state image sensor SP, followed by a hold capacitor C1, a resistor R4, and a buffer amplifier BP. constitutes a dark current signal holding circuit. The resistor R4 is a resistor for forming a low pass filter together with the capacitor _C1 , and is not necessarily required. Resistors R5, R6, R7, R8 and operational amplifier OP1 constitute a differential amplifier circuit as an operating circuit for dark current compensation, and from image information including dark current components obtained by the photosensitive pixel sections _S1 to _S0 . True image information UF is output by subtracting the dark current signal components obtained by the dummy pixels D ₁ and D ₂ held by the dark current signal holding circuit.

AG ₂ An analog gate for extracting only the signals corresponding to the photosensitive pixel sections S ₁ to _{S o} from the output of the above differential amplifier circuit; PD is the analog gate AG
The peak value of the signal obtained through 2 (hereinafter referred to as VP
PH is a peak detection circuit for detecting
is a peak hold circuit for holding the peak value VP detected by the peak detection circuit;
9, R10, and R11 are voltage dividing resistors for obtaining the above upper and lower limit reference voltages V _MAX and V _MIN . CP1 is calculated by comparing the hold value VP of the peak hold circuit PH with the upper limit reference voltage V _MAX .
A comparator that outputs a high level signal when VP>V _MAX and a low level signal when VP≦V _MAX , CP
2 is a comparator that compares the above hold value VP with the lower limit reference voltage V _MIN and outputs a high level signal when VP<V _MIN and a low level signal when VP≧V _MIN ; IV is the output of comparator CP1 The output is used as a count mode control signal for the up-down counter UDC (in this case, a 3-bit binary up-down counter) for setting the accumulation time.・Down counter UDC
granted to. Incidentally, the up-down counter UDC is set here so that it goes into the up-count mode when the output of the inverter IV goes high, and goes into the down-count mode when it goes low. OR1 is an OR gate for calculating the logical sum of the output of comparator CP1 and the output of comparator CP2, and EX is the 3-bit output Q ₁ , Q ₂ , Q ₃ of the up-down counter UDC and the output of the inverter IV. An exclusive OR gate, AN is an exclusive OR gate to take the exclusive OR of
Output of gate OR1 and exclusive or
The output of gate EX and the counting pulse CP from the timing control circuit TCC, which will be described later.
and an AND gate, the output of which is applied to the up-down counter UDC as the count clock of the up-down counter UDC. In addition, the above Exclusive or Gate EX has the shortest accumulation time t ₁
Or, when the maximum time is set to _t8 , information on shifting to a shorter or longer time side is sent to the comparator.
This is to prevent the up/down counter UDC from being reset when it is output from CP1 or CP2, and to fix the accumulation time to the currently set shortest or longest accumulation time. Incidentally, the 3-bit output _Q1 of the up/down counter UDC above
The correspondence relationship between Q ₃ and the above-mentioned 8 stages of accumulation time specified thereby is as shown in FIG.

TCC is a timing control circuit for generating various control pulses and control signals according to the timing chart shown in Figure 5, and PUC
is a reset pulse for the up-down counter UDC to initially set the charge accumulation time of the solid-state image sensor SP to the shortest accumulation time _t1 when the power is turned on, and CP is a pulse that reads the signal of the solid-state image sensor SP once. The counting pulse of the up/down counter UDC that occurs once every time (i.e.,
(accumulation time control pulse), Aφ1 sends a signal necessary for dark current detection for each readout, that is, a signal corresponding to the dummy pixel portions D ₁ and D ₂ through the analog gate AG1. A gate control signal Aφ2 for the analog gate AG1 for reading out is sent to the photosensitive pixel sections S ₁ to _{S o} out of the output of the differential amplifier circuit for each readout through the analog gate. φ R is a gate control signal for the analog gate AG2 for extracting a signal corresponding to the signal, φ _R is a peak reset control signal for resetting the peak detection circuit PD immediately after the start of each readout, and φ
_H is the peak detection value before the peak detection circuit PD is reset each time one reading is completed.
The peak hold control signal for holding VP in the peak hold circuit PH, SH is the charge transfer gate FB ₁ ~ in the solid-state image sensor SP.
Gate control pulse (shift pulse) for FB _n , ICG is also the integral clear gate FA ₁ ~
The gate control signal (integral clear signal) for FA _n , φ ₁ and φ ₂ are analog charge transfer signals.
The transfer clock pulse for the shift registers CA ₁ to CA ₂ m (that is, the analog shift registers CA ₁ to _{CA 2} m are two-phase drive type here. Also, the shift pulse SH is φ ₁ RS is also a charge-voltage conversion circuit.
This is the reset pulse for FET FC1.

The timing control circuit TCC controls the solid-state image sensor based on the time information indicated by the outputs _Q1 to _Q3 of the up-down counter UDC.
It controls the function of controlling the charge accumulation time of SP, and specifically, it controls the shift from the fall of the integral clear signal ICG to the low level, indicated by t in FIG.
Control of the accumulation time is realized by controlling the period until the rise of the pulse SH between the above eight stages _t1 to _t8 according to the states of the outputs _Q1 to _Q3 of the up-down counter UDC. It is something to do. Therefore, here, the actual charge accumulation time of the solid-state image sensor SP is "the above time t+the high level duration period Δt of the shift pulse SH". Incidentally, the above-mentioned solid-state image sensor SP is of the two-phase drive type as mentioned above, and the signals of each pixel are output in synchronization with _φ1 here, and the output starts in synchronization with the shift pulse SH. It is something to be admired.

Now, in accordance with the improvement of the present invention, a configuration for resetting the accumulation time as described below is added to the configuration of the above-described imaging device. That is, in FIG. 3, NA is a NAND gate for taking the inverse AND of the outputs Q ₁ to _{Q 3} of the up-down counter UDC, and R12 and C2 are a resistor and a capacitor that constitute a predetermined time constant circuit. ,
Tr is connected to the above capacitor C in order to operate the time constant circuit in response to the low output of the NAND gate NA.
2, R13 and R14 are voltage dividing resistors for obtaining a predetermined reference voltage, and CP3 compares the terminal voltage of the capacitor C2 with the reference voltage provided by the resistors R13 and R14 to determine the voltage at the terminal of the capacitor C2. This is a comparator that outputs a high level signal when the voltage exceeds the reference voltage, and its output is connected to the OR gate OR2, which receives the clear pulse PUC for the up-down counter UDC from the timing control circuit TCC. and the output of the OR gate OR2 is
Provided as a reset pulse to counter UDC.

Now, in the above configuration, when the power of the device is turned on, at this time, the up/down counter UDC is output from the timing control circuit TCC.
A reset pulse PUC (power up clear pulse) is output for the
is applied to the up-down counter UDC through gate OR2, and the up-down counter UDC is
Counter UDC is reset and its output Q ₁ ~ _{Q 3}
As a result, the designated storage time of the solid-state image sensor SP is initially set to the shortest storage time _t1 as shown in FIG. On the other hand, when the power is turned on, the timing control circuit TCC further sends transfer clock pulses φ ₁ , φ ₂ and a reset pulse to the solid-state image sensor SP.
At the same time as starting the output of RS, the integral clearing signal ICG is made high and the integral clearing gate FA ₁ ~
By turning on FA _n , the pixel parts D ₁ and D ₂
And accumulation of generated charges in S ₁ to S _o is prohibited. When an external trigger signal is applied to the timing control circuit TCC in this state,
In response to this trigger signal, the timing control circuit TCC immediately sets the integral clear signal ICG to low level and turns off the integral clear gates FA ₁ to FA _n , as shown in FIG. 5, thereby controlling the pixel section.
The accumulation of the generated charges at D ₁ , D ₂ and S ₁ to _{S o} is started, and at this time, the accumulation time indicated by the outputs Q ₁ to _{Q 3} of the up-down counter UDC (i.e., In this case, it starts counting the shortest time ( _t1 ), and when this timing ends, it outputs a shift pulse SH. Therefore, at this point, the charge transfer gates FB ₁ to _{FB n}
is turned on, charges accumulated in the pixel portions D ₁ , D ₂ and SD ₁ to SDn are transferred to the charge transfer analog gates through the charge transfer gates FB ₁ to _{FB n} while the above-mentioned time measurement is being performed. Shift register CA ₁ ~
After being captured in each corresponding bit of CA ₂ m, it is transferred to the charge-voltage conversion circuit through the analog shift registers CA ₁ to CA ₂ m, where it is converted into voltage and output as voltage information. Become.
Furthermore, after the timing control circuit TCC outputs the shift pulse SH, it makes the integral clear signal ICG high again and clears the integral clear gate.
By turning on FA ₁ to FA _n , the pixel section D ₁ ,
Accumulation of generated charges in D ₂ and S ₁ to _{S o} is prohibited.

Now, when the output of the scanning signal from the solid-state image sensor SP is started in this way, the timing control circuit TCC
As shown in the figure, the analog gate AG is activated at the timing when the signals corresponding to the dummy pixel parts _D1 and _D2 are output.
The analog gate AG1 is turned on by setting the gate control signal Aφ1 for dummy pixel portions D 1 and D 2 to high level, and therefore, the signals corresponding to the dummy pixel portions D ₁ and D ₂ are transferred to the dark side of the solid-state image sensor SP by the capacitor C1. The dark current signal is held as a current signal, and the held dark current signal is applied to one input of the differential amplifier circuit through the buffer amplifier BP. Therefore, the differential amplifier circuit subsequently receives a signal corresponding to the photosensitive pixel portions S ₁ to _{S o} at the other input, thereby generating a signal obtained by subtracting the dark current signal component from the signal;
That is, the image information signal VF with dark current compensation is output. On the other hand, at this time, as shown in FIG. 5, the timing control circuit TCC controls the analog gate ASG2 during the period when the solid-state image sensor SP outputs signals corresponding to the photosensitive pixel sections _S1 to _S0 .
By setting the gate control signal Aφ2 to high, the analog gate AG2 is turned on, and therefore, among the outputs of the differential amplifier circuit, the output corresponding to the photosensitive pixel portions S ₁ to _{S o} peaks. It will be added to the detection circuit PD. The peak detection circuit PD has already been reset by the reset signal φ _R from the timing control circuit _TCC as shown in _FIG . By applying the outputs of the differential amplifier circuits corresponding to the photosensitive pixel sections S ₁ to _{S o} through the analog gate AG2, the peak value thereof is detected. Then, when the output of the signals corresponding to the photosensitive pixel sections S ₁ to _{S o} from the solid-state image sensor SP is completed, the timing control circuit
TCC is a gate control signal Aφ as shown in FIG.
By setting analog gate AG ₂ to low and turning off analog gate AG ₂ , peak value detection by the peak detection circuit PD is completed, and after that, a hold signal φ _H is applied to the peak hold circuit PH. At this point, the peak detection output VP of the peak detection circuit PD is held. When the peak value VP is held in the peak hold circuit PH, the comparators CP1 and CP2 compare the held peak value VP with the upper and lower limit reference voltages V _MAX and V _MIN , respectively, and calculate the comparison results. is output as a high or low logic signal. That is, for example, if VP<V _MIN , the output of comparator CP1 becomes low and the output of comparator CP2 becomes high. Therefore, the output of inverter IV becomes high, and the up/down counter UDC goes up.・Set to count mode and set to OR gate
The output of OR1 becomes high, and at this time, the output of exclusive or gate EX also becomes high. Therefore, after the peak hold circuit PH finishes holding the peak detection output VP of the peak detection circuit PD, the timing control circuit TCC
As shown in Figure 5, the up/down counter
When the count pulse CP for UDC is output, the count pulse CP is outputted by the AND gate AN
is applied to the count input of the up-down counter UDC, and the up-down counter UDC counts up by one, thus,
As the outputs Q ₁ to _{Q 3} become low, low, and high, the solid-state image sensor SP is activated as shown in Figure 4.
The designated accumulation time of is switched from the shortest time t ₁ to the next time t ₂ . Therefore, in the next scan, the timing control circuit TCC controls the period t from the fall of the integral clear signal ICG to the low level to the rise of the shift pulse SH according to the time _t2 , thereby performing solid-state imaging. The storage time of the element SP is extended, and the level of the image information signal VF obtained through the differential amplifier circuit is thereby increased. This accumulation time changing operation is repeated until the state of V _MIN ≦VP ≦ V _MAX is obtained, and finally V _MIN ≦ VP ≦ V
When the _MAX state is obtained, the outputs of comparators CP1 and CP2 both become low at this point, and the output of OR gate OR1 becomes low, causing the count pulse CP from the timing control circuit TCC to become low. Granting to the up-down counter UDC is prohibited by the AND gate AN, and therefore, at this point, changes in the accumulation time will be stopped and the accumulation time will be maintained at this proper time. Of course, if the state of VP < V _MIN occurs again while scanning is repeated under the appropriate accumulation time, the accumulation time will be switched to a longer time by the above operation, and vice versa. to
If a state of VP>V _MAX occurs, the comparator CP
The output of comparator CP2 is high, the output of comparator CP2 is low, and the output of inverter IV is low, setting the up-down counter UDC to down count mode, and the count from the timing control circuit TCC.・
By counting down by one using the pulse CP, the storage time can be switched to a shorter time by one step, and through this operation, the storage time of the solid-state image sensor SP is always the appropriate time, that is,
The time is controlled such that an appropriate image signal level of V _MIN ≦VP≦V _MAX can be obtained.

In the above explanation, the shortest initial set time _t1 is the appropriate accumulation time, that is, V
It goes without saying that if the accumulation time is such that _MIN ≦ VP ≦ V _MAX , the accumulation time will be maintained at this time t ₁ , but on the other hand, under this minimum time t ₁ , VP > V _MAX . However, in this case, the output of comparator CP1 is high, the output of comparator CP2 is low, and the output of inverter IV is low, so the output of exclusive OR gate EX is also low, and therefore the accumulation The time is not changed and remains fixed at the minimum time _t1 .

Now, in the process of control as described above, for example, when the accumulation time is controlled to the longest time _t8 ,
Assuming that a state of VP<V _MIN occurs, as mentioned above, such a state is either a state in which the brightness of the incident light to the solid-state image sensor SP is extremely low to the extent that it is unsuitable for use of the device, or the brightness of the incident light is too low. Either the dark current signal level is extremely increased due to an extreme increase in the dark current signal level, and here, it is assumed that the latter is caused and the control described below is performed. That is, in the state where the maximum accumulation time is specified as the maximum time _t8 , the outputs _Q1 to _Q3 of the up-down counter UDC are all high as shown in FIG. When VP<V _MIN , the output of comparator CP1 is low, and the comparator
The output of CP2 goes high and the inverter
As the output of IV becomes high, the output of exclusive-or gate EX becomes low, and the up-down counter of the count pulse CP from the timing control circuit TCC
While the application to UDC is prohibited by the AND gate AN, at this time, the output of the NAND gate NA, which had been high until then, becomes low, so that the transistor Tr, which was previously in a conductive state,
becomes non-conductive and the capacitor C2 begins to be charged through the resistor R12, and the terminal voltage of the capacitor C2 exceeds a predetermined reference voltage set by the resistors R13 and R14, i.e. , after a predetermined time has elapsed, the output of the comparator CP3 changes from low to high at this point, and therefore, the high level output of the comparator CP3 at this time is applied to the up-down counter UDC through the OR gate OR2. This resets the up/down counter UDC and all of its outputs Q ₁ to _{Q 3} become low.
In this way, the storage time of the solid-state image sensor SP is the minimum time t ₁
It will be reset to . Therefore, even when the accumulation time is controlled to the longest time _t8 , VP<V _MIN
As mentioned above, the state in which the solid-state image sensor
If the problem is caused by an extreme increase in the dark current signal level due to an extreme increase in the brightness of the incident light on the SP, resetting the accumulation time will get you out of this state and produce a proper image signal or This means that similar image signals can be obtained.

Note that due to the non-conduction of the transistor Tr due to the low output of the NAND gate NA, the capacitor C2
The next scan is performed before charging starts and the terminal voltage exceeds the above-mentioned predetermined reference voltage, and at this time, if the condition of VP<V _MIN is eliminated, the comparator CP2 Since the output of NAND gate NA becomes low, the output of NAND gate NA becomes high,
Therefore, when the transistor Tr becomes conductive, the capacitor C2 is immediately discharged and the storage time is not reset. Incidentally, in this case, V _MI
If _N ≦ VP ≦ V _MAX , the accumulation time is maintained at t ₈ , and if VP > V _MAX , the output of comparator CP1 becomes high, and the accumulation time is changed from t ₈ . It will be switched to _t7 .

Now, in the embodiment of the present invention explained above, if the storage time of the solid-state image sensor SP is controlled to the maximum time _t8 and still VP<V _MIN , the solid-state image sensor is activated as described above. Although it may be said that the luminance of incident light to the element SP is so low that it is not suitable for use of the device, for the time being, all solid-state image sensors SP
It was assumed that the dark current signal component was extremely increased due to an extreme increase in the incident light brightness, and the accumulation time was reset unconditionally. Of course, it is also possible to actively determine the difference between the two and reset the accumulation time only in the latter case.
To achieve this, for example, the configuration of a brightness level determining circuit as shown in FIG. 6 may be added to the configuration of the circuit system shown in the third diagram. That is, in FIG. 6, LS is the solid-state image sensor SP.
OP2 is a photometric element for measuring the brightness of light that is substantially equivalent to the incident light on the photometric element LS.
R15 and R16 are voltage dividing resistors for setting a predetermined reference voltage, and CP4 is an operational amplifier that together constitute a photometric circuit, and CP4 compares the output of the photometric circuit with the reference voltage to determine whether the photometric circuit output is equal to or higher than the reference voltage. This is a comparator designed to output a high level signal only when Therefore, the comparator CP
By additionally providing the output of 4 to the input of the third NAND gate NA shown in the figure, the NAND gate NA
The output of the comparator CP4 is controlled to the time _t8 with the longest accumulation time, and even when VP<V _MIN , if the incident light intensity is lower than the predetermined level, the output of the comparator CP4 is low. remains high, and on the other hand, when the incident light brightness is above the predetermined level in the same state, the output of the comparator CP4 is high, so its output becomes low, and thus the solid-state image sensor A distinction is made between a state in which the brightness of the light incident on the SP is too low to be suitable for use of the device, and a state in which the dark current signal component is extremely increased due to an extreme increase in the brightness of the light incident on the solid-state image sensor SP. Therefore, the above-mentioned reset of the accumulation time is performed only in the latter case.

Furthermore, in the embodiment described above, the above-mentioned accumulation time to be reset is set to the shortest time _t1 , but it is true that as mentioned above, when an extreme increase in the incident light brightness is expected, this shortest time is set. Although resetting to t ₁ is the most effective method, in some cases, especially depending on the SP characteristics of the solid-state image sensor, the accumulation time to be reset may not be set to the shortest time t ₁ but may be set close to this. A relatively short period of time, e.g. t ₂ and t ₃ in Figure 4
Of course, it is also possible to use a time such as t ₄ or the like, and for this purpose, a part of the configuration of the circuit system shown in the third diagram may be modified as shown in FIG. 7. That is, in Fig. 7, TCC' is the third
This is a timing control circuit similar to the illustrated timing control circuit TCC, but here the third illustrated timing control circuit TCC
In addition to the functions possessed by the comparator CP3,
Power up in response to the high level output of
By outputting a single clear pulse CLR similar to the clear pulse PUC to the up-down counter UDC, the up-down counter UDC is reset, and further after outputting the clear pulse CLR, It has a function of immediately outputting a predetermined number of sub-count pulses CP' similar to the above-mentioned count pulse CP, and the sub-count pulses CP' are connected to an OR gate that receives the output of the AND gate AN. It is applied to the count input of the up-down counter UDC through OR3. Other than the above, the configuration is the same as the configuration shown in the third figure, except that the OR gate OR2 is not required.

According to this configuration, as described above, when the output of the comparator CP3 goes high, in response, the timing control circuit TCC' immediately outputs the clear pulse CLR and the up-down
In addition to resetting the counter UDC, the sub-counter is reset immediately after outputting the clear pulse CLR.
Outputs a predetermined number of pulses CP′, and this
It is applied to the up/down counter UDC through gate OR3. On the other hand, in this state VP<
V _MIN , the output of comparator CP1 is low, and therefore the up-down counter UDC is set to up-count mode;
After the UDC is reset once, the sub-count
In response to the pulse CP', the count is increased by the given number, and thus the accumulation time is reset to the time determined by the given number of the sub-count pulse CP' at this time. Become. That is, if the assigned number of the sub-count pulse CP' is 1, the accumulation time to be reset at this time is _t2 , as is clear from FIG. 4, and the assigned number is 2, 3, . . . As a result, the accumulation time to be reset becomes t ₃ , t ₄ , and so on.

It goes without saying that the brightness level determination circuit shown in FIG. 6 can also be added to the modified example shown in FIG.

As detailed above, according to the present invention, two techniques are used in combination: dark current compensation of the scanning output from the solid-state image sensor and control of the image signal integration time based on the level of the scanning signal. imaging device,
Specifically, when an image is scanned by a solid-state image sensor, the solid-state image sensor outputs a dark current signal generated inside the solid-state image sensor and a scanning signal including the dark current signal. A circuit subtracts the dark current signal from the scanning signal to obtain an imaging signal for the image, and an integration time control circuit controls the image signal integration time of the solid-state image sensor based on the level of the imaging signal. As an imaging device designed for this purpose, there is a concern that the image signal integration time control may progress to an undesirable state, which occurs when, for example, the incident light brightness increases rapidly under a relatively long image signal integration time. By reliably eliminating this problem and maintaining good image signal integration time control even in such a situation, it becomes possible to always obtain an appropriate imaging signal. It is extremely useful.

Incidentally, as a method for determining the appropriateness of the image signal integration time of the solid-state image sensor, in the embodiment, a method was adopted in which it was determined whether the peak level of the image signal was within a predetermined level range. It goes without saying that the present invention is not limited to the embodiments described above, and as already mentioned, it can be used, for example, to determine whether the average level of an image signal is within a predetermined level range. It is also sufficiently effective when employing a method such as quantizing an image signal and determining the state of quantization.

Similarly, regarding a method for detecting a dark current signal generated inside a solid-state image sensor, in the embodiment, a part of the pixel array of the solid-state image sensor is masked (this can be formed by means such as an Al vapor deposition layer). A dark current signal was obtained through the light-shielded dummy pixel section by blocking light with a dummy pixel section, but in addition to this, a dark current generating section having no photosensitizing effect was provided to obtain a dark current signal. Alternatively, instead of these, an empty transfer section may be set in a part of the analog shift register for charge transfer, and the dark current signal may be obtained from the empty transfer section. That is, in the latter case, for example, in the configuration of the _solid -state image sensor SP shown _{in FIG} .
It is sufficient to delete the FB2 etc. and detect the signals obtained by the register sections _CA1 to CA4 etc. as dark current signals.

In addition, in the embodiment, a CR time constant circuit consisting of a resistor R12 and a capacitor C2 is provided in the accumulation time reset circuit, so that even when the accumulation time is the longest, _t8 , VP<
If the state of V _MIN continues for a predetermined time, the accumulation time is reset as the predetermined time elapses, so that, for example, if the above-mentioned condition is resolved within the predetermined time, the accumulation time is reset. However, if such consideration is not required, the output of the NAND gate NA can be directly ORed instead of the output of the comparator CP3.
In the case of the gate OR2 or the modified example shown in the seventh figure, it may be added to the timing control circuit TCC'.

Incidentally, the imaging device of the present invention is disclosed in, for example, Japanese Patent Application No. 52-505 (Japanese Unexamined Patent Publication No. 53-85453), Japanese Patent Application No. 52-506 (Japanese Unexamined Patent Application No. 53-85454), and Application No. 52-117235 (Unexamined Patent Publication No. 51556-1973)
Distance detection devices such as those proposed in, etc., or the same as those proposed in Japanese Patent Application No. 53-38566
130825) or the distance detection device disclosed in the aforementioned US Pat. No. 4,004,852.

The peak detection circuit PD and the peak hold circuit PH in the embodiments are, for example, disclosed in Japanese Patent Application No. 53-38566 (Japanese Unexamined Patent Publication No. 1983-1989) filed by the applicant.
130825), the configuration of a peak detection circuit and a peak holding circuit (sample and hold circuit) can be adopted.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the relationship between the incident light brightness to the solid-state image sensor, its signal integration time, and image signal output, and Figure 2 is a diagram showing how the dark current signal level fluctuates and the resulting output after dark current compensation. 3 is a circuit diagram showing the configuration of a circuit system according to an embodiment of the present invention, and FIG. 4 is an up/down diagram for setting the accumulation time (signal integration time) in the embodiment shown in the third embodiment.・A diagram showing the relationship between the output of the counter and the accumulation time specified by it.
A timing chart showing the operation of the illustrated embodiment, FIG. 6 is a partial circuit diagram showing an example of a brightness level determination circuit that can be added as an improvement to the third illustrated embodiment, and FIG. 7 is a partial circuit diagram for the third illustrated embodiment. FIG. 7 is a partial circuit diagram showing a circuit configuration of a main part of a modified example, particularly related to the modification. SP...solid-state image sensor, _D1 , _D2 ...dummy pixel section for dark current detection, MS...mask, _S1 to S _o ...photosensitive pixel section, AG1, R4, C1... components of dark current detection and holding circuit, OP1, R5-R8...Components of differential circuit for dark current compensation, PD, PH, R9-R1
1, CP1, CP2... Components of a circuit for determining the suitability of signal integration time, UDC... Up-down counter as a circuit for setting integration time, TCC; TCC'... Timing control circuit as an integration time control circuit, NA, Tr, C2, R12-R14, CP
3; TCC', OR3... Components of the integration time reset circuit, LS, OP2, R15, R16, CP4... Components of the brightness level determination circuit.

Claims (1)

[Claims] 1. When scanning an image with a solid-state image sensor, the solid-state image sensor outputs a dark current signal generated inside the solid-state image sensor and a scanning signal including the dark current signal, and A circuit subtracts the dark current signal from the scanning signal to obtain an imaging signal for the image, and an integration time control circuit controls the image signal integration time of the solid-state image sensor based on the level of the imaging signal. In the image pickup device, the level of the image pickup signal from the differential circuit is adjusted to a predetermined level while the image signal integration time of the solid-state image pickup device is adjusted to the longest controllable integration time by the integration time control circuit. further comprising a reset circuit for resetting the image signal integration time of the solid-state imaging device to a shorter integration time, which is to be set by the integration time control circuit, by detecting that the image signal integration time of the solid-state image sensor has fallen below the level of the integration time control circuit. An imaging device characterized by: 2 The level of the imaging signal from the differential circuit is adjusted to the maximum integration time when the image signal integration time of the solid-state imaging device is controllable by the integration time control circuit in the reset circuit. When the state of being below a predetermined level continues for a predetermined time, the image signal integration time of the solid-state image sensor to be set by the integration time control circuit is reset to a shorter integration time as the predetermined time elapses. Mr,
An imaging device according to claim 1. 3 When the level of the imaging signal from the differential circuit is adjusted to the maximum integration time when the image signal integration time of the solid-state imaging device is controlled by the integration time control circuit, the reset circuit is adjusted to the longest integration time that can be controlled. an integration time that is shorter than the image signal integration time of the solid-state image sensor to be set by the integration time control circuit when the illuminance of the image is below a predetermined level and at this time is above a predetermined level; An imaging device according to claim 1 or 2, configured to be reset to .