JP2589124B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device that performs automatic exposure control on a solid-state imaging device such as a CCD.

(B) Conventional technology Exposure control of an image pickup apparatus, for example, a television camera, usually controls a mechanical aperture mechanism in a lens barrel by an iris control circuit, which causes a cost increase.

Therefore, conventionally, in a solid-state imaging device such as a television camera using a solid-state imaging device, an attempt has been made to electronically perform automatic exposure control (auto iris) by utilizing the driving principle of the solid-state imaging device.

For example, in Japanese Utility Model Application No. 61-139527, in a frame transfer type CCD solid-state imaging device, an image which has been photoelectrically converted and stored in a light receiving area of this device during a photoelectric conversion period for each vertical blanking period. Exposure control means is provided for transferring and discharging charges in a direction opposite to the transfer direction for reading out image signals, and accumulating image charges photoelectrically converted only in the remaining photoelectric conversion period (effective photoelectric conversion period) for one screen. Things have been suggested. Therefore, according to such an exposure control means, an optimum exposure state can be obtained by changing the reverse transfer timing of the electric charge according to the brightness of the subject.

FIG. 6 shows a basic configuration of a solid-state imaging device having such an auto iris function.

In the figure, (S) is a frame transfer type CCD solid-state imaging device comprising a light receiving area (1), a storage area (2), and a horizontal register (3).
After the image charge obtained by photoelectric conversion in one screen unit (field unit) is temporarily transferred and stored in the storage area (2) every vertical blanking period, the horizontal register (scanning line unit) is used in one scanning line unit every horizontal blanking period. 3) to output as an image signal. Then, the image signal which is continuous in units of fields is subjected to signal processing such as sample hold and amplification in a signal processing circuit (4), and is output to an external device as a video signal.

The CCD solid-state imaging device (S) is driven by a clock, and a first transfer clock generation circuit (8) or a reverse transfer clock generation circuit (9) is provided in the light receiving area (1) by a clock selection circuit (15). 4) obtained by selecting
The phase clocks φ _{P1 to} φ _P4 are supplied, the storage area (2) is supplied with the four-phase clocks φ _{S1 to} φ _S4 from the second transfer clock generation circuit (10), and the horizontal register (3) is further supplied with horizontal signals. Two-phase clock φ from transfer clock generation circuit (11)
_H1 and _φH2 are supplied.

Note that these clock generation circuits (8), (9), (1)
0) and (11) are generated based on the basic clock from the same oscillation circuit (5), and the horizontal blanking pulse generation circuit (6) similarly generates a pulse indicating the horizontal blanking period based on the basic clock. Based on the horizontal blanking pulse, the vertical blanking pulse generation circuit (7) creates a pulse indicating a vertical blanking period. The vertical blanking pulse is input to a first transfer clock generation circuit (8), which determines the generation timing of the first transfer clock transmitted in a specific period for each vertical blanking. Is input to the reverse transfer clock generation circuit (9), which determines the generation timing of the reverse transfer clock to be transmitted in the horizontal period for each horizontal blanking.

(14) a reverse transfer clock supply timing generating means, which selects a clock of the reverse transfer clock generation circuit (9) by a clock selection circuit (15) and selects the light receiving area (1)
Is determined in which horizontal blanking period the reverse transfer driving is performed. The timing of the reverse transfer clock supply timing generation means (14) is determined based on the horizontal blanking pulse of the horizontal blanking pulse generation circuit (6) and the vertical blanking pulse of the vertical blanking pulse generation circuit (7). Further, a comparison circuit (13) compares an integrated value from an integration circuit (12) obtained by integrating a video signal (luminance signal) from the signal processing circuit (4) for each field.
Is performed in accordance with the feedback signal compared with the predetermined reference value, that is, the timing is delayed as the value of the video signal (luminance signal) increases (brighter). Note that this comparison processing can also be performed directly on the output (image signal) from the CCD solid-state imaging device (S) as image information.

FIG. 7 shows a conventional configuration of such a comparison circuit (13). The circuit shown in the figure compares an integrated value from an RC integrating circuit (12) composed of a resistor R1 and a capacitor C1 with a reference voltage Vr of a set resistor R2, and includes a comparator COM for this purpose.
The output of the comparator COM is 2 at two different timings t1 and t2 at the middle position of the vertical blanking period.
The flip-flops FF1 and FF2 are set.

Therefore, a total of 2 from these flip-flops FF1 and FF2
The bit data becomes the above-mentioned feedback signal,
It is input to the reverse transfer clock supply timing generation means (14), and determines whether the reverse transfer clock supply timing is advanced or delayed. The transistor Q has an integral capacitance C1 for each field, that is, for each vertical blanking period.
Is provided to discharge the electric current.

According to such a conventional comparison circuit (13), when there is a bright spot W at the bottom of the screen as shown in FIG.
As shown in FIG. 9, the output of the video signal Y (t) increases in the latter half position of the vertical blanking period V, and the integrated value ∫
A curve (a) of Y (t) dt rises. When there is a bright spot W at the top of the screen as shown in FIG. 10, the output of the video signal Y (t) becomes large in the first half position of the vertical blanking period V as shown in FIG. The curve (b) of the integral value ∫Y (t) dt rises.

Accordingly, as shown in FIG. 12 in which these integral value curves are superimposed, the history of the integral value ΔY (t) dt differs because the spot W position is different even though the brightness on the entire screen is the same.
As a result, the output value from the comparator COM at the timings t1 and t2 differs depending on both cases.
There was a concern that the feedback signals set in FF1 and FF2 would have opposite results.

(C) Problems to be Solved by the Invention As described above, the present invention includes a comparison circuit that obtains a feedback signal corresponding to the brightness of the entire screen without being affected by a difference in spot position on the screen. Is provided.

(D) Means for Solving the Problems The first solid-state imaging device of the present invention has the following configuration.

(1) A solid-state imaging device that obtains continuous image information for each screen by photoelectrically converting a received image at predetermined time intervals. (2) An integration for integrating image information obtained by the solid-state imaging device for each screen. (3) a comparison circuit for comparing a signal value at the end of each screen of the integrated signal obtained from the integration circuit with a reference value set corresponding to an appropriate exposure amount of the solid-state imaging device; Automatic exposure control means for variably setting an effective photoelectric conversion period of the solid-state imaging device for each predetermined time based on a comparison result of the comparison circuit.

Further, a second solid-state imaging device according to the present invention has the following configuration.

(1) A solid-state imaging device that obtains continuous image information for each screen by photoelectrically converting a received image at predetermined time intervals. (2) An integration for integrating image information obtained by the solid-state imaging device for each screen. (3) a first reference value set in correspondence with a signal value at the end of each screen of the integrated signal obtained from the integration circuit and an upper limit of an appropriate exposure amount of the solid-state imaging device, and a lower limit thereof By comparing with the second reference value set corresponding to
An exposure limiting signal is output when the value of the integration signal is greater than the first reference value, and an exposure fixing signal is output when the value is smaller than the first reference value and larger than the second reference value, and is smaller than the second reference value. And (4) controlling the effective photoelectric conversion period of the solid-state imaging device at predetermined time intervals based on the result of the comparison, and receiving the exposure limit signal. When the effective photoelectric conversion period at this time is shortened by a specific time, when the exposure fixed signal is received, the effective photoelectric conversion period at this time is fixed,
Automatic exposure control means for extending the effective photoelectric conversion period at this time for a specific time when the exposure promotion signal is received.

(E) Function According to the solid-state imaging device of the present invention, the comparison circuit sets the reference value set in accordance with the signal value of the integrated signal obtained by integrating the video signal at the final time point for each screen and the appropriate exposure amount of the solid-state imaging device. Since the value is compared with the value, exposure control can be automatically performed based on a feedback signal according to an integration signal corresponding to the brightness of the entire screen.

(F) Embodiment The solid-state imaging device of the present invention has the same basic configuration as that of the solid-state imaging device of FIG. 6, for example. (1
The specific configuration of 3).

FIG. 1 shows a comparison circuit (1) used in the solid-state imaging device of the present invention.
An example of 3) is shown below. Two comparators COM to which the integrated value ∫Y (t) dt from the RC integrator (12) having the discharging transistor Q are input to the comparator (13) of FIG.
1, COM2 is provided. The other input of the first comparator COM1 is connected to a voltage dividing point of a resistor R2 capable of variably setting a first reference voltage Vr1 corresponding to an upper limit value of an appropriate exposure, and the other input of the second comparator COM2. Is connected to a voltage dividing point of a resistor R3 which can be variably set to a second reference voltage Vr2 (smaller than Vr1) corresponding to a lower limit value of an appropriate exposure. Then, the result of the magnitude comparison by the comparators COM1 and COM2 is stored in the flip-flops FF1 ^* and FF2 ^* at the final timing te of the field corresponding to the vertical blanking period V.

Therefore, both flip-flops FF1 ^* and FF2 ^* have the first
At the final timing te of the vertical blanking period V where the histories (a) and (b) of the two integrated values in FIG. 2 finally match, as shown in FIG. Reference values Vr1, Vr
The result of the magnitude comparison with 2 is stored and output. The outputs of the flip-flops FF1 ^* and FF2 ^* are converted to 2-bit data [x
For example, [0,0] is ∫Y (t) dt ≧ Vr1, [1,0] is Vr1> ∫Y (t) dt ≧ Vr2, [1,1] ] Represents Vr2> ∫Y (t) dt.

In the solid-state imaging device of the present invention, these three types of 2
Bit data [0,0], [1,0] and [1,1] are used as "exposure limit signal", "exposure fixed signal" and "exposure promotion signal", respectively, and work as automatic exposure control means. Reverse transfer clock supply timing generation means (14) in FIG.
Controls the expansion and contraction of the effective photoelectric conversion period for each frame period in the light receiving area (1) of the CCD solid-state imaging device (S) based on these signals.

Such a reverse transfer clock supply timing generation means (1
As shown in FIG. 3, as shown in FIG. 3, a decoder (141) for decoding 2-bit data, a 5-bit up / down counter (142) for counting 0 to 31, and 0 to 256 are placed in high-order steps in units of eight. It comprises a step counter (143) capable of counting 5 bits 32 times, and a comparator (144) for detecting coincidence between the output values of these counters (142) and (143).

Therefore, according to the circuit (14), the comparison circuit (1
3) When the input signal [x1, x2] from “Exposure limit signal”
The decoder (141) inputs the up signal U to the up / down counter (142), and this value counts up by one. Conversely, in the case of the “exposure promotion signal”, the decoder (14
In 1), the down signal D is input to the up / down counter (142), and this value is counted down by one. further,
At the time of the "exposure fixed signal", the signal output is not performed, and the value of the up / down counter (142) is continuously held.

In this way, the up-down counter (142) stores the step number (increases or decreases according to the exposure amount) when the photoelectric conversion period T in the vertical blanking period V is divided into 32 steps. On the other hand, while the step counter (143) is reset by the vertical blanking pulse Pv and the horizontal blanking pulse Ph is counted from 0 to 31 every 8 over the subsequent photoelectric conversion period T, this value is maintained by the up-down counter. When the set value of (142) is reached, the comparator (144) sends the reverse transfer clock supply timing pulse Pb to the clock selection circuit (15) at this timing.

Therefore, as shown in FIG. 4, the clock selection circuit (15) supplies the reverse transfer clock φb to the storage area (2) of the CCD solid-state imaging device (S) only when the above-mentioned timing pulse Pb is generated. And the period from the end of the reverse transfer driving of the storage area (2) to the start of the forward transfer driving by the first transfer clock φf (referred to as an effective photoelectric conversion period) Te, which is the charge actually used as the image charge. Photoelectric conversion is performed.

If the amount of photoelectric conversion in the effective photoelectric conversion period Te is too large and the exposure is excessive as shown by the curve (c) in FIG. 2, the supply timing of the reverse transfer clock φb in FIG. [T / 32] is delayed by one step until the proper exposure is achieved as shown by the curve (e) in FIG.
/ 1 vertical blanking period] and the effective photoelectric conversion period Te
Is continued at a constant speed. Conversely, if the exposure is insufficient as shown by the curve (c) in FIG. 2, the reverse transfer clock φ in FIG.
The supply timing of b is one step in the direction of OPEN [T / 3
2] It will be quicker and [1 step /
1 vertical blanking period], the effective photoelectric conversion period Te
At a constant velocity. Then, the curve (e) in FIG.
As shown in FIG. 4, the supply timing of the reverse transfer clock shown in FIG. 4 does not move and the effective photoelectric conversion period Te is fixed as long as the range is within this range.

The reverse transfer clock supply timing generating means (14) for performing the automatic exposure control as described above not only expands / contracts the effective photoelectric conversion period Te, but also fixes this period Te in a proper exposure range. It is possible to eliminate the flicker of the playback screen when the shortening and the shortening are performed alternately. Further, since the expansion / contraction operation is sequentially changed at predetermined steps with respect to the target, it is possible to suppress the deterioration of the image quality of the reproduction screen due to a rapid exposure change. Also, the step amount of the exposure change can be freely changed by independently setting the step widths for both the extension and the shortening of the effective photoelectric conversion period Te.

In the embodiment of the device of the present invention described in detail above, as shown in FIG.
Although the reference voltages Vr1 and Vr2 of both comparators COM1 and COM2 can be individually variably set, as shown in FIG. 5, only a single reference value Vro can be variably set to improve operability. Circuit devices can also be used. That is, the circuit shown in the figure is proportional to the exposure amount obtained by dividing the power supply voltage by the transistor Qr and the series connection of the resistors R4, R5 and R6 in accordance with the integrated value ∫Y (t) dt of the video signal. It compares the high and low two-level voltage values Y1 and Y2 with a single reference value Vro, and three kinds of signals "exposure limit signal", "exposure fixed signal" and "exposure" as in the circuit of FIG. The "promotion signal" is output.

In any of the comparison circuits shown in FIGS. 1 and 5, when the circuit is also formed as an IC, the range of the appropriate exposure amount can be easily changed only by changing the value of the external resistor. So
The merit is greater than that of the conventional circuit of FIG. 7 in which the determination timings t1 and t2 cannot be changed.

Further, in the embodiment of the present invention described in detail above, CC
D Although the example in which the unnecessary charge is eliminated by the reverse transfer driving of the light receiving area (1) of the solid-state imaging device is described above, the invention is not limited to this. It may be. Therefore, in the present invention, of course, besides the frame transfer type CCD solid-state image sensor, the interline type CCD solid-state image sensor and MOS
It is possible to employ a solid-state imaging device of the type.

(G) Effects of the Invention As is clear from the above description, the solid-state imaging device of the present invention has a comparison circuit for determining whether exposure is excessive or insufficient, and a signal value at the end of each screen of an integrated signal obtained by integrating a video signal. And a reference value set corresponding to an appropriate exposure amount of the solid-state imaging device, so that a feedback signal corresponding to the brightness of the entire screen can be obtained from this comparison circuit. Therefore, according to the present invention, stable auto iris control can be performed without being affected by differences in spot positions on the screen.

[Brief description of the drawings]

FIGS. 1 and 5 are configuration diagrams of different specific examples of the comparison circuit used in the solid-state imaging device according to the present invention, and FIGS.
Fig. 11, Fig. 11 and Fig. 12 are signal diagrams on the time axis, respectively.
FIG. 3 is a circuit configuration diagram of a reverse transfer clock supply timing generating means used in the device of the present invention, FIG. 6 is a block diagram showing a basic configuration of the solid-state imaging device, FIG. 7 is a circuit diagram showing a comparison circuit of the conventional device, 8 and 10 are schematic diagrams of the imaging screen. (1) ... light receiving area, (2) ... accumulation area, (3) ... horizontal register, (4) ... signal processing circuit, (8), (9), (10), (11) ... Clock generation circuit, (12) integration circuit, (13) comparison circuit, (14) reverse transfer clock supply timing generation means, (15) clock selection circuit.

Claims (1)

(57) [Claims] 1. A solid-state imaging device that obtains continuous image information for each screen by photoelectrically converting a received image at predetermined time intervals, and an integration circuit that integrates image information obtained by the solid-state imaging device for each screen. The signal value of the integral signal obtained from the integration circuit at the final point of each screen is compared with the first and second reference values set corresponding to the upper and lower limits of the appropriate exposure amount of the solid-state imaging device. A pair of comparator circuits, each of which outputs an exposure limit signal in response to a comparison result of the comparator circuit when the value of the integration signal is greater than a first reference value;
A decode circuit that outputs an exposure fixing signal when the value is smaller than the second reference value and outputs an exposure promotion signal when the value is smaller than the second reference value; and an effective photoelectric conversion period of the solid-state imaging device at predetermined time intervals. Is controlled in a plurality of steps, the effective photoelectric conversion period is shortened by one step when the exposure limit signal is received, and the effective photoelectric conversion period is fixed when the exposure fixed signal is received. A solid-state imaging device comprising: exposure control means for extending an effective photoelectric conversion period by one step when a signal is received.