JP3121033B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging apparatus for controlling an integration time and a signal reading control based on a signal from a photoelectric conversion element.

[0002]

2. Description of the Related Art When in-focus detection is performed based on a signal from a photoelectric conversion element, appropriate integration control and readout control of the photoelectric conversion element are required. Many proposals have been made so far. For example, a method of arranging a photoelectric conversion element dedicated for integration control near a photoelectric conversion element for signal detection, and controlling the integration time of the photoelectric conversion element for signal detection based on the output of the photoelectric conversion element dedicated for integration control (Japanese Patent Application No. 2006-122857). Showa 57-64711
And a method of detecting the peak value of the output of the photoelectric conversion element itself and controlling the integration time of the photoelectric conversion element. Further, a method of detecting the MAX and MIN values of the photoelectric conversion element and controlling the integration time of the photoelectric conversion element based on the contrast (MAX-MIN) value (Japanese Patent Application No. 1-222).
No. 583).

[0003]

The current storage type photoelectric conversion element has a small dynamic range, and the following disadvantages occur when the integration time is controlled by targeting a general subject. FIGS. 22 and 23 show one of the photoelectric conversion elements.
The output of the line is shown with the horizontal axis as a read pixel, and (A)
Shows a signal state in an ideal state, (B) shows a signal state when integration time control is performed by peak value detection, and (C) shows a signal state when integration time control is performed by average value detection. When the integration time is controlled with the average value of the entire photoelectric conversion element, there is a bright main subject in the dark [(A) of FIG. 22].
And the originally required signal is saturated [(C) in FIG. 22]
Correct distance measurement is not possible.

When the integration time is controlled by the peak value of the photoelectric conversion element, if there is a bright spot-like object other than the main subject [FIG. 23 (A)], the dynamic range of the main subject is in a spot-like portion. As a result, the distance is lessened [FIG. 23 (B)]. Also, in the case where the contrast difference (MAX-MIN) of the photoelectric conversion element is used as a reference, the same problem as that of performing the integration time control at the peak value occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem of the conventional integration time control method for a photoelectric conversion element. In order to perform focus detection, appropriate integration time control and signal readout are performed under any conditions. It is an object of the present invention to provide an imaging device that performs control.

[0006]

An image pickup apparatus according to the present invention for solving the above problems comprises a photoelectric conversion element arranged in an array for converting a light quantity distribution into an electric signal, and a light beam from a subject. An imaging optical system that forms an image on the photoelectric conversion element, a peak detection circuit that detects a pixel signal having the largest amount of light from each pixel signal of the photoelectric conversion element, and an average of all pixel signals of the photoelectric conversion element In an image pickup apparatus having at least an average value detection circuit for detecting a value, an integration time of signals of the peak detection circuit and the average value detection circuit
From the photoelectric conversion element based on the
Interpolation processing of the two detected image signals for focus detection
It is characterized by forming a signal to be used. This
The structure of will be explained based on the concept diagram of Figure 1. An imaging apparatus for focus detection according to the present invention includes an imaging optical system 1 that guides a light beam of a subject to a photoelectric conversion element 2 and a signal obtained by photoelectrically converting a light amount distribution from the imaging optical system 1 into a distribution of electric signals. To the peak detection circuit 3 and the average value detection circuit 4, and the photoelectric conversion element 2 from which a part or all of the signal photoelectrically converted by the timing signal from the focus detection circuit 6 is read out
A peak detection circuit 3 that detects a peak value of a part or the whole of the photoelectric conversion element 2 based on a start signal from the focus detection circuit 6 and outputs a peak detection signal to the focus detection circuit 6; An average value detection circuit 4 that detects an average value of a part or the entirety of the photoelectric conversion element 2 based on a start signal from the microcomputer and outputs an average value detection signal to a focus detection circuit 6; a peak detection circuit 3 and an average value detection circuit 4 A part or the whole of the photoelectric conversion signal of the photoelectric conversion element 2 is read out based on the detection signal from the CPU 2 to perform focus detection, and information (position, focal length, etc.) of the imaging optical system 1 is input from the drive circuit 5 and the imaging optical A focus detection circuit 6 for outputting the drive amount of the system 1 to the drive circuit 5; and reading the photographic optical system information from the photographic optical system 1 and outputting the information to the focus detection circuit 6 according to the drive amount from the focus detection circuit 6. Drive the photographing optical system 1 Composed of the drive circuit 5 to.

[0007] In the imaging apparatus for focus detection configured as described above, after the peak value of the photoelectric conversion signal is detected by the peak detection circuit 3, part or all of the photoelectric conversion element 2 is read out. The next readout timing is determined according to the average value output at the time of peak value detection, read out again, and the signal used for focus detection is formed by interpolation processing based on the outputs of the two photoelectric conversion elements. Do.

[0008]

Next, an embodiment will be described. FIG. 2 is a circuit diagram showing an embodiment in which the present invention is applied to a focus detection apparatus using an AF line sensor. The photoelectric conversion device in this embodiment is a static induction transistor (Static Ind.
Auction Transistor (hereinafter abbreviated as SIT) type solid-state imaging device. This SIT-type solid-state imaging device has an SI
T F _i and (i = 1~n), and the transistor E _{i (i} = _1~n) Reset SIT F _i with RS _in signal, S
And IT F transistor D _i charges generated at controlled by SF _in signal _{i (i} = _1~n) and accumulates via the charge storage capacitor C _{i (i} = _1~n), the charge storage capacitor C transistors B _i (i amplifying output _i of the charge
= 1 to n) and a transistor A _{i (i} = 1~n) for selectively controlling the transistors B _i, the transistor G _{i (i} = 1~n for amplifying output charge of the charge storage capacitor C _i at the time of addition readout ), A transistor H _i (i = 1 to n) for selectively controlling an area in which addition and reading are performed, and a transistor I _i (i = 1 to n) for resetting the charge of the charge storage capacitor C _i by the R _in signal. , A decoder DEC for controlling the addition output line reset transistor L and the read control transistors A _i , _Hi with a DC _in signal
, A current-voltage conversion resistor R1 and an output line
A transistor K to be reset by V, an output OS obtained by current-voltage conversion by R1, and V _ref1 corresponding to a peak value level.
And outputs as an OSP signal
1 and a transistor J for controlling the timing of addition and reading by the AV _in signal, an operational amplifier OP2 for converting the addition current to the addition current and a voltage, and comparing the output of the operation amplifier OP2 with a value obtained by dividing the addition current reference voltage _Vref2. MOS1,
Comparators OP3 and O outputting to MOS2 and MOS3
P4, OP5 and resistors R2, R3, R4 for dividing the added current reference voltage _Vref2 . The addition current reference voltage V _ref2 can be varied according to the number of pixels to be added.
Is set not to turn on first. Here,
The addition output, that is, a predetermined weight
The added value is the average value.

FIG. 3 shows the photoelectric conversion characteristics of the SIT. SI
The T output linearly changes to a saturation level with respect to the light amount as shown in the figure. FIG. 4 shows the output OSP of the peak value detection comparator OP1 and the addition output detection comparator OP.
Output MOS1, MOS2, MOS of 3, OP4, OP5
3 shows a relationship between the number 3 and the flag FGi (i = 0 to 3) indicating each state.

FIG. 5 shows the flow from the start to the end of integration (S
UB1). Following the start of step F1000,
In step F1001, a focus area is designated by switching between a spot area and a wide area [signal reading transistors A _i , H by decoder DEC.
_i (i = j to m) ON]. Next, step F1
At 002, the pixel and the charge storage capacitor C _i (i
= 1 to n), the flag FGi (i = 0 to 3), and the limiter timer are reset. Next, integration is performed in step F1003,
The limiter timer is started, and Step F1004
To determine the limiter time (t <T _L ), and t <T _L
If so, the process proceeds to step F1005, where the peak value detection signal OS
P is determined, and if OSP is not 1, step F10
Return to 04. If OSP = 1, S in step F1006
Transistor D to control the integration time constant at F _in signal
_i (i = 1 to n) is turned off, and then step F100
At step 7, the pixel signal is read from the OS signal by the shift signal of the decoder DEC (taken into DD1).

Next, in step F1009, the transistors D _i (i = 1 to n) are turned on again, and the decoder DE is turned on.
The transistors A _i , H _i (i = jｊ
m) is turned ON to determine the comparator output MOS2 for determining the addition output (MOS2 = H) Step F10
Enter 10. If output MOS2 = H, step F10
In step 21, the comparator output MOS1 for determining the addition output is determined (MOS1 = H). If MOS1 = H, only the flag FG0 is set to 1 in step F1022 (FG0 =
1). If the output MOS1 is not H in step F1021, the process proceeds to step F1023, and only the flag FG1 is set to 1 (FG1 = 1).

In step F1010, the output MOS2 =
If not H, the flow moves to step F1030 to judge the addition output judgment comparator output MOS3 (MOS3 = H).
Is performed, and if the output MOS3 is not at H, step F103
When 1 is set, only the flag FG3 is set to 1 (FG3 = 1), and the output M
If OS3 = H, only the flag FG2 is set to 1 in step F1032 (FG2 = 1). Next, step F103
At 3, the limiter time is determined (t <T _L ), and t <T _L
If so, in step F1034, check FG2 again (F
G2 = 1), and if FG2 = 1, step F1
Return to 033. If FG2 = 1, step F1035
Then, the comparator output MOS2 for determining the addition output is determined again (MOS2 = H). If MOS2 = H, the process returns to step F1033.

When MOS2 = H in step F1035,
When t < _TL is not satisfied in step F1033 and when step F
When t <T _{L in} 1004, the process proceeds to step F1036,
Transistor D that controls integration time constant by SF _in signal
_i (i = 1 to n) is turned off. Next, step F10
At 37, the operation goes through the operation of reading from the OS signal by the shift signal of the pixel signal decoder DEC (take in the DD2), and after the operations of steps F1022 and F1023, the operation enters step F1040 and ends.

FIG. 6 shows how the in-focus point is detected. The primary imaging plane is transmitted by the condenser lens CL, and the taking T
Images are formed as A and B images on the sensor surface S via two sets of separator lenses SL that look at the pupil divided into two parts L. The interval between the A and B2 images changes according to the focus state.

FIG. 7 is an explanatory diagram relating to the detection of the interval between two images. FIG. 7C is a diagram showing the relationship between the pixel and the sensor output, in which the A and B images are superimposed, and in the focus detection calculation, the absolute value of the difference between the A and B images (shown by oblique lines) is correlated. Value. Figure 7 (A) is 2 to obtain the second image distance from the correlation calculation value
An image interval detection operation, that is, an operation of calculating a true image interval from a point where the correlation operation value is MIN and two points on both sides is shown. FIG. 7B shows a correlation operation similar to that of FIG. 7A, except that the interval between two images is twice as large as that of FIG.

FIG. 8 shows comparator outputs OSP and MOS.
1, MOS2, MOS3 and flag FG _i (i = 0 to 3)
FIG. 6 is a diagram showing a relationship between the read timing and the read timing. In the figure, indicates the output indicating the peak value in the pixel, and indicates the added value in each state. When FG0 = 1 (in the case of,), the signal is read at the time point a when the peak value reaches the OSP level. For additional value also becomes the same as the substantially peak value (the which are beyond the MOS1) in some cases there is no contrast, 2 image interval detection <br/> also in combination of two images interval operation shown in FIG. 7 (B) to detect. When FG1 = 1 (in the case of,), the signal is read out at the time point a when the peak value reaches the OSP level, and the signal is read between the two images shown in FIG.
An interval between two images is detected by an interval detection calculation. When FG2 = 1 (in the case of,), the time point a when the peak value reaches the OSP level and the time point b when the addition output reaches the level of the MOS2
Read the signal with. Signal DD read at time points a and b
1 and DD2, the signal is subjected to interpolation processing, and FIG.
2 image interval 2 image interval detection operation shown to detect. FG
In the case of 3 = 1 (in the case of,), the signal is read at the time point a when the peak value reaches the OSP level and at the time point c when the limiter time is reached. Signal DD read at time points a and c
1 and DD2, the signal is subjected to interpolation processing, and FIG.
Detecting the image-to-image gap at 2 picture interval detection operation shown in. F
When Gi = 0 (i = 0 to 3), the signal is read at the time point d when the limiter time is reached. Starring shown in FIG. 7 (B)
The interval between two images is detected by using the calculation in combination.

FIG. 9 shows an interpolation process for the A image when FG2 = 1 and FG3 = 1. The data of DD1 and DD2 are shown in FIGS. Figure 3 shows SIT output
Since it changes linearly as shown in FIG.
Data at the time of peak detection and average value detection
The data is converted by linear interpolation from the data and two integration times as shown in FIG.

FIG. 10 shows a flow up to the detection of the focal point of the camera. From the start step (F1100), the focus area is determined to be wide or spot (F1101), and then in step F1102, the first release determination (1st = ON) is performed. F11 if 1st = OFF
01, if 1st = ON, SUB1 shown in FIG.
(F1103). Next, step F1
At 104, the in-focus point detection calculation shown in FIG.
In 1105, the photographing optical system is driven to the in-focus position, and a stop step (F1105) is performed.

In this embodiment, the peak value and the average value, that is,
The weighted sum can be detected by the signal detection pixel, and the peak
By reading and interpolating the image signal when the value and the average value are detected, a signal having a high S / N can be obtained, and high focusing accuracy can be obtained. Further, by detecting the peak value and the average value with one solid-state imaging device, downsizing and cost reduction can be realized.

In this embodiment, the photoelectric conversion device is S
An example using an IT-type solid-state imaging device is shown.
(Amplified MOS Intelligent Imager), CMD (Char
A non-destructive readout imaging device such as a (ge Modulation Device) type solid-state imaging device may be used. A method other than this embodiment may be used in the focusing operation.

Next, a description will be given of a second embodiment in which the present invention is applied to an in-focus point detecting apparatus based on the contrast method. In the contrast method, as shown in FIG. 11, a signal in a certain frequency band is extracted from the output of the sensor 11 through a band filter 12, and a signal obtained by integrating the signal in an integration circuit 13 is used.

FIG. 12 is a diagram showing the relationship between the position of the focus lens and the contrast signal.
As for P, the contrast signal is maximized, and the contrast signal before and after that is monotonically increased or decreased with respect to the lens position. By obtaining a contrast value while moving the lens using this relationship, the position of the lens to be focused can be determined.

The purpose of the present embodiment is to use the average and peak photometric outputs from the sensor when the in-focus point is detected using the contrast method, and to effectively use the dynamic range of the signal processing system. FIG. 13 shows the configuration of the focus detection circuit 6 shown in FIG. The focus detection circuit includes a determination circuit 21 composed of a comparator for binarizing a signal from the photoelectric conversion device, a delay line 22, and a bandpass filter 23 for extracting a specific frequency band from the signal output from the delay line 22. , Focus area control signal 24 and judgment circuit
A gate circuit 25 that gates the output of the band-pass filter according to the condition 21;
D conversion circuit 26 and addition circuit 27 for adding A / D conversion output
It is composed of

The operation sequence relating to integration control and signal reading in this embodiment is the same as that in the first embodiment, and is as shown in FIGS.

Next, a timing chart of the detection unit is shown in FIG.
And FIG. FIG. 14 shows signal components at the time of peak detection, and FIG. 15 shows signal components at the time of average value detection. Fig. 14
Then, with respect to the sensor output shown in FIG.
The signal region to be extracted is determined by the comparator output shown in FIG. In FIG. 15, the signal area is determined by the sensor output shown in (A) and the comparator output shown in (B) for determining the unsaturated output level b of the sensor output. There is no region where the comparator output of FIG. 14B and the comparator output of FIG. 15B cross each other.

A predetermined frequency component of the signal whose area is determined by the comparator output is extracted by the bandpass filter 23, and digital addition is performed according to the characteristic (response delay characteristic) of the bandpass filter 23 after the A / D conversion. The addition value of the bandpass filter 23 at the time of reading shown in FIG. 14 is added to the addition value of the bandpass filter 23 at the time of reading shown in FIG. I do. For example, the added value at the time of peak detection is weighted by b / a, and added to the added value at the time of detecting the average value to obtain a contrast signal.

FIG. 16 is a circuit diagram of an AF line sensor used in the second embodiment. The AF line sensor has a part of the functions of the photoelectric conversion device 2, the peak detection circuit 3, and the average value detection circuit 4 shown in FIG. In FIG. 16, S1 to Sn
Is a pixel SIT constituting a line sensor, and each SIT
Have P-MOS transistors Q _{P1 to} Q _Pn for resetting the gate of the SIT.
The source of _P1 ~Q _Pn are connected, respectively. The drain of the SIT is connected to a power supply (not shown). SI
The source of T is connected to the source lines 31-1 to 31-n, and each source line is connected to the pixel signal readout circuit 32 and the photometry circuit 33. The gate of Q _P1 to Q _Pn is connected to the pulse phi _PG is applied to the common, and a drain connected in common to the SIT gate reset voltage V _PD.

The source line 31-1 to 31-n is connected to a source line reset transistor Q _RS1 to Q _RSn, pulse phi _R is adapted to be applied in common to the gate. The source lines 31-1 to 31-n are connected to storage capacitors C _{H1 to} C _Hn via transfer transistors Q _{T1 to} Q _Tn , respectively.
And the gates of the drive transistors Q _{D1 to} Q _Dn , respectively, so that a transfer pulse φ _T is commonly applied to each gate of the transfer transistors Q _{T1 to} Q _Tn . The drains of the driving transistors Q _{D1 to} Q _Dn are commonly connected to the power supply V _DD , and their sources are connected to the output line 34 via the horizontal selection switch transistors Q _{S1 to} Q _Sn . The gates of the horizontal selection switch transistors Q _{S1 to} Q _Sn are connected to a horizontal scanning circuit 35 so that horizontal scanning pulses φ _{H1 to} φ _Hn are applied.

The drive transistors Q _D1 -Q _D
The connection point between _Dn and the horizontal selection switch transistors Q _S1 to Q _Sn, respectively connected to the reset transistor Q _R1 to Q _Rn, to the gates of the reset transistors Q _R1 to Q _Rn, reset to a common pulse phi _R is adapted to be applied. Further, a load resistor _RL and an output line reset transistor _QRV are connected in parallel to the output line 34, and an output line reset pulse _φRV is applied to the gate of the reset transistor _QRV. I have. The signals stored in the storage capacitors C _{H1 to} C _Hn include drive transistors Q _{D1 to} Q _Dn, switch transistors Q _{S1 to} Q _Sn , and load resistance R _L.
And a source follower circuit composed of

The photometric circuit 33 is two MOS transistor switch _{Q C11 ~Q C1n, Q C21 ~Q} C2n, and peak photometric _circuit, and a MOS source follower circuit for averaging metering detection. MOS transistor switch Q _C11
To Q _C1n are connected to SIT source lines _31-1 to 31-n, the gates are connected in common, and pulse φ _CTL1 is applied. The sources of Q _{C11 to} Q _C1n are Q _{C21 to} Q _{C
The drains} of _C2n , the capacitors C _{M1 to} C _Mn and the gates of the drive MOS transistors Q _{MP1 to} Q _MPn of the peak photometry output MOS source follower circuit are connected. Q
The drains of _{MP1 to QMPn} are commonly connected to the power supply _VDD ,
The sources are connected to the peak photometric output lines 37, respectively. The peak metering output line 37 has a reset M
OS transistor Q _RMP, the load resistance R _P are connected in parallel, the Q _RMP adapted pulse phi _R is applied. The gates of Q _{C21 to} Q _C2n are connected in common and a pulse φ _CTL2 is applied, the sources of Q _{C21 to} Q _C2n are connected in common to line 38, and the driving MOS transistor Q of the average source photometric output MOS source follower circuit Connected to _MA gate. Drain of Q _MA is connected to the power supply V _{DD, and} a source is connected to the average photometric output line 36,
Reset MOS transistor Q _RMA, the load resistor R _A are connected in parallel, to the gate of Q _RMA pulse phi _R
Is applied.

Next, the line sensor constructed as described above will be described.
The operation will be described with reference to the pulse timing diagram shown in FIG.
explain. First, period t₁~ T_TwoAt the pulse φ_R,
φ_T,φ_CTL1,φ_CTL2To the “H” level, and the capacitance C_H1~
C_Hn,C_M1~ C_Mn, Source lines 31-1 to 31-n and photometric times
Reset the output lines 36 and 37 of the road. Then, period t
_Two~ T_ThreeAnd pulse φ_PGIs set to the “L” level and the P-MOS
Transistor Q_P1~ Q _PnTo turn on the pixels SIT S1
The gate voltage of Sn is V_PDReset to pixel SIT
I do. After resetting the pixel, the gate of the pixel SIT
Becomes a floating state and starts light accumulation.

In the period t _{3 to} t ₄ in the light accumulation period,
Since the pulse φ _CTL1 is at “H” level and the pulse φ _CTL2 is at “L” level, the output terminal MOSP of the photometry output line 37 is
, An output corresponding to the pixel output of the strongest light among all the pixels, that is, a peak photometric output is obtained. Period t
₅ ~t ₆ is also similar. In the middle of the period t ₄ ~t _5, the pulse phi _CTL1 is "L" level, the pulse phi _CTL2 becomes "H" level, the charge stored in the capacitor C _M1 -C _Mn far, capacitor C _M1 -C because it is averaged in the line capacitance of the source line of _Mn and Q _C21 to Q _C2n, averaging metering output appears at the output terminal MOSA photometric output line 36.

Here, the capacitance values of C _{M1 to} C _Mn are represented by C _M , FIG.
The line capacity of the line 38 which is connected to the gate of Q _MA C _L in, phi _CTL1 is "L", φ _CTL2 is immediately before the "H" C
_M1 -C When the _Mn of the voltage and V ₁ ~V _n, φ _CTL1 is "L", the voltage V _A of the source line Q _C21 to Q _C2n after phi _CTL2 becomes "H" is, V _A = C _M (V ₁ + V ₂ +
··· + V _n) can be expressed as _{/ (nC M + C L)} . At this time, the gate voltages of Q _{MP1 to} Q _MPn also become _VA .
This is the same even in the period t ₆ ~t _7.

[0034] In the period t ₈ ~t _9, becomes the pulse phi _T is "H" level, the pixel signals are transferred to the storage capacitor C _H1 -C _Hn, to operate the subsequent shift register 35, the pulse phi _H1 ~
When φ _Hn is applied to Q _{S1 to} Q _Sn , pixel signals are sequentially read to the output terminal OS of the output line 34.

As described above, in the line sensor configured as shown in FIG. 16, the pulses φ _CTL1 and φ _CTL1
By controlling _CTL2 , a peak photometric output and an average photometric output can be obtained.

Next, a third embodiment will be described with reference to FIG. FIG. 18 is a circuit diagram showing a line sensor having an average and peak photometry circuit in an apparatus for detecting a focal point in the same manner as in the second embodiment. In this line sensor, the pixels are the same as in the second embodiment shown in FIG.
The source lines 41-1 to 41-n are connected to an average photometry circuit 42 and a peak photometry / pixel signal readout circuit 43. The average light metering circuit 42 includes a source line reset transistor Q
_{RS1 to} Q _RSn , transfer transistors Q _{T11 to} Q _T1n , storage capacitors C _{A1 to} C _An, selection switches Q _{SA1 to} Q _SAn , and a shift register that applies pulses to the gates of the selection switches
The average photometric output MOSA is provided on an output line 46 via an integrating circuit 45.

The peak photometry / pixel signal readout circuit 43
It has substantially the same configuration as the pixel signal readout circuit of FIG. 16, and includes transfer transistors Q _{T21 to} Q _T2n and a storage capacitor C _H1.
To Q _Hn , drive transistors Q _{D1 to} Q _Dn , horizontal selection switch transistors QS _{1 to} Q _Sn , load resistance _RL , output line reset transistor _QRV, and decoder 47. In the peak photometry / pixel signal readout circuit of this embodiment, a decoder 47 is used for horizontal selection. When all the decoders 47 are turned on, a peak photometry output MOSP appears on the output line 48, and when the decoder 47 is sequentially turned on, Pixel signals appear on the output line 48 in time series.

Next, the operation of the third embodiment will be described with reference to the pulse timing chart shown in FIG. First, in the period t _{1 to} t ₂ , the pulses φ _R, φ _T1, φ
_T2 and all decoder outputs φ _{H1 to} φ _Hn are set to “H” level,
Source lines 41-1 to 41-n, storage capacitors C _{A1 to} C _An, C _H1 to
Reset C _Hn and output lines _46,48 . Subsequently, the pulse φ _{PG is set} to the “L” level in the period t ₂ to t ₃ , and Q _{P1 to} Q _Pn
Is turned on to reset the pixels SIT S1 to Sn.
When this reset ends, each pixel starts storing light.

During the light accumulation period (period t _{3 to} t _{6 in the} figure),
Since the pulse φ _T2 and the decoder outputs φ _{H1 to} φ _Hn remain at the “H” level, the output line 48 has an output corresponding to the pixel output to which the strongest light is applied among the outputs of all the pixels.
That is, a peak photometric output appears. During the light accumulation period, t ₄
In ~t ₅ and t ₄ '~t _5' duration, pulse phi _T1 becomes "L" level, when operating the shift register 44 during this period, the storage capacitor C _A1 -C in _An phi _T1 is "L" Since the electric charge corresponding to each pixel output until time t ₄ and t ₄ ′ at which the level is reached is accumulated, an output obtained by integrating each pixel signal, that is, an average photometric output appears on the output line 46.

When the light accumulation period ends (time t ₆ ),
The pulses φ _T1 and φ _T2 and the decoder outputs φ _{H1 to} φ _{Hn go} to “L” level, and the storage capacitors C _{A1 to} C _{An and} C _{H1 to} C _Hn
Accumulates a charge corresponding to each pixel output during the light accumulation period. Subsequently, at time t ₇ , the pulse φ _RV becomes “H” level, and the output line 48 is reset. Then the decoder 47 from the time t ₈ becomes successively "H" level, the pixel signal appears at the output line 48.

In FIG. 19, the timing of switching the pulse φ _T1 to the “H” or “L” level may be performed during the light accumulation period or during the integration period depending on the usage.
Similarly to _T2 , the average photometry output may be taken out after the light accumulation is always set to the “H” level and the light accumulation is completed. The shift register 44 can be replaced with a decoder.

Next, a fourth embodiment will be described with reference to FIG. In this embodiment, the present invention is applied to an apparatus for detecting a focal point in the same manner as in the second embodiment. FIG. 20 shows a circuit configuration of an area sensor having an average and peak photometry circuit in the focal point detecting apparatus. The figure is shown. This area sensor is obtained by arranging the pixels of the line sensor shown in FIG. 16 in a matrix of m × n. The matrix-shaped pixels are provided with a V decoder 51 and an R decoder 52 for row selection.
Each pixel is provided with row selection switches Q _{V11 to} Q _Vmn . Note that this row selection V decoder 51 and switch Q
_When only one row is used, _{V11 to QVmn} can be omitted by adjusting the output of the R decoder 52 (the pixels are always reset except for the selected row).

The operation of this sensor is the same as that of the first embodiment except that the operation of selecting a row by the V decoder 51 and the R decoder 52 is required.
This is the same as the line sensor shown in FIG.

FIG. 21 shows an area sensor according to a fifth embodiment in which the pixels of the line sensor shown in FIG. 18 are arranged in an m × n matrix in the same manner as the fourth embodiment shown in FIG. FIG. 4 is a circuit configuration diagram. The operation of this sensor is also the same as that of FIG.
This is the same as the line sensor shown in FIG.

[0045]

As described above with reference to the embodiments,
ADVANTAGE OF THE INVENTION According to this invention, it can read out the pixel signal of a photoelectric conversion apparatus using the average value and the peak value of the signal of the pixel array itself of a photoelectric conversion apparatus, and can perform appropriate focusing detection by performing an interpolation process. . In addition, since the detection of the average value and the detection of the peak value are obtained from one photoelectric conversion device, downsizing and cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a configuration of the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing photoelectric conversion characteristics of SIT.

FIG. 4 shows an output OSP of a peak value detection comparator and outputs MOS1, MOS2, and MOS2 of an addition output detection comparator.
FIG. 6 is a diagram showing a relationship between MOS3 and a flag FGi indicating each state.

FIG. 5 is a flowchart showing the operation from the start to the end of integration in the first embodiment shown in FIG. 2;

FIG. 6 is a diagram illustrating an aspect of focus detection.

FIG. 7 is an explanatory diagram related to two-image interval detection.

FIG. 8 is a diagram illustrating a relationship between a comparator output, a flag, and a read timing.

FIG. 9 is a diagram illustrating an aspect of an interpolation process.

FIG. 10 is a flowchart illustrating an operation up to the detection of a focal point.

FIG. 11 is a diagram illustrating a circuit configuration for obtaining a contrast signal.

FIG. 12 is a diagram illustrating a relationship between a lens position and a contrast signal.

FIG. 13 is a block diagram illustrating a configuration of a focus detection circuit according to a second embodiment.

FIG. 14 is a diagram illustrating signal components at the time of peak monitor detection.

FIG. 15 is a diagram illustrating a signal component when an average monitor is detected.

FIG. 16 is a circuit configuration diagram of a line sensor used in the second embodiment.

FIG. 17 is a pulse timing chart for explaining the operation of the line sensor shown in FIG. 16;

FIG. 18 is a circuit configuration diagram of a line sensor used in the third embodiment.

19 is a pulse timing chart for explaining the operation of the line sensor shown in FIG. 18.

FIG. 20 is a circuit configuration diagram of an area sensor used in the fourth embodiment.

FIG. 21 is a circuit configuration diagram of an area sensor used in the fifth embodiment.

FIG. 22 is a diagram illustrating one-line output of a photoelectric conversion element when a bright main subject is present in the dark.

[Fig. 23] Fig. 23 is a diagram illustrating an output of one line of the photoelectric conversion element when there is a spot-like bright object other than the main subject.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 imaging optical system 2 photoelectric conversion device 3 peak detection circuit 4 average value detection circuit 5 drive circuit 6 focus detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 5/335 H04N 1/04 102 (56) References JP-A-58-147280 (JP, A) JP-A-60-58780 ( JP, A) JP-A-63-175468 (JP, A) JP-A-62-115864 (JP, A) JP-A-2-36681 (JP, A) JP-A-1-103077 (JP, A) JP JP-A-63-196181 (JP, A) JP-A-59-6677 (JP, A) JP-A-1-222583 (JP, A) JP-A-63-76476 (JP, A) JP-A-62-115863 (JP, A) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02B ^7/ 28-7/40 G03B 3/00-3/12 H04N 5/30-5/335

Claims (4)

(57) [Claims] 1. A photoelectric conversion element arranged in an array for converting a light quantity distribution into an electric signal, a photographing optical system for forming an image of a light beam from a subject on the photoelectric conversion element, and each pixel of the photoelectric conversion element The number of peak detection circuits for detecting a pixel signal having the largest amount of light from among signals and an average value detection circuit for detecting an average value of all pixel signals of the photoelectric conversion element are reduced.
In the imaging device provided with the two, two images read from the photoelectric conversion element based on the integration time and the integration value of the signals of the peak detection circuit and the average value detection circuit, respectively.
Interpolate image signals to form signals for focus detection
Imaging device, characterized in that that. 2. A pixel output line voltage holding capacitor connected via a first switch group connected in series to each pixel output line of the photoelectric conversion element, and a peak input terminal connected to the capacitor. And a first MOS source follower circuit connected to the pixel output line voltage holding capacitor, the average value detection circuit includes a second switch group having one end connected to the pixel output line voltage holding capacitor,
Of claim 1 imaging apparatus, wherein the configured at a second MOS source follower circuit connected to a gate input terminal in common to the other end of the switch group. 3. An average value detection circuit comprising: a pixel output line voltage holding capacitor connected through a switch group connected in series to each pixel output line of the photoelectric conversion element; and each pixel held by the capacitor. 2. The image pickup apparatus according to claim 1 , wherein said image pickup apparatus comprises means for adding and reading signals. 4. A switch in which the peak detection circuit has an output line common to a pixel signal readout line of the photoelectric conversion element, and a peak output and a pixel signal readout output to the common line are connected to the common line. imaging apparatus according to claim 1 or 3, wherein it is configured so as to selectively output is controlled by a signal applied to the group.