JPH04304407A - Focusing detector - Google Patents

Abstract

PURPOSE:To perform highly accurate focusing detection by performing proper integration time control by a focusing detector which performs the focusing detection according to the signal from a photoelectric conversion device. CONSTITUTION:The focusing detector consists of an image pickup optical system 1 which images the luminous flux from an object on the photoelectric conversion device 2, the photoelectric conversion device 2 which converts the light quantity distribution from the image pickup optical system 1 into an electric signal, a peak detecting circuit 3 which detects the peak value of the photoelectric conversion device 2, a means value detecting circuit 4 which detects the means value of the photoelectric conversion device 2, and a focusing detecting circuit 6 which reads out the photoelectric conversion signal of the photoelectric conversion device 2 according to the detection signals from the peak detecting circuit 3 and mean value detecting circuit 4 to perform the focusing detection and outputs the driving quantity of the optical system 1 to a driving circuit 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a focused point detection device for detecting a focused point based on a signal from a photoelectric conversion element.

0002

2. Description of the Related Art When detecting a focused point based on a signal from a photoelectric conversion element, appropriate integral control and readout control of the photoelectric conversion element is required. Many proposals have been made so far. For example, a method (patent application There is a method in which the peak value of the output of the photoelectric conversion element itself is detected and the integration time of the photoelectric conversion element is controlled. Furthermore, there is a method of detecting the MAX and MIN values of the photoelectric conversion element and controlling the integration time of the photoelectric conversion element based on the contrast (MAX-MIN) value (Japanese Patent Application No. 1-22258).
3) etc.

0003

Problems to be Solved by the Invention The current storage type photoelectric conversion elements have a small dynamic range, and when controlling the integration time with a general subject as a target, the following disadvantages occur. 22 and 23 show the output of one line of the photoelectric conversion element with the horizontal axis representing the readout pixel;
A) shows the signal state in an ideal state, (B) shows the signal state when integral time control is performed by peak value detection, and (C) shows the signal state when integral time control is performed by average value detection. . When the integration time is controlled using the average value of the entire photoelectric conversion element, there is a bright main subject in the dark [(A in Figure 22)
], the originally necessary signal becomes saturated [(C in Figure 22)
)] Correct distance measurement is not possible.

Furthermore, when the integration time is controlled using the peak value of the photoelectric conversion element, if there is a bright spot other than the main subject [Fig. 23(A)], the dynamic range of the main subject becomes spot-like. As a result, the distance becomes smaller [FIG. 23(B)] and accurate distance measurement cannot be performed. Also, when the contrast difference (MAX-MIN) of the photoelectric conversion element is used as a reference, the same problem as when the integration time is controlled using the peak value occurs.

The present invention was made in order to solve the above-mentioned problems of the conventional integration time control method of the photoelectric conversion element in focus point detection, and is aimed at general subjects and provides appropriate integration under any conditions. It is an object of the present invention to provide a focused point detection device that can perform focused point detection through time control.

[0006]

[Means and Operations for Solving the Problems] The structure of the present invention for solving the above problems will be explained based on the conceptual diagram of FIG. The in-focus point detection device according to the present invention includes a photographing optical system 1 that guides a luminous flux of a subject to a photoelectric conversion element 2, a photoelectric conversion of a light intensity distribution from the photographic optical system 1 into an electric signal distribution, and peak detection of the photoelectrically converted signal. The photoelectric conversion element 2 outputs to the circuit 3 and the average value detection circuit 4, and part or all of the photoelectrically converted signal is read out by the timing signal from the focused point detection circuit 6, and the activation signal from the focused point detection circuit 6. The peak detection circuit 3 detects the peak value of a part or the whole of the photoelectric conversion element 2 and outputs a peak detection signal to the focused point detection circuit 6. an average value detection circuit 4 that detects the average value of the part or the whole and outputs an average value detection signal to the focused point detection circuit 6;
Based on the detection signals from the peak detection circuit 3 and the average value detection circuit 4, part or all of the photoelectric conversion signal of the photoelectric conversion element 2 is read out to detect the in-focus point, and information (position, A focused point detection circuit 6 inputs the focal length (focal length, etc.) and outputs the driving amount of the photographing optical system 1 to the drive circuit 5; It is comprised of a drive circuit 5 that drives the photographing optical system 1 according to the drive amount from the focus detection circuit 6.

[0007] In the focused point detection device configured as described above, after the peak detection circuit 3 detects the peak value of the photoelectric conversion signal, a part or all of the photoelectric conversion element 2 is read out,
Furthermore, the next readout timing is determined according to the average value output at the time of peak value detection, and the next readout timing is read out again, and the signal used for in-focus point detection is interpolated based on the outputs of the two photoelectric conversion elements.
Perform in-focus point detection.

[0008]

[Example] Next, an example will be explained. FIG. 2 is a circuit configuration diagram showing an embodiment in which the present invention is applied to a focused point detection device using an AF line sensor. The photoelectric conversion device in this example includes a static induction transistor (Statistical Induction Transistor).
c Induction Transistor (hereinafter abbreviated as SIT) type solid-state imaging device. This SIT type solid-state imaging device has SIT Fi (i=1~
n), a transistor Ei (i=1 to n) that resets SIT Fi with the RSin signal, and SIT F
A charge storage capacitor Ci (i=1 to n) stores the charge generated at i via a transistor Di (i=1 to n) controlled by the SFin signal, and the charge of the charge storage capacitor Ci is amplified and output. Transistor Bi
(i=1 to n), a transistor Ai (i=1 to n) that selectively controls the transistor Bi, and a transistor Gi (i=1 to n) that amplifies and outputs the charge of the charge storage capacitor Ci during addition reading. , a transistor Hi (i=1 to n
), and a transistor Ii (i=1 to n) that resets the charge of the charge storage capacitor Ci by the Rin signal.
, a transistor L for resetting the addition output line, a decoder DEC that controls the readout control transistors Ai and Hi with the DCin signal, and a current-voltage conversion resistor R.
1, a transistor K that resets the output line with the signal RV, a comparator OP1 that compares the output OS converted from current to voltage by R1 with Vref1 corresponding to the peak value level and outputs it as an OSP signal, and the timing of addition readout. transistor J that controls the voltage using the AVin signal, and operational amplifier OP2 that converts the sum current into voltage.
, and the output of operational amplifier OP2 are added to the current reference voltage Vre
Compare with the divided value of f2 and find MOS1, MOS2, MOS
Comparators OP3, OP4, OP5 output to 3,
Resistors R2 and R3 that divide the addition current reference voltage Vref2
, R4. Note that the addition current reference voltage Vref2 is variable according to the number of pixels to be added, and the addition current output MOS1 is outputted earlier than the OSP that detects the peak value output.
It is set not to be N.

FIG. 3 shows the photoelectric conversion characteristics of SIT. S.I.
As shown in the figure, the T output changes linearly with the amount of light up to the saturation level. Figure 4 shows the output OSP of the peak value detection comparator OP1 and the addition output detection comparator OP.
3, OP4, OP5 output MOS1, MOS2, MOS
3 and flags FGi (i=0 to 3) indicating each state.

FIG. 5 shows the flow from the start to the end of integration (S
UB1). Following the start of step F1000,
In step F1001, the focus area is specified by switching between the spot area and the wide area [signal readout transistors Ai, Hi are selected by the decoder DEC;
(i=j to m)]. Then step F1
002, pixel, charge storage capacitor Ci (
i=1 to n), flag FGi (i=0 to 3), and limiter timer are reset. Next, in step F1003, the integration and limiter timers are started, and in step F100
In step 4, the limiter time is determined (t<TL), and t<TL is determined.
If TL, the process moves to step F1005, where the peak value detection signal OSP is determined, and if OSP=1, the process returns to step F1004. If OSP=1, step F100
In step F1007, the transistor Di (i=1 to n) that controls the integration time to be constant is turned off using the SFin signal, and then in step F1007, the pixel signal is input to the decoder DEC using the OS signal.
It is read out by the shift signal (taken into DD1).

Next, in step F1009, the transistor Di (i=1 to n) is turned on again, and the decoder D is turned on.
Transistors Ai, Hi (i=
Step F in which only j to m) are turned on and the comparator output MOS2 for determining the addition output is determined (MOS2=H)
Enter 1010. If output MOS2=H, step F
Comparator output MOS1 for determining addition output at 1021
(MOS1=H), and if MOS1=H, only flag FG0 is set to 1 in step F1022 (FG
0=1). If the output MOS1 is not high in step F1021, the process moves to step F1023 and only the flag FG1 is set to 1 (FG1=1).

[0012] In step F1010, the output MOS2=
If not H, the process moves to step F1030, and the comparator output MOS3 for determining the addition output is determined (MOS3=H).
is performed, and if the output MOS3 is not high, step F103
1 sets only flag FG3 to 1 (FG3=1) and outputs M
If OS3=H, only flag FG2 is set to 1 (FG2=1) in step F1032. Then step F103
3, the limiter time is determined (t<TL), and t<T
If L, FG2 is checked again (FG2=1) in step F1034, and if FG2=1, the process returns to step F1033. If FG2=1, step F103
5, the comparator output MOS2 for determining the addition output again
(MOS2=H) is determined, and if MOS2=H is not determined, the process returns to step F1033.

[0013] When MOS2=H in step F1035,
When t<TL is not established in step F1033, and when t<TL is established in step F1004, the process moves to step F1036, and the transistor Di (i=1 to n), which controls the integration time constant using the SFin signal, is turned off. Next, in step F1037, the OS signal is read out (taken into DD2) by the shift signal of the pixel signal decoder DEC, and after the operations of steps F1022 and F1023, the process proceeds to step F1040 and ends.

FIG. 6 shows how the in-focus point is detected. The primary image plane is transmitted through the condenser lens CL, and the taking T
Images A and B are formed on the sensor surface S through two sets of separator lenses SL that look at the pupil divided into two parts L. The interval between the A and B2 images changes depending on the focus state.

FIG. 7 shows an explanatory diagram regarding detection of the interval between two images. FIG. 7(C) is a diagram showing the relationship between pixels and sensor output, and shows two images A and B superimposed, and in the in-focus point detection calculation, the absolute value of the difference between images A and B (displayed by diagonal lines) is used for correlation calculation. value. FIG. 7A shows an interpolation calculation for determining the two-image interval from the correlation calculation value, that is, a calculation for calculating the true two-image interval from the point where the correlation calculation value is MIN and two points on both sides. (B) in FIG. 7 is a correlation calculation similar to (A), but
The interpolation interval is twice that in case (A), and is also used for low contrast.

FIG. 8 shows the comparator output OSP, MOS
1, MOS2, MOS3 and flag FGi (i=0 to 3)
FIG. 4 is a diagram showing the relationship between the reading timing and the reading timing. ■ in the diagram
indicates the output indicating the peak value within the pixel, and ■ to ■ indicate the added value in each state. If FG0=1 (
(2), (2), the signal is read out at time a when the peak value reaches the OSP level. Since the added value is also almost the same as the peak value (■ exceeds MOS1) and there may be no contrast, the interpolation calculation shown in FIG. 7B is also used for detection. When FG1=1 (■, ■), the signal is read out at time a when the peak value reaches the OSP level, and detected by the interpolation calculation shown in FIG. 7(A). When FG2=1 (■, ■), the peak value is OS
The signal is read out at time a when the P level is reached and at time b when the addition output reaches the level of MOS2. The signals are interpolated using the signals DD1 and DD2 read at time points a and b, and detected by the interpolation calculation shown in FIG. 7(A). FG3=
In the case of 1 (■, ■), the signal is read out at time a when the peak value reaches the OSP level and at time c when the limiter time is reached. Signals DD1 and D read out at time points a and c
The signal is interpolated using D2 and detected by the interpolation calculation shown in FIG. 7(A). When FGi=0 (i=0 to 3), the signal is read out at time d when the limiter time is reached. The interpolation calculation shown in FIG. 7B is also used for detection.

FIG. 9 shows interpolation processing for image A when FG2=1 and FG3=1. The data of DD1 and DD2 are shown in FIGS. 9A and 9B. SIT output is shown in Figure 3.
As shown in , it changes linearly, so DD1, DD2
Figure 9 (C) is obtained by linear interpolation using the data and two integration times.
Convert the data as shown in .

FIG. 10 shows the flow up to detection of the in-focus point of the camera. From the start step (F1100), after determining whether the focus area is wide or spot (F1101), a 1st release determination (1st=ON) is performed in step F1102. If 1st=OFF, F11
Return to 01, and if 1st=ON, SUB1 shown in Figure 5
The integral operation is performed (F1103). Then step F1
At 104, the in-focus point detection calculation shown in FIG. 7 is performed, and at step F
At step 1105, the photographing optical system is driven to the in-focus position, and a stop step (F1105) is performed.

In this embodiment, the peak value and average value can be detected by the signal detection pixel, and by reading out the signal at the time of detection and performing interpolation processing, it is possible to obtain a signal with a high S/N ratio and achieve high focusing accuracy. is obtained. Further, by detecting the peak value and the average value using one solid-state imaging device, size reduction and cost reduction can be realized.

Furthermore, in this embodiment, S is used as a photoelectric conversion device.
Although the one using an IT-type solid-state imaging device is shown, AMI (
Amplified MOS Intelligent
Imager), CMD (Charge Module)
An imaging device capable of non-destructive readout, such as a solid-state imaging device may be used. A method other than this embodiment may also be used in the in-focus point calculation.

Next, a second embodiment will be described in which the present invention is applied to a focused point detection device using a contrast method. As shown in FIG. 11, the contrast method uses a contrast signal obtained by extracting a signal in a certain frequency band from the output of a sensor 11 through a bandpass filter 12 and integrating the signal in an integrating circuit 13.

FIG. 12 is a diagram showing the relationship between the focus lens position and the contrast signal. At the lens position JP during focusing, the contrast signal is maximum, and the contrast signals before and after that are monotonous with respect to the lens position. increase or decrease By using this relationship and obtaining the contrast value while moving the lens, the lens position for focusing can be determined.

The present embodiment aims to use the average and peak photometric outputs from the sensor to effectively utilize the dynamic range of the signal processing system when performing in-focus point detection using the contrast method. FIG. 13 shows the configuration of the focused point detection circuit 6 shown in FIG. 1. This focused point detection circuit includes a determination circuit 21 composed of a comparator that binarizes the signal from the photoelectric conversion device, a delay line 22, and a bandpass filter 23 that extracts a specific frequency band from the signal output from the delay line 22. and focus area control signal 2
4, a gate circuit 25 that gates the bandpass filter output according to the conditions of the determination circuit 21, an A/D conversion circuit 26 that A/D converts the output of the gate circuit 25, and an adder circuit 27 that adds the A/D conversion outputs. It is composed of

The operation sequence regarding integral control and signal readout in this embodiment is the same as that in the first embodiment, and is as shown in FIGS. 4, 5, and 8.

Next, the timing chart of the detection section is shown in FIG.
4 and FIG. 15. FIG. 14 shows signal components when detecting a peak monitor, and FIG. 15 shows signal components when detecting an average monitor. In FIG. 14, the signal region to be extracted is determined based on the comparator output shown in (B) which determines a certain level a with respect to the sensor output shown in (A). Figure 1
In step 5, the signal region is determined based on the sensor output shown in (A) and the comparator output shown in (B) which determines the non-saturated output level b of the sensor output. There is no area where the comparator output in FIG. 14(B) and the comparator output in FIG. 15(B) cross each other.

A bandpass filter 23 extracts a predetermined frequency component of the signal whose region is determined by the comparator output, and performs digital addition according to the characteristic (response delay characteristic) of the bandpass filter 23 after A/D conversion. The added value of the bandpass filter 23 during readout shown in FIG. 14 is added with a certain weighting to the added value of the bandpass filter 23 during readout shown in FIG. do. For example, the added value at the time of peak detection is weighted by b/a, and added to the added value at the time of average value detection to obtain a contrast signal.

FIG. 16 shows a circuit diagram of the AF line sensor used in the second embodiment. The AF line sensor has some of the functions of the photoelectric conversion device 2, peak detection circuit 3, and average value detection circuit 4 shown in FIG. In FIG. 16, S1~
Sn is a pixel SIT constituting the line sensor, and each S
IT is P-MOS for resetting the gate of SIT
It includes transistors QP1 to QPn, and the SIT gate and the sources of QP1 to QPn are connected, respectively. The drain of SIT is connected to a power source (not shown). The sources of SIT are source lines 31-1 to 31
-n, and each source line is connected to a pixel signal readout circuit 32 and a photometry circuit 33. QP1~Q
The gates of Pn are connected in common to which pulse φPG is applied, and the drains are commonly connected to SIT gate reset voltage VPD.
It is connected to the.

The source lines 31-1 to 31-n are connected to source line reset transistors QRS1 to QRSn.
, and a pulse φR is commonly applied to their gates. Also, source line 31-1
~31-n are connected to the gates of storage capacitors CH1-CHn and drive transistors QD1-QDn via transfer transistors QT1-QTn, respectively, and are commonly connected to the gates of transfer transistors QT1-QTn. A pulse φT is applied. Further, the drains of the drive transistors QD1 to QDn are commonly connected to the power supply VDD, and their sources are connected to the output line 34 via the horizontal selection switch transistors QS1 to QSn. Each gate of the horizontal selection switch transistors QS1 to QSn is connected to a horizontal scanning circuit 35 and configured to receive horizontal scanning pulses φH1 to φHn.

Further, the drive transistors QD1 to
QDn and horizontal selection switch transistors QS1 to QS
At the connection point with n, reset transistors QR1 to Q
Rn respectively, and its reset transistor Q
A common reset pulse φ is applied to each gate of R1 to QRn.
R is applied. Further, a load resistor RL and an output line reset transistor QRV are connected in parallel to the output line 34, and an output line reset pulse φRV is applied to the gate of the reset transistor QRV. The signals stored in the storage capacitors CH1 to CHn are read out by a source follower circuit composed of drive transistors QD1 to QDn, switch transistors QS1 to QSn, and a load resistor RL.

The photometric circuit 33 includes two types of MOS transistor switches QC11 to QC1n, QC21 to QC.
2n, and peak photometry circuit, average photometry detection MOS
It consists of a source follower circuit. The drains of MOS transistor switches QC11 to QC1n are S
It is connected to IT source lines 31-1 to 31-n, and its gates are commonly connected and a pulse φCTL1 is applied thereto. Each source of QC11 to QC1n is QC21 to Q
MO for driving each drain of C2n, capacitance CM1 to CMn and MOS source follower circuit for peak photometry output
It is connected to the gates of S transistors QMP1 to QMPn. The drains of QMP1 to QMPn are commonly connected to the power supply VDD, and the sources are respectively connected to the peak photometry output line 37. In addition, the peak photometry output line 37 includes a reset MOS transistor QRM.
P and load resistance RP are connected in parallel, and QRM
A pulse φR is applied to P. The gates of QC21 to QC2n are commonly connected to apply the pulse φCTL2, and the sources of QC21 to QC2n are commonly connected to line 38 and connected to the gate of the drive MOS transistor QMA of the average photometry output MOS source follower circuit. ing. The drain of QMA is connected to the power supply VDD, the source is connected to the average photometry output line 36, and the reset MOS transistor Q
RMA and load resistance RA are connected in parallel,
A pulse φR is applied to the gate of the QRMA.

Next, the operation of the line sensor configured as described above will be explained with reference to the pulse timing diagram shown in FIG. First, during the period t1 to t2, the pulses φR, φT, φCTL1, and φCTL2 are set to “H”.
level, capacitance CH1~CHn, CM1~CMn,
The source lines 31-1 to 31-n and the output lines 36 and 37 of the photometric circuit are reset. After that, period t2 ~
At t3, pulse φPG is set to “L” level and P-MOS
Transistors QP1 to QPn are turned on, and pixel SIT
The gate voltages of S1 to Sn are fixed to VPD and the pixel SIT is reset. After pixel reset is completed, pixel SIT
The gate becomes floating and begins to accumulate light.

During the period t3 to t4 in the optical accumulation period, the pulse φCTL1 is at “H” level, and the pulse φCTL
2 is at the "L" level, the output terminal MOSP of the photometric output line 37 provides an output corresponding to the output of the pixel that is hit by the strongest light among all the pixels, that is, the peak photometric output. The same applies to the period t5 to t6. In the middle period t4 to t5, the pulse φCTL1 goes to "L" level and the pulse φCTL2 goes to "H" level, and the charges accumulated in the capacitors CM1 to CMn until then are transferred to the capacitor CM1.
Since the line capacitances of the source lines ~CMn and QC21 ~QC2n are averaged, an average photometric output appears at the output terminal MOSA of the photometric output line 36.

[0033] Here, the capacitance values of CM1 to CMn are CM
, CL is the line capacitance of line 38 connected to the gate of QMA in FIG. 16, φCTL1 is “L”, φCTL2
The voltage at the CM1 to CMn terminals immediately before becomes “H” is V1.
~Vn, the voltage VA of the source line of QC21 ~QC2n after φCTL1 goes “L” and φCTL2 goes “H” is VA = CM (V1 + V2
+...+Vn)/(nCM+CL). At this time, the gate voltage of QMP1 to QMPn also becomes VA. This also applies to the period t6 to t7.

During the period t8 to t9, the pulse φT is “
H” level, and the pixel signal reaches the storage capacitors CH1 to CHn.
Then, when the shift register 35 is operated and the pulses φH1 to φHn are applied to QS1 to QSn, the pixel signals are sequentially read out to the output terminal OS of the output line 34.

As explained above, in the line sensor configured as shown in FIG.
, φCTL2, a peak photometric output and an average photometric output can be obtained.

Next, a third embodiment will be explained based on FIG. 18. FIG. 18 is a circuit configuration diagram showing a line sensor having average and peak photometry circuits in an apparatus for detecting a focused point using a method similar to that of the second embodiment. In this line sensor, the pixels are the same as those in the second embodiment shown in FIG.
2 and a peak photometry/pixel signal readout circuit 43. The average photometry circuit 42 includes source line reset transistors QRS1 to QRSn, transfer transistors QT11 to QT1n, and storage capacitors CA1 to
CAn, selection switches QSA1 to QSAn, and a shift register 44 that applies pulses to the gates of the selection switches, and the average photometric output MOSA appears on an output line 46 via an integrating circuit 45.

The peak photometry/pixel signal readout circuit 43 has almost the same configuration as the pixel signal readout circuit shown in FIG. 16, and includes transfer transistors QT21 to QT2n,
Storage capacitors CH1 to CHn, drive transistors QD1 to QDn, horizontal selection switch transistor Q
It consists of S1 to QSn, a load resistor RL, an output line reset transistor QRV, and a decoder 47. In the peak photometry/pixel signal readout circuit of this embodiment, the decoder 47 is used for horizontal selection, and when all the decoders 47 are turned on, the peak photometry output MOSP appears on the output line 48, and when the decoders 47 are turned on one after another,
The pixel signals appear on the output line 48 in time series.

Next, the operation of the third embodiment configured as described above will be explained with reference to the pulse timing chart shown in FIG. First, during the period t1 to t2, the pulses φR,
φT1, φT2 and all decoder outputs φH1 to φHn
is set to "H" level, and the source lines 41-1 to 41-n are set to "H" level.
, storage capacitors CA1 to CAn, CH1 to CHn, and output lines 46 and 48 are reset. Then period t2
~t3, pulse φPG is set to “L” level QP1~Q
Turn on Pn and reset the pixels SIT S1 to Sn. Once this reset is complete, each pixel begins to accumulate light.

During the optical accumulation period (period t3 to t6 in the figure)
), pulse φT2 and decoder output φH1 to φHn are “
Since it remains at the "H" level, an output corresponding to the output of the pixel that is hit by the strongest light among the outputs of all pixels, that is, a peak photometric output appears on the output line 48. During the light accumulation period, from t4 to t5 During the period from t4' to t5', the pulse φT1 becomes "L" level, and when the shift register 44 is operated during this period, the storage capacitors CA1 to C
An has times t4 and t when φT1 becomes “L” level.
Since charge corresponding to each pixel output up to 4' is accumulated, an output obtained by integrating each pixel signal, that is, an average photometric output appears on the output line 46.

When the optical accumulation period ends (time t6), pulses φT1, φT2 and decoder outputs φH1 to φ
Hn becomes “L” level, and the storage capacitances CA1 to CAn,
Charges corresponding to each pixel output during the optical accumulation period are accumulated in CH1 to CHn. Then, at time t7, pulse φRV
becomes "H" level and resets the output line 48. Thereafter, from time t8, the decoder 47 sequentially attains the "H" level, and a pixel signal appears on the output line 48.

In FIG. 19, pulse φT1 is set to “H”.
Depending on the usage, the timing of switching to the `` or ``L'' level may be done during the optical accumulation period, or it may be kept at the ``H'' level during the integration period, similar to pulse φT2, and then switched to the ``H'' level after the optical accumulation is completed. The average photometric output may be taken out.Also, the shift register 44 can be replaced with a decoder.

Next, a fourth embodiment will be explained based on FIG. 20. In this embodiment, the present invention is applied to a device for detecting a focused point in the same manner as in the second embodiment, and FIG. 20 shows the circuit configuration of an area sensor having average and peak photometry circuits in the focused point detection device. Show the diagram. This area sensor has pixels of the line sensor shown in FIG. 16 arranged in an m×n matrix, and the matrix pixels are provided with a V decoder 51 and an R decoder 52 for row selection. row selection switch QV11 ~QVmn
has been established. Note that when the row selection V decoder 51 and switches QV11 to QVmn are used for only one row, they can be adjusted by adjusting the output of the R decoder 52 (pixels other than the selected row are always in the reset state). It is also possible to omit it.

The operation of this sensor is as follows: V decoder 51,
The line sensor is the same as the line sensor shown in FIG. 16 except that the R decoder 52 requires an operation to select a row.

FIG. 21 shows an area sensor according to a fifth embodiment in which the pixels of the line sensor shown in FIG. 18 are arranged in an m×n matrix like the fourth embodiment shown in FIG. 18 is a circuit configuration diagram, and the operation of this sensor is similar to the line sensor shown in FIG. 18, except that the V decoder and R decoder are required to select a row.

[0045]

[Effect of the invention] As explained above based on the embodiments,
According to the present invention, the pixel signal of the photoelectric conversion device is read out using the average value and peak value of the signal of the pixel array itself of the photoelectric conversion device, and by performing interpolation processing, it is possible to perform appropriate in-focus point detection. . Further, since the average value detection and the peak value detection are obtained from one photoelectric conversion device, it is possible to reduce the size and cost.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing the configuration of the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing the photoelectric conversion characteristics of SIT.

[Figure 4] Output OSP of the peak value detection comparator, output MOS1, MOS2 of the comparator for addition output detection,
It is a figure which shows the relationship between MOS3 and the flag FGi which shows each state.

FIG. 5 is a flowchart showing the operation from the start to the end of integration in the first embodiment shown in FIG. 2;

FIG. 6 is a diagram showing an aspect of focus detection.

FIG. 7 is an explanatory diagram regarding two-image interval detection.

FIG. 8 is a diagram showing the relationship between comparator output, flag, and read timing.

FIG. 9 is a diagram showing a mode of interpolation processing.

FIG. 10 is a flowchart showing operations up to in-focus point detection.

FIG. 11 is a diagram showing a circuit configuration for obtaining a contrast signal.

FIG. 12 is a diagram showing the relationship between lens position and contrast signal.

FIG. 13 is a block configuration diagram showing the configuration of a focused point detection circuit according to a second embodiment.

FIG. 14 is a diagram showing signal components during peak monitor detection.

FIG. 15 is a diagram showing signal components during average monitor detection.

FIG. 16 is a circuit configuration diagram of a line sensor used in a second embodiment.

17 is a pulse timing diagram for explaining the operation of the line sensor shown in FIG. 16. FIG.

FIG. 18 is a circuit configuration diagram of a line sensor used in the third embodiment.

19 is a pulse timing chart for explaining the operation of the line sensor shown in FIG. 18. FIG.

FIG. 20 is a circuit configuration diagram of an area sensor used in a fourth embodiment.

FIG. 21 is a circuit configuration diagram of an area sensor used in the fifth embodiment.

FIG. 22 is a diagram showing the output of one line of the photoelectric conversion element when there is a bright main subject in the dark.

FIG. 23 is a diagram showing the output of one line of the photoelectric conversion element when there is a bright spot other than the main subject.

[Explanation of symbols]

1 Imaging optical system 2 Photoelectric conversion device 3 Peak detection circuit 4 Average value detection circuit 5 Drive circuit 6 Focused point detection circuit

Claims (5)

[Claims] Claim 1: A photographic optical system that forms an image of a light beam from a subject on a photoelectric conversion device, and photoelectric conversion pixels arranged in a one-dimensional array or a two-dimensional array that converts the light intensity distribution from the photographic optical system into an electrical signal. a photoelectric conversion device including a readout control circuit thereof, a focus detection circuit that detects a focus point based on a photoelectrically converted signal, and a drive circuit that moves a photographing optical system to the detected focus point position. A focused point detection device comprising: a peak detection circuit that detects a pixel signal with the highest amount of light from among each pixel signal of the photoelectric conversion device; and an average value detection circuit that detects an average value of all the pixel signals of the photoelectric conversion device. What is claimed is: 1. A focused point detection device comprising a circuit, and configured to read signals from the photoelectric conversion device based on signals from the peak detection circuit and the average value detection circuit. 2. A claim characterized in that two output signals read from a photoelectric conversion device are subjected to interpolation processing based on signals from a peak detection circuit and an average value detection circuit to form a signal used for in-focus point detection. Item 1. Focused point detection device according to item 1. 3. The peak detection circuit includes a first circuit connected in series to each pixel output line of the photoelectric conversion device.
The average value detection circuit includes a pixel output line voltage holding capacitor connected through a group of switches, and a first MOS source follower circuit having a gate input terminal connected to the capacitor. Claim characterized in that it is constituted by a second switch group each having one end connected to a capacitor, and a second MOS source follower circuit having a gate input terminal commonly connected to the other end of the second switch group. 3. The focused point detection device according to 1 or 2. 4. The average value detection circuit includes a pixel output line voltage holding capacitor connected to each pixel output line of the photoelectric conversion device via a switch group connected in series, and each pixel held by the capacitor. Claim 1 characterized by comprising: means for adding and reading signals.
Or the focused point detection device according to 2. 5. The peak detection circuit shares an output line with a pixel signal readout line of the photoelectric conversion device, and connects the peak output output to the common line and the pixel signal readout to the common line. Claim 1, 2 or 4, characterized in that it is configured to be selectively output under control by a signal given to the group.
The focused point detection device described.