JPS5885583A - Manufacture of semiconductor laser - Google Patents

Manufacture of semiconductor laser

Info

Publication number
JPS5885583A
JPS5885583A JP18309181A JP18309181A JPS5885583A JP S5885583 A JPS5885583 A JP S5885583A JP 18309181 A JP18309181 A JP 18309181A JP 18309181 A JP18309181 A JP 18309181A JP S5885583 A JPS5885583 A JP S5885583A
Authority
JP
Japan
Prior art keywords
layer
semiconductor
laser
ion implantation
high resistivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18309181A
Other languages
Japanese (ja)
Other versions
JPS622719B2 (en
Inventor
Tadashi Fukuzawa
董 福沢
Nobutoshi Matsunaga
松永 信敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP18309181A priority Critical patent/JPS5885583A/en
Publication of JPS5885583A publication Critical patent/JPS5885583A/en
Publication of JPS622719B2 publication Critical patent/JPS622719B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region

Abstract

PURPOSE:To form a high specific resistance layer having preferable boundary surface and surface state and preferable electric characteristics by converting a semiconductor layer into a high specific resistance layer by ion implantation. CONSTITUTION:The first clad layer 2, n or p type or undoped active layer 3, the second clad layer 4 and a cap layer 5 are formed on a substrate 1, and a high specific resistance layer 6 is formed by oxygen ion implantation around the layer 5. A layer 7 for forming a circuit element forming region is formed on the layer 6, a source electrode 8, a gate electrode 9, a drain electrode 10, an insulating film 14 and metal electrodes 12, 13 are formed, thereby forming a field effect transistor. The respectively semiconductor layers of the semiconductor laser are formed of at least three types of elements of a group consisting of In, Ga Al, As, P and Sb.

Description

【発明の詳細な説明】 本発明は半導体レーザ装置の製造方法に関し、さらに詳
述す扛ば、発光領域を流れる電流を変調するための機能
回路素子を集積化した素子及び集積回路を具えた半導体
レーザ装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor laser device, and more particularly, the present invention relates to a method for manufacturing a semiconductor laser device, and more particularly, it relates to a semiconductor laser device having an integrated circuit device and an integrated circuit device for modulating a current flowing through a light emitting region. The present invention relates to a method for manufacturing a laser device.

を放出させ、それをグラスファイバーなどに導入させて
光通信に応用する提案等がなされている。
Proposals have been made to emit light and introduce it into glass fibers, etc., to apply it to optical communications.

従来この種の装置は、高比抵抗、或いは導電型半導体層
を、液相成長法、又は、熱拡散法等により形成されてい
た。しかし、上述の液相成長法などは、ドープ量の正確
な制御が困難であり、安定した高比抵抗層全形成するこ
とは難かしかった。
Conventionally, in this type of device, a high resistivity or conductive semiconductor layer has been formed by a liquid phase growth method, a thermal diffusion method, or the like. However, in the liquid phase growth method described above, it is difficult to accurately control the doping amount, and it is difficult to form a stable high resistivity layer in its entirety.

また、選択的に液相成長させると、他の半導体層との間
に互いに歪などの影響を与えたまま半導体層を形成する
こととなり出来上った素子を極めて電気的に劣化させる
欠点が存した。
In addition, selective liquid phase growth has the disadvantage that the semiconductor layer is formed with mutual effects such as strain on other semiconductor layers, resulting in extremely electrical deterioration of the completed device. did.

本発明の目的は、上記欠点の無い、簡単な構成で半導体
レーザ素子を機能デバイス回路等に使用するに適しfc
vR規な半導体レーザ装置の製造方法を提供することに
ある。
An object of the present invention is to provide a fc semiconductor laser device suitable for use in functional device circuits, etc., with a simple configuration and without the above-mentioned drawbacks.
An object of the present invention is to provide a method for manufacturing a vR-compliant semiconductor laser device.

上記目的を達成するための本発明の構成は、半導体基板
上に設けられた活性層上に、更に、半導体層を単層もし
くは複層形成する工程と、該層中に酸素又はA/元素を
選択的にイオン打込みを行なう工程と、上記イオン打込
みにより形成された高比抵抗層又は該層上に回路素子形
成領域を設ける工程とを有することにある。
The structure of the present invention for achieving the above object includes a step of further forming a single layer or a multilayer semiconductor layer on an active layer provided on a semiconductor substrate, and adding oxygen or A/element into the layer. The method includes the steps of selectively implanting ions, and providing a high resistivity layer formed by the ion implantation or a circuit element formation region on the layer.

本発明は、上述のように半導体層をイオン打込みにより
高比抵抗層に転化させることにより、界−2よび表面状
態が良好で電気的特性の良好な高比抵抗層が形成される
。すなわち、液相成長法など新規の層を逐次積上げて形
成するものと異なり、既存の半導体層を逐−徐々に高比
抵抗層に転化せしめていくので無理なく安定した層が得
られるわけである。引き絖いて、後の工程で素子形成領
域が形成される。この工程は800〜1000 ’cの
高温雰囲気中で行なわれるので、実質的なイオン打込み
後の熱処理工程と併用され、工程の簡素化に利点がある
。打込みエネルギーは800〜1500KeVで10”
 〜10”cm−2打込まれる。
In the present invention, by converting a semiconductor layer into a high resistivity layer by ion implantation as described above, a high resistivity layer having good field-2 and surface conditions and good electrical characteristics is formed. In other words, unlike methods such as liquid phase growth, which are formed by sequentially stacking new layers, existing semiconductor layers are gradually converted into a high resistivity layer, making it possible to easily obtain stable layers. . By drawing the wire, an element forming region will be formed in a later step. Since this process is carried out in a high temperature atmosphere of 800 to 1000'C, it is used in conjunction with a heat treatment process after substantial ion implantation, and has the advantage of simplifying the process. Implant energy is 800-1500KeV and 10”
~10”cm-2 is implanted.

この打込みエイ・ルギーは通常の導電型不純物全ドープ
する場合より、数倍高い。8o、0KeVに満たない場
合は充分高比抵抗層が得られず、また、15001(e
Vを越える場合は、却って半導体1−に欠陥を発生せし
め好ましくない。打込み深さは、所望の素子の大きさで
異なるが普通1〜5μmで活性層に到達しない深さで、
かつキャップ層より深く形成することが肝要である。
This implantation energy is several times higher than that in the case where all conductivity type impurities are doped. If it is less than 8o, 0KeV, a sufficiently high resistivity layer cannot be obtained, and if it is less than 15001 (e
If it exceeds V, it is not preferable because it may even cause defects in the semiconductor 1-. The implantation depth varies depending on the size of the desired element, but is usually 1 to 5 μm, a depth that does not reach the active layer.
It is also important to form the layer deeper than the cap layer.

また、打込みは予じめ所定のマスクを介して選択的に行
なってレーザの発光領域を回避させておくことが必要で
ある。前述したように、高エネルギーで打込むので深い
深さまで容易に高比抵抗層化ができる。また、表面から
、0.5〜0.6μmの処に打込んだ原子の濃度のピー
ク値を有する。こ:t′Ll−1:、所定の半導体層内
部に一層絶縁効果の高い領域を保有し、高比抵抗層を一
層効あるものとすると共に、表面、及びさらに深い半導
体層内の領域を多酸のドープによる結晶的破損がら未然
に阻止し得る効も併用している。これらの、打込み技術
は、通常のシリコン半導体装置等を形成する場合と、基
本的に同じものが使用され新らたに特別な付属装置など
を必要としないので極めて、答易な方法で電気的特性の
良好な半導体レーザが提供できる。
Further, it is necessary to perform the implantation selectively in advance through a predetermined mask to avoid the laser emission region. As mentioned above, since it is implanted with high energy, it is possible to easily form a high resistivity layer to a deep depth. Further, the peak concentration of the implanted atoms is 0.5 to 0.6 μm from the surface. This: t'Ll-1: has a region with a higher insulating effect inside a predetermined semiconductor layer, making the high resistivity layer even more effective, and increasing the surface and deeper regions within the semiconductor layer. It also has the effect of preventing crystal damage caused by acid doping. These implantation techniques are basically the same as those used to form ordinary silicon semiconductor devices, and do not require any new special accessory equipment, so they are extremely simple and easy to use for electrical implantation. A semiconductor laser with good characteristics can be provided.

このように、イオン打込みは、打込まれた半導体層を破
壊することなく極めて結晶的に安定に保持させfcまま
高比抵抗層を形成するので、この打込み層内に他の半導
体元素を打込んで素子形成領域の形成全OJ′能ならし
める。また、この打込み層は表面も安定した状態で傅ら
nるので結晶の整合性がよく、該層上に他の半導体層を
形成してもこの半導体層は完全な結晶性が得られ、この
半導体層を素子形成領域としての使用を可能ならしめる
In this way, ion implantation maintains the implanted semiconductor layer in an extremely stable crystalline manner without destroying it, forming a high resistivity layer with fc intact, so it is possible to implant other semiconductor elements into this implanted layer. The full OJ' capability for forming the element formation region is achieved by the following steps. In addition, this implanted layer has a stable surface, so the crystal consistency is good, and even if another semiconductor layer is formed on this layer, this semiconductor layer will have perfect crystallinity. A semiconductor layer can be used as an element formation region.

上述のように、極めて絶縁体に近い高比抵抗層が上記半
導体層中に形成させることによりレーザ゛ハなどの発光
素子部分と、回路部分とが分離さ扛、イ の電流は特定の領域に集中しレーザ素子における電流閉
じ込め効果を有し、動作電流の効率化を促すとともに、
レーザ素子と能動回路とを絶縁分離する。この絶縁分離
は導電型不純物とは異なる元素がイオン打込みによシ半
導体層中に打込まれてなどの化合物半導体層などに、酸
素イオンなどをイオン打込みにより打込んで形成される
。イオン源としては上記酸素、A/などの他にも打込み
後に変化しないものであれば適宜目的により用いられる
。が打込み後の熱処理によシ低比抵抗にならないことが
肝要である。この意味で酸素、A/等が好ましい。上記
高比抵抗層は、前述のようにレーザ素子部分と回路素子
部分とが分離されればよいが、レーザの活性層の深さよ
りは浅く、クラッド層よりは深いことが望ましい。この
方が動作電流が活性層に到達するまでに拡がらずに有効
活用ができ、かつ、打込による結晶性の低下が活性層に
及ぶCとなく岨流狭搾の効果がより商めら扛る。
As mentioned above, by forming a high resistivity layer that is very close to an insulator in the semiconductor layer, the light emitting element part such as a laser diode is separated from the circuit part, and the current flows to a specific region. It has a concentrated current confinement effect in the laser element, promotes efficiency of operating current, and
The laser element and the active circuit are insulated and separated. This insulation isolation is formed by implanting oxygen ions or the like into a compound semiconductor layer or the like in which an element different from a conductivity type impurity is implanted into a semiconductor layer by ion implantation. As the ion source, in addition to the above-mentioned oxygen and A/2, any ion source that does not change after implantation may be used depending on the purpose. It is important that the resistivity does not become low due to heat treatment after implantation. In this sense, oxygen, A/, etc. are preferred. The high resistivity layer may have a depth that is shallower than the active layer of the laser and deeper than the cladding layer, although it is sufficient that the laser element portion and the circuit element portion are separated as described above. In this way, the operating current can be used effectively without spreading before it reaches the active layer, and the effect of narrowing the current can be more effectively used without the crystallinity decreasing due to implantation reaching the active layer. Ru.

−J7C1半導体材料としてu、In 、 Ga 、 
AI!、 AsP、およびsbからなる群のうち少く共
3種類を構成元素とすることが肝要である。これらはヘ
テ図である。レーザ光の進行方向に垂直な面での断面図
を示している。
-J7C1 semiconductor materials include u, In, Ga,
AI! It is important that the constituent elements be at least three of the group consisting of , AsP, and sb. These are Hete diagrams. A cross-sectional view taken in a plane perpendicular to the traveling direction of laser light is shown.

n −G a A S基板1上に、公知の液相成長技術
で、0.3)なる活性層3と、該層3上に厚さ1〜3μ
mのp−(ja、−、A7j、As  (0,2≦Z≦
0.7)なる第2タラツドノー4と、該層4上に厚さ0
.1〜0.7μmのp −G a A sなるキャップ
層5とが形成される。このキャップ層5の囲りに高比抵
抗層6がたとえば酸素のイオン打込みにより形成される
An active layer 3 with a thickness of 0.3) is formed on the n-Ga A S substrate 1 by a known liquid phase growth technique, and a layer 3 with a thickness of 1 to 3 μm is formed on the layer 3.
p-(ja, -, A7j, As (0,2≦Z≦
0.7) and a second layer 4 with a thickness of 0.
.. A cap layer 5 of p-GaAs having a thickness of 1 to 0.7 μm is formed. A high resistivity layer 6 is formed around this cap layer 5 by, for example, oxygen ion implantation.

−レーザの既その発光領域を示す。レーザの横モード制
御のために、図のように上記基板1に予じめ断面が逆台
形状の窪味(溝)が設けられてあってもよい。上記レー
ザ素子領域に並置して上記高比抵抗層6上に後述する方
法により形成された回路集子形成領域を形成するn −
G a A s層7が設けら詐ている。該領域7上もし
くは領域7内に、公知の製造手段;C,1ニジ回路機能
素子が形成される。例えば、図の如く、ソース電極8、
ゲート電極9、ドレイン電極10、絶縁膜14、そして
金属電極12および13を設けて電界効果型のトランジ
スタが構成されている。第2図は上記第1図の概略上面
図である。上記金属配線12は、上記レーザの電極部1
1と接続されている。一方、上記FETのソース電極8
に接続されている。上記ゲート電極9は上記ドレイン′
11を極10に接続している電極13を割って中間をゲ
ート用ポンディングパッド16と接続されている。これ
ら、電極12.13および16の形態、形状は回路素子
や使用目的により適宜変化が可能である。次いで本発明
の製造方法について述べる。
- indicates the existing emission area of the laser; In order to control the transverse mode of the laser, a recess (groove) having an inverted trapezoidal cross section may be provided in advance in the substrate 1 as shown in the figure. A circuit assembly forming region is formed on the high resistivity layer 6 by a method described later in parallel to the laser element region.
The GaAs layer 7 is not provided. On or within the region 7, a C, 1 circuit functional element is formed by known manufacturing means. For example, as shown in the figure, the source electrode 8,
A field effect transistor is constructed by providing a gate electrode 9, a drain electrode 10, an insulating film 14, and metal electrodes 12 and 13. FIG. 2 is a schematic top view of FIG. 1 above. The metal wiring 12 is the electrode part 1 of the laser.
1 is connected. On the other hand, the source electrode 8 of the FET
It is connected to the. The gate electrode 9 is the drain′
The electrode 13 connecting the electrode 11 to the pole 10 is divided and the intermediate portion is connected to a gate bonding pad 16. The form and shape of these electrodes 12, 13 and 16 can be changed as appropriate depending on the circuit element and purpose of use. Next, the manufacturing method of the present invention will be described.

半導不レーザの各半導体Jf12,3.4および5Te
を0.5mgに調整することによシ得らnる。
Each semiconductor Jf12, 3.4 and 5Te of semiconductor non-laser
It was obtained by adjusting the amount to 0.5 mg.

また、活性層3は、G’aを6g、GaAs((400
mg、そしてA/を2mgに、クラッド層4は、Gaf
6g、GaAsを400mg、AI!を10mg % 
そしてZnを30mgに、さらにまた、キャップ層5は
、Cx a f 5 g 、  (J a A S f
 400 ” LそしてZn f 30 m g VC
a周整することによシ得られる。
In addition, the active layer 3 contains 6 g of G'a and GaAs ((400
mg, and A/ is 2 mg, and the cladding layer 4 is made of Gaf.
6g, 400mg of GaAs, AI! 10mg%
Then, Zn is added to 30 mg, and the cap layer 5 is made of Cx a f 5 g , (J a A S f
400” L and Zn f 30 mg VC
It can be obtained by adjusting the a.

第3図に示す如く、ストライプ状の溝(深さ0.5〜5
μm)18’i有するn型GaAs#!−導体基板上に
説明した如き半導体層2〜5全成長せしめる。各層の厚
みは前に述べた通りである。
As shown in Figure 3, striped grooves (depth 0.5-5
μm) n-type GaAs with 18'i #! - Full growth of semiconductor layers 2 to 5 as described above on a conductor substrate. The thickness of each layer is as described above.

レーザ発振せしめる領域の上部(これは上述の溝の部分
に対応している)にフォトレジスト等でイオン打込み用
マスク17を帯状に形成する。
An ion implantation mask 17 is formed in a band shape using photoresist or the like above the region where laser oscillation is to be performed (this corresponds to the above-mentioned groove portion).

第4図に示す如くイオン打込用マスク17を介し、B 
00 KeV、 深さ0.5〜2μmテ酸素イオ/21
を打込み、高比抵抗層6を形成する。次いで、第5図に
示したように、マスク17i除去後、n−GaAs層7
f、厚さ0.2〜5μmQ相成長法で作製する。通常の
化学食刻法を用いて1=’ E Tを形成する部分のみ
n −G a A s層7を残す。レーザ素子部に対応
する領域上は、p −G a A s層5が露出する(
第6図)。こうして準備された半導体基体表面全面に厚
すO15/!7rrl)SiO□膜14f:CVD法で
形成し、更にソースおよびドレインに対応する箇所の5
in2膜を選択的に除去する。第7図がこの状態である
。この除去された箇所にA u −Ge−Niを蒸着し
、所定形状にパターニングののち、アロイ化し電極8,
10を形成する。次いで、前記第1図に示した如く、レ
ーザ電極部に対応するSin!膜を開口し、レーザ電極
部、及びゲート電極部分K T i 、 Cr、 Au
を積層して蒸着し所定の金属パターンを形成する。基板
結晶の裏面を研磨し、100μm程度まで薄くした後、
n側を極18としてAu−8nを蒸着後、素子を分離し
、ボンディングを行なう。このようにして、能動回路を
具なえた半導体レーザ装置が形成さnる。第1図がこの
完成図である。
As shown in FIG. 4, through the ion implantation mask 17,
00 KeV, depth 0.5-2 μm te oxygen io/21
is implanted to form a high resistivity layer 6. Next, as shown in FIG. 5, after removing the mask 17i, the n-GaAs layer 7 is removed.
f, thickness 0.2 to 5 μm manufactured by Q phase growth method. Using an ordinary chemical etching method, the n-GaAs layer 7 is left only in the portion where 1='ET is to be formed. The p-GaAs layer 5 is exposed on the region corresponding to the laser element part (
Figure 6). A thickness of O15/! is applied to the entire surface of the semiconductor substrate thus prepared. 7rrl) SiO□ film 14f: Formed by CVD method, and 5
Selectively remove the in2 film. FIG. 7 shows this state. Au-Ge-Ni is deposited on the removed portion, patterned into a predetermined shape, and then alloyed to form the electrode 8,
form 10. Next, as shown in FIG. 1, the Sin! corresponding to the laser electrode section is formed. The film is opened and the laser electrode part and gate electrode part K T i , Cr, Au
are laminated and vapor-deposited to form a predetermined metal pattern. After polishing the back side of the substrate crystal and making it thin to about 100 μm,
After Au-8n is evaporated with the n side as the pole 18, the elements are separated and bonded. In this way, a semiconductor laser device equipped with an active circuit is formed. Figure 1 shows this completed drawing.

を第8〜9図を用いて説明する。第8図でけレーザ奪1
者造作成後、酸素イオン打込みの時800〜1.500
KeVO高エネルギーで打込み同図布に示すように表面
では酸素濃には比較的低く、表面から0.5〜0.6μ
mのところにピークを持つプルファイル全形成する。こ
の時ピーク付近の酸素濃度゛;T十分尚くレーザとに’
 E’1”の分離は完全に行なわ屓、かつ表面付近の酸
素濃度は十分に低くここに1作られる1!” ETの特
性は損なわれない。さらにこ(11) の上に第9図に示す如(SiあるいはSeをSiならば
75〜10 QKeV、 5 x 10” 〜5 xl
 012cm−2S eは250〜300KeV5xl
O”〜5X1012crn−2打込みFETなどOXX
影形成用活性層19を形成する。この時81あるいは同
じ方法により形成されるので説明を省略する。
will be explained using FIGS. 8 and 9. Figure 8 Deke Laser Robbery 1
800 to 1.500 when implanting oxygen ions after artificial creation
KeVO is implanted with high energy, and as shown in the figure, the oxygen concentration is relatively low at the surface, and the oxygen concentration is 0.5 to 0.6μ from the surface.
A complete pull file with a peak at m is formed. At this time, the oxygen concentration near the peak ゛;T is sufficient for the laser.
E'1'' is completely separated, and the oxygen concentration near the surface is sufficiently low that the properties of 1!'' ET produced here are not impaired. Furthermore, on top of this (11) as shown in Figure 9 (if Si or Se is Si, 75 to 10 QKeV, 5 x 10" to 5
012cm-2S e is 250-300KeV5xl
O''~5X1012crn-2 implant FET etc. OXX
A shadow forming active layer 19 is formed. At this time, since it is formed by 81 or the same method, the explanation will be omitted.

実施例 2 本発明は、前述の実施例の説明で述べたG a A 5
−GaA、/As系の半導体以外にも適用でき、高速変
調特性の優れた半導体レーザを得ることができる。以下
説明するが、便宜的に前記実施例における第1図を用い
ることとする。構成組材が異なるだけで作用、効果等は
全く同様であるためである。
Example 2 The present invention is based on the G a A 5 described in the description of the above embodiments.
- It can be applied to semiconductors other than GaA and /As-based semiconductors, and a semiconductor laser with excellent high-speed modulation characteristics can be obtained. In the following explanation, for convenience, FIG. 1 in the above embodiment will be used. This is because the functions, effects, etc. are exactly the same, only the constituent materials are different.

n型InP基板1上に、n型InP層2(厚さ1μm)
、アンドープj n o4s Ga 、、 A s o
、asPo、、7 レーザ活性層3(厚さ0.1μm)
、p型(12) InP 4 (厚さ1.5μm[一液相成長法で作成し
、皐2クラッド層4とキャップノー鑓同−物として+; いる。7として、n型InP)!e用いた。波長1.6
μmでレーザ発振し、2.5 GHzで変調することが
できた。
On n-type InP substrate 1, n-type InP layer 2 (thickness 1 μm)
, undoped j no4s Ga ,, A so
, asPo,, 7 Laser active layer 3 (thickness 0.1 μm)
, p-type (12) InP 4 (thickness 1.5 μm [created by single-liquid phase growth method, as the same material as the cladding layer 4 with no cap; 7, n-type InP)! e was used. Wavelength 1.6
Laser oscillation was possible at μm and modulation at 2.5 GHz.

実施例 3 n 型1 n P基板1上に、n型I rl+)、52
 A / (1,4gAs112(厚さ1.0μm)、
n型1 n o 、s B Ga o 、47As層3
(厚さ0.12μm)、p型’ nO,!12 ”’0
.48As層4(厚さ1.0μm)を高真空中で、分子
線エピタキシャル法で成長せしめる。次いで、ウェー−
へ−’に真空中から取り出すことなく、酸素イオンのビ
ームで選択的にパターンを描き、実施例1で示した高比
抵抗領域6金形成した。この方式はフォトレジストを用
いることなく、直接イオン打込によりパターン形成がo
J能である。
Example 3 On the n-type 1 n P substrate 1, the n-type I rl+), 52
A/(1.4gAs112 (thickness 1.0μm),
n-type 1 no, s B Ga o, 47As layer 3
(thickness 0.12 μm), p-type 'nO,! 12”'0
.. A 48As layer 4 (thickness: 1.0 μm) is grown by molecular beam epitaxial method in a high vacuum. Next, the wave
Without taking it out of the vacuum, a pattern was selectively drawn with an oxygen ion beam to form the high resistivity region 6 gold shown in Example 1. This method allows pattern formation by direct ion implantation without using photoresist.
It is J-Noh.

イオン打込後、σらに分子線エピタキシャル法により、
IIn型1n O,ff13 (J ao、47 A 
S J@ 0.21t In f成(13) 長させ、7で示したFETの能動層とする。以下は、実
施例1と同じ方法で作製できるので説明を省略する。
After ion implantation, using molecular beam epitaxial method,
IIn type 1n O, ff13 (J ao, 47 A
S J @ 0.21t In f formation (13) is made long and used as the active layer of the FET shown in 7. The following description can be omitted since it can be manufactured by the same method as in Example 1.

以上詳述したように、本発明はレーザ素子の傍の高比抵
抗層を画エネルギーのイオン打込みにより形成して、該
素子を回路素子から電気的に分離すると共に電流狭搾を
行なわしめた点電気的特性の良好なコンパクトな集積回
路を具えた半導体レーザ装置を提供でき、工業的利益大
なるものである。
As detailed above, the present invention is characterized in that a high resistivity layer near the laser element is formed by ion implantation with image energy to electrically isolate the element from the circuit elements and to narrow the current. It is possible to provide a semiconductor laser device equipped with a compact integrated circuit with good electrical characteristics, which is of great industrial benefit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を使用して形成した半導体レート・・基
板、2・・・第1クラッド層、3・・・活性層、4・・
・第2クラッド層、5・・・キャップ層、6・・・高比
抵抗層、7・・・n型FE T’活性層、8・・・ソー
ス、9・・・ゲート、10・・・ドレイン、12および
13・・・導電(14) 配線層、14・・・絶縁膜、15・・・発光領域。 特訂出y;1人 (15) \)        ■\  N 第 乙  図 菖  g  団 第 q 図
FIG. 1 shows semiconductor layers formed using the present invention: substrate, 2... first cladding layer, 3... active layer, 4...
- Second cladding layer, 5... Cap layer, 6... High specific resistance layer, 7... N-type FET' active layer, 8... Source, 9... Gate, 10... Drain, 12 and 13... Conductive (14) wiring layer, 14... Insulating film, 15... Light emitting region. Special edition y; 1 person (15) \) ■\ N No. 2 Iris illustration g Group No. q fig.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板上にレーザ発光せしめるための活性層を
含む複数の半導体層を形成する工程と、前記複数の半導
体層中の所定個所にイオン打込み法によって高比抵抗領
域を形成する工程と、少なくとも前記高比抵抗領域上に
半導体層を設ける工程と、この半導体層中に少なくとも
回路で低濃度であり、該高比抵抗領域内に濃度のピーク
を有する如き不純物濃度分布を有せしめることを特徴と
する半導体レーザ装置の製造方法。
1. A step of forming a plurality of semiconductor layers including an active layer for laser emission on a semiconductor substrate, a step of forming a high resistivity region at a predetermined location in the plurality of semiconductor layers by an ion implantation method, and at least A step of providing a semiconductor layer on the high resistivity region, and providing the semiconductor layer with an impurity concentration distribution having a low concentration at least in the circuit and having a concentration peak within the high resistivity region. A method for manufacturing a semiconductor laser device.
JP18309181A 1981-11-17 1981-11-17 Manufacture of semiconductor laser Granted JPS5885583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18309181A JPS5885583A (en) 1981-11-17 1981-11-17 Manufacture of semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18309181A JPS5885583A (en) 1981-11-17 1981-11-17 Manufacture of semiconductor laser

Publications (2)

Publication Number Publication Date
JPS5885583A true JPS5885583A (en) 1983-05-21
JPS622719B2 JPS622719B2 (en) 1987-01-21

Family

ID=16129595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18309181A Granted JPS5885583A (en) 1981-11-17 1981-11-17 Manufacture of semiconductor laser

Country Status (1)

Country Link
JP (1) JPS5885583A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951586A (en) * 1982-09-17 1984-03-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS59188377A (en) * 1983-04-08 1984-10-25 Mitsubishi Electric Corp Controlling method of pulse width modulation type voltage inverter
JPH01196888A (en) * 1988-02-02 1989-08-08 Matsushita Electric Ind Co Ltd Optical integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951586A (en) * 1982-09-17 1984-03-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS59188377A (en) * 1983-04-08 1984-10-25 Mitsubishi Electric Corp Controlling method of pulse width modulation type voltage inverter
JPH01196888A (en) * 1988-02-02 1989-08-08 Matsushita Electric Ind Co Ltd Optical integrated circuit

Also Published As

Publication number Publication date
JPS622719B2 (en) 1987-01-21

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