JPS588344A - デ−タ転送方式 - Google Patents

デ−タ転送方式

Info

Publication number
JPS588344A
JPS588344A JP10650881A JP10650881A JPS588344A JP S588344 A JPS588344 A JP S588344A JP 10650881 A JP10650881 A JP 10650881A JP 10650881 A JP10650881 A JP 10650881A JP S588344 A JPS588344 A JP S588344A
Authority
JP
Japan
Prior art keywords
data
signal
fifo
data transfer
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10650881A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0160862B2 (enrdf_load_html_response
Inventor
Kazutoshi Michioka
道岡　和俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10650881A priority Critical patent/JPS588344A/ja
Publication of JPS588344A publication Critical patent/JPS588344A/ja
Publication of JPH0160862B2 publication Critical patent/JPH0160862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
JP10650881A 1981-07-08 1981-07-08 デ−タ転送方式 Granted JPS588344A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10650881A JPS588344A (ja) 1981-07-08 1981-07-08 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10650881A JPS588344A (ja) 1981-07-08 1981-07-08 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS588344A true JPS588344A (ja) 1983-01-18
JPH0160862B2 JPH0160862B2 (enrdf_load_html_response) 1989-12-26

Family

ID=14435362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10650881A Granted JPS588344A (ja) 1981-07-08 1981-07-08 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS588344A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPH0160862B2 (enrdf_load_html_response) 1989-12-26

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