JPS5880733A - Data transfer device - Google Patents

Abstract

PURPOSE:To perform the transfer of data with high reliability through a simple constitution, by adding microcomputers to the main body of a copying machine and its accessory device to perform the parallel-serial and serial-parallel conversions and therefore enabling the mutual serial transfer of data between the copying machine and its accessory device. CONSTITUTION:A microcomputer 21 of master side and a microcomputer 31 of slave side are provided to a transmitting/receiving part 20 for main body of a copying machine and a transmitting/receiving part 30 for accessory device respectively. Then the serial-parallel and parallel-serial converting functions of data are added to the computers 21 and 31 respectively. The master/slave side is set by the switches 22 and 32 connected to a port R4 of the computers 21 and 31 respectively. Then the data given from an input terminal IN1 is read into the computer 21 and then converted into a serial data to be transferred to the computer 31 through an antenna ANT. This serial data is then converted into a parallel data and delivered to an output terminal OUT2. The data of an input terminal IN2 is converted into a serial data by the computer 31 to be transferred serially to the computer 21 and then converted into a parallel data to be delivered to an output terminal OUT1.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a data transfer device that mutually exchanges data.

In general, in a copying machine that improves operability and precisely controls copy quality, data transfer is performed to exchange various data between the copying machine itself and an additional device equipped with a sorter, human power sensor, etc. The equipment is safe. This conventional data transfer device includes a central processing unit (1) (CPIJ) /2, an I10 controller /
3, Output driver/ri, Input interface/j,
It has a power supply circuit/6 for the CPU and a power supply circuit 77 for the additional device.

Additional equipment ff(, n includes sequence controller/wa, input interface A, output driver 2/A.

An output load 22A and an input sensor 23Af are provided, and a flat cable, for example, consisting of a number of connecting wires corresponding to each Yuzugo is used for mutual data transfer.

The input interface 15 of the copying machine main body // and the input interface of the additional device /g,! 17 A&j.
, Kt. As a measure to prevent f, it is also possible to use a photo-caggler as shown in FIG. but,
In any case, as the number of IVI signals to be transferred increases, the number of connector bins also increases, which not only increases the cost of connector cables, but also causes deterioration in device reliability. ing. Also, Universal Asynchronous Receiver Transmitter (UAR'l'
), and the transmission rate is lθ. - Data that can be serially transferred at about 2DK (focus per second) (31) There are transfer devices, but although they have versatility, there are many differences as data transfer devices between the copier itself and its attached devices. In order to eliminate the above-mentioned drawbacks, the purpose of the invention is to provide a data transfer device that can be easily applied to existing copying machines by installing a microcomputer (kbitf) for serial data transfer in the main body of the copying machine and its additional devices. It is about providing.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing an example of the configuration of the main parts of the data transfer device according to the present invention. This data transfer device includes
Compatible transmitter/receiver units and 3θ are provided in the copier main body and additional devices, respectively. The transmitting/receiving section〃, 3θ is mounted on one printed circuit board, and the seven microcomputers 2/,
It incorporates a J/ and an interface circuit. And the transmitter/receiver section〃.

The transmission line that couples the 3θ signals includes a connection line that connects mutual antenna terminals and a common ground.

Therefore, in implementation, a single connection line can be used as a transmission line.

The microcomputers IX2/ and J/ have the functions of serial-parallel and parallel-serial conversion of data, and the master/stub settings are made with switches n and 32 connected to the Rμ boat. In the case shown in FIG. 0, the microcomputer 21 of the transmitting/receiving section for the main body of the copying machine is a replica of the microcomputer 31 of the transmitting/receiving section 3θ for the master/additional device. The microcomputer, 2/, 3/ has a power terminal Wee, a ground terminal Vss and a control terminal RT.
EX,
An oscillation oscillator is connected to X, and oscillates a tarok pulse of, for example, 2 MHz. By the way, as the microcomputers 2/ and 3/, for example, a microprocessor having a ROM (read only memory) and a RAM (random access memory) housed in a single chip can be used.

In this data transfer device, the terminal P of the transmitting/receiving section is now
When data is supplied from the copier main body to the input terminal IN/ consisting of /13 to P/24t, the data is sent to the amplifier 2.
3.20 is amplified and the R2 port is connected to the microcomputer 2/
The data is read in, converted into serial data, and transmitted from the baud R/ to the transmitter/receiver section 3θ via the antenna terminal ANTi. This transmitting/receiving section 3θ has an antenna terminal ANT'(j
The serial data is received and input to the R/board of the microcomputer 3/. The microcomputer 31 converts the serial data into parallel data, and
Boat repair P All terminals of the boat are all valved and amplifiers 33, 3 are installed.
41. And amplifier 33. :Fil, amplify the parallel data and transfer it to the output terminal OU'l' consisting of terminals P2O1-P2/2.

Similarly, when the slave-side transmitter/receiver 3θ transmits the master-side transmitter/receiver data, the data input to the input terminal IN2 consisting of additional devices or terminals P273 to P2≠, the amplifiers 35, 36 , microcomputer 3/, antenna terminal ANT, microcomputer〃, amplifier B, and terminal P10/- through it.
It can be transferred (j) to the output terminal OUT/ consisting of P//2. In this case, microcomputer 3
/ performs parallel TU column conversion of data, and the microcomputer 21 performs serial/parallel conversion of data. In this way, the transmitter/receiver section 3θ can perform bidirectional data transfer.

3 is a signal waveform diagram showing an example of a communication format applied to the data transfer device of FIG. 3. FIG.

The microcomputer 31 executes l/stenf from step 1 to step 0 as shown in the figure.
Frame data transfer can be performed. Step ■
, ■, the microcomputer 2 on the master side
The microcomputer 31 on the 1-slave side performs transfer long synchronization 1tlJNk. Therefore, the microcomputer 1 starts from step ■ in which the transmission line is open, so that the bit O of the l frame is @ln.
Start Stella 1 ■ by going from 10'' to '
Period consisting of g bits as / to I'A8! The transfer of M is transferred to the microcomputer 31.

(6) During this period, the microcomputer 31 activates the rising edge area i'ASK,2 of the O focus, and determines the period TM i bit θ of the transfer long pulse sent from the master side.
The average of the long period (+rf'rs k is determined by adding up g times of ~7), is processed and transferred, and is sent back to the microcomputer 2/ with the focus r~/S in step (2).Then, the microcomputer 2/Its, , it is checked whether the long transfer period TM and the average value T8 are equal.If TM\TS, communication with the microcomputer 31 will not be possible, so the transmission line is set to 0 at focus 16 in step (2). ” and informs the microcomputer 31.

However, if TM=TS, the microcomputer λ
/ to 1, step ■ to focus 17"O", TAS
Start running K-Hiro. The microcomputer 2/ starts counting transfer longs from the focus 17 in step (3).

At the next step (■, ■), the microcomputer 2/ executes TASKJ and first transfers the 72-pinto serial data consisting of the focus 7g-〃 to the microcomputer 3/, and then the focus 3θ~ 32
A check bit consisting of three pins is transmitted. Among these check bits, the focus 3θ may be an even parity focus, but in this example, the complement of the previous focus is set to 0, and the distinction between the focus 29 and the focus 3θ is made clear. ing. The focus 31 in the check focus is centered depending on the content of the data.
) is the same value as the focus B, which is the focus of the 7th point of the /2 focus data.
The check focus of the focus 32 is set to 0'' to represent the final focus, and at the end of this focus 3, the transmission line is fully opened.

Microcomputer I performs steps ■~■'
While executing l'A8KJ, microcomputer 3 transfers and reads fc data 11AsK-
In this way, the microcomputer 2/ converts the parallel data supplied to the terminals P//3 to P/241 of the transmitter/receiver section into out-of-plane data, and sends the data to the antenna terminal ANT. The data is sent to the transmission line via the microphone P converter 3, and the 1st column data is received, converted to parallel data again, and sent to the terminals P20/-P and Z/2 of the transmitting/receiving section is 3θ, respectively. supply. Therefore, the terminal P//2 at the input terminal IN/ of the transmitting/receiving section
The data supplied to ~P/21/- is the symptom of the output terminal OUT 2 of the transmitting/receiving section 3θ, and the data supplied to the -4'- terminal P20/
-P, 2/, and 2, respectively.

By the way, in step (2), the microcomputers 2/ and 3/ switch the transmission/reception mode and prepare to change the data transmission direction. Then, in step 12, the microcomputer 31 on the slave side sets the focus point to "o" and starts counting the number of long transfers in order to start transmitting data. The microcomputer 3 fly has already made a long transfer synchronized sound in steps ゛■ and ■, so it has a long transfer period TM in step ■! 2 pinto serial data (pinto 3
5 to 6) f It is possible to sequentially transmit the data to the microcomputer 21.

(ri) Also, in step @, the microcomputer 31
is sent to the check bits of 3 pins (pins 37 to M) k to the microcomputer 2 in the same manner as in step (2).

Thus, while microcomputer 3 is executing 1'kSK3 to send data, microcomputer 21 is executing 1'ASK to receive that data.
Execute step 4'. Therefore, the data supplied to the terminals P2/3 to P, 2.2μ at the input terminal IN2 of the transmitter/receiver 16 is supplied to the corresponding terminals P101-P//2 of the output terminal QUIP/ of the transmitter/receiver 16 section. can do. In step-0, the microcomputer 2/...? / also turns on the transmission line and becomes 'I'ASKO, which waits for the start of step 1 of the next data transfer frame.

FIG. 5 is a block diagram showing the configuration of the main parts of the microcomputers 1 and 31. microcomputer 2
/, 3/ are discount I memories respectively? ? 1S j/%I
tAM (random access memory) 1% j-2%
@74 Logic unit 33 work accumulator j4! have. Here, the ROM of the control storage unit jl
(Read (10) only memory) stores microinstructions and information necessary for controlling data transfer lock cycles and the like. The decoder DCR decodes the data read from the ROM, and the tourogram counter PC decodes the address of the ROM. Also, stack STK is, for example, LI
A series of registers used in a FO (last in first out) format. .

Next, the ItAM section S2 consists of a plurality of memory areas, and the addresses thereof are designated as X and Y address registers. Among the plurality of memory areas, RAM / stores data supplied to input terminal IN/ or input terminal IN,2,
RAM 2 is output terminal OU'1'/or output terminal O
UI! 2. Store data to be supplied to 2. And R.A.
M3 is a memory area for storing serial input data transmitted from the other party's computer to the [t/port] via the antenna terminal AN'I'i. In addition to this,
RAM i 5/ has an interrupt counter that increments by 10 l when there is a timer interrupt, a memory area for storing the transfer lock period TM, a memory area for storing the measured transfer lock period T8, and input/output. There is a memory area that stores all data management numbers.

Next, the flowchart of the main program in Figure 6,
The operation of this data transfer device will be described with reference to the subroutine flowcharts shown in FIGS.

When power is supplied to the microcomputer 2/11 and initialization is performed by the reset signal, the main program shown in FIG. , in the next step 62 the subroutine "IODA'
l'A'" is executed. This subroutine "IO
DA' and l'A'' are microcomputer 2, respectively.
/, J/, reads the input information of input terminal IN/, IN, 2 into RAM/, input terminal, output terminal OUT/,
This is a routine that supplies output information read from ItAM to OU'l'', 2. In step 63,
The lock period TM is transferred to , and the interrupt counter is activated.

The transfer lock period TM is...as described in 1, ft0M
The 0 interrupt counter, which is written in and determines the data serial transmission speed, increments its contents by +l every time a timer interrupt occurs.

In step A≠, the microcomputer 2/,
3/ to determine whether it is a master or a slave. Then, since the microcomputer 2/ is the master and the microcomputer 3/ is the slave, the process moves to the next step and the subroutine is executed at step 6≠.
ASI(/”, Step “66 The Blue Ten''l!
A8K, z'' is executed. Therefore, the microcomputer 27 &'f, , the cycle 'I'Mtehit 0
The r bits from bit 7 to bit 7 are used to send the transfer lock pulse to all transmission lines, and the microcomputer 3/
measures the transfer lock period (see step ■ in Figure q). Next, the microcomputer 3/ returns a transfer lock pulse from the bin f to the focus 7S based on the measured transfer lock circumference MT8, and the microcomputer 21 receives the transfer lock pulse (see Fig. (See step ■).

(13) In this way, microcomputers 2/ and 3/ perform synchronous control of the transfer lock cycle. As a result, mutual communication is possible within the clock period TM F' TS. This determination is made in the subroutine "EI'LROR" at step 67, and the clock cycle is "1" M.
(If it becomes 'I', input "/" into the error flag register. The microcomputer 2/ judges whether this error flag is @t l+ in step 6r, and if the error flag is ln, , step 6
Then, the error flag register is reset and the process returns to step 62. However, if the error flag is 10'', control is transferred to the next step 70.

Here, if the error flag becomes ``l'', the microcomputer 2/ will lower the transmission line to 60'' and the microcomputer 3/
/ Notify. However, if an abnormality occurs in the microcomputer 3/ and the transfer lock cycle cannot be measured,
It is detected in the subroutine "martoa", the error flag register becomes "l", and the transmission line also becomes "o".

Now, in step 7θ, it is determined whether the microcomputers 2/ and 3/ are masters or slaves again.
TASKJ" and "TAsxg" are executed in steps 7/72, and at the same time, the slave microcomputer 31 executes subroutine "f'A8.
4'”.

” TASKJN is executed in steps 73 and 717.

That is, the microcomputer 21 first sets the transmission line to 60" at step 1 in the figure, then performs steps
Transfers the serial data of the focus, and transfers the check focus of the 3 points at the focus 3θ to 32. At this time, the microcomputer 3/ enters the data reception operation at step "■, and receives the 72-bit data at steps ■ and ■. Read serial data and 3-bit check focus.

In this way, the microcomputer 2/ executes the subroutine "TASIU", and the microcomputer 31 executes the subroutine "TASK≠".

Then, the transmission line is opened at step ■ in the figure, and once again (the microcomputer 31 beeps), the subroutine from step ■ to [phase], which includes data transmission over 311-F9, is executed. ?” and at the same time executes the microcomputer 2 subroutine “TASKg 'i.Microcomputer 2/.

31 completes the subroutine "I'A8 TA8KJ" in steps 72 and 74L, respectively, control is transferred to step 62 for the next data transfer.

The steps of the main program are as described above, and each of its subroutines will be sequentially explained next.

First, in the subroutine "IODATA", 31 on the microcomputer side is the data management number θ~/l
According to the input data 'i TtAM /,
An operation of reading output data from ILAM 2 is performed.

Therefore, as shown in the flowchart in Figure 7,
When the subroutine "IODA'I'A" is called,
The data management number is cleared in step 7♂l, the input data is imported into ILAM / in steps 12 to 6, the management number is cleared again in step 7, and then the data management number is cleared in steps II to 2. Output data is read from RAM 2. That is, in steps and 2, for example, input terminals P//3 to
Data management number assigned to each P/217''
The input data is checked according to the values o" to "//". Then, for example, if the data of the input terminal P/13 with the data management number "O" is set to 1 or ON, step The process branches to t3 or step g≠, and the input data is written to the location of RAM / corresponding to the data management number +IO11.

In the next step gj, the data management number is incremented by 10I, and the data management number becomes 0''.
Since "/"K becomes "/", the management number becomes /2 in step r6.
``Check is ``No'', and step ''
Control is returned to r2.

Similarly, the input data is RA according to the data management number.
The data management number is "/2" (
12) Since the check in step r6 becomes ``YES'', the control is transferred to step 7. In step II-92, the output data read from itAM, 2 is read out according to the data management number. , for example, is distributed to the output terminals P10/~P//2 of the transmitting/receiving section, but the control is essentially the same as steps f, 2~t6. In step 63 of the program, as mentioned above, R
It is transferred to AM and the long period TM is sent,
Interrupt counters are enabled. When this interrupt counter receives a timer interrupt, the interrupt routine shown in FIG. 3 is called and steps 10/-/θ3 are executed. That is, each time an interrupt occurs, the contents of the interrupt counter are incremented, and when the interrupt counter overflows, the error flag register is set.

The microcomputer 21 executes the subroutine "'l'A8/" at step 6j of the main program.
f Execute. FIGS. 2 to 72 are flowcharts of the subroutine / /F 1 ``'I'A8''. Subroutine ``I'A8/''? 11", the microcomputer 2/+X sends out a transfer lock pulse with a period of 〒M consisting of repeated edges of "O" and "L" to the transmission line via the antenna terminal AN1, and then
The period T8 of the transfer lock pulse sent back from the microcomputer 31 is measured. The r focus transfer lock pulse consisting of focus θ~7 is at step IO Hiro~
/20, this is done by alternately performing the setting of the antenna terminal AN'l' and the subroutine "CN'['CLR"Q.

Here, the subroutine @CNTCLR" consists of Step 5 shown in Fig. 1θ, Step 73≠, /33, and clears the interrupt counter, and clears the contents of the interrupt counter and the period TM (1'LAM). The transfer lock period TM is controlled to be one by one by checking the match between the transfer lock period TM and the transfer lock period TM.

Subroutine ``〒ASK/'' step/, 27~/
In 21, the slave side microprocessor 3/
In order to measure the period T8 of the focus transfer lock pulse sent back by
RE/” are repeated alternately.

Figure 1 is a flowchart of the subroutine "MBA8UIL'E O", in which the contents of the error flag register are checked in step /JG, and if it is /", it is a return, or if it is θ", it is in step /37. The interrupt counter is cleared. Next, in step /31, a check is made to see if @, H has been transmitted to the antenna terminal AN'F.
Since the formant has been created as shown in ``C'', proceed to Step 1/39 where the contents of the interrupt counter /uO are checked to see if they are one time the transfer lock period TM, and step /39 is executed. In step 39, white is normally decided, so we return to step 31.
3→Step /39→39→Step ゛/31→Suden 1/39... and repeats the movement. However, at some point the antenna terminal AN! falls to 0'', so at that time step 13 to step /
39, and in step i39, the contents of the interrupt counter are stored in the corresponding area of the RAM as the measurement clock cycle TS.This causes the period until the antenna terminal ANT falls from 1" to 10", that is, the antenna terminal ANT falls to 11
The period T8 can be measured.

Also, as mentioned above, Stetsu 7 t3r→Sten 1/39
→ String / 31 → Step 13 ... Even during roofing, the interrupt routine continues asynchronously, and due to this, the interrupt counter iqo is incremented, but the antenna Terminal ANT is @O forever
If the interrupt counter does not fall to λX,
A count value called TM is counted. This is due to a communication failure, so step/
The program advances from JF to step /4'/, sets an error flag in the error flag register in step 1, and returns. However, only in the measurement of bit r, the measurement result is not adopted because the operation is only to detect the fall of the antenna terminal ANT from 11'' to @O''.

The subroutine "MEASURE/" is shown in Figure 12.
This is the same as UR'Eo.

Thus, when the return lock cycle consisting of the r focus of ~focus r~/4I is measured, the subroutine ``l〒A
At step /29 of "SK/", the interrupt counter is cleared, and at the next step /30, the F-flag register is checked again.As a result, if the content of the error flag register is "l#", the interrupt counter is cleared. is returned to the main program, but if its content is @O'', it is moved to step /J/.

In step 131, calculation of the average value of the measurement clock period 〒8 is executed, but here, the approximate value is calculated by majority vote and is set as the average value of the measurement clock period TS. The current transfer lock 'FM' is rewritten. Next step 133
Now, the contents of the interrupt counter and the transfer ptsukTM are compared, and the interrupt counter continues counting until they match, and at the 11 points that match, the control is returned to the main program (22). .

In parallel with the above-mentioned subroutine "TASK/", the microcomputer J/LX on the slave side executes the subroutine "l'AsK,2". Measurement of the period JUj 'PM of the transfer lock pulse sent from the side and processing of the measurement results Step ias~/67
is step /2/ of subroutine "TASK/" -
/33, and step isr~/73, which sends the clock pulse back to the master side based on the measurement transfer lock cycle, is also the subroutine "l〒ARK/
It is almost the same as the step /It −/λO of '. However, since it only follows the transfer lock period TM of the focus Q and detects the falling edge of the antenna terminal, the measured value itself has no meaning.

In addition, since the measurement of the transfer lock of the focus point B is completed and bit 7 is 11", the interrupt counter is cleared at the rising edge of the step 3. Therefore, the transfer lock is cleared. Period 'FM measurement was carried out for focus θ~B, and during focus 70 period ';1ij3~
/j7 is executed.

In addition, the subroutine "MEA8UR'E o ' in STETSU11413"-/j2, part of ASUR1
It/'' consists of the steps in the flowchart shown in Figures 11 and 12, and
The subroutine "CTRCLR" in -i'y3 consists of the steps of the flowchart shown in FIG.

Figure 1 is a flowchart of the subroutine "E)tROR" of step 67 in the main program. This subroutine "IflRROR' is a microcomputer, 3/ is "TASK/", "
This is executed after finishing TASK2'', and the focus 76 of the communication format (Fig. 77
) This routine determines the value of step ■). Referring to the flowchart in FIG. 1, the interrupt counter is cleared in step 174t, and in step /7j a comparison is made to see if the contents of the interrupt counter match the transfer lock period TM. If they match, in the next step 176, the antenna terminal ANT-b'-"l" is set to indicate that the transfer lock has been synchronized. However, if they match, it is checked in step 177 whether or not the error flag register is set to l''.As a result, if the error flag is l'', the antenna terminal AN is After 'I' is set to θ'', control is returned to step /71. However, if the error flag is o', the antenna terminal ANT is set to 11'' in step /79, and again in step /10. antenna terminal ANT
A check is made to see if is 1pa. Find out the reason,
This is because the antenna terminal ANT may be set to o" at any time to indicate an abnormality on the master or slave side, and it is necessary to check this. In step tro, the antenna terminal ANT is set to @l". Ah, control is transferred to step/76,
Otherwise, in step tri, the error flag register ``/'' is set and control is returned to the step 17j. Subroutine “ERROR” like this
In the subroutine "'l!A8/".

(25) "TASK, 2" checks whether the error flag register has been sent, and if the error flag has been sent to @/m, the antenna terminal AN'l
' is set to 'O'. Also, the error flag is set to '/
”, the other party's error transmission is detected, and the other party is connected to the antenna terminal AN' due to the error.
I! If it is set in ItOII, set the error flag register to al'', wait until pinto/6 is completed, and write the contents of the interrupt counter and the transfer lock period.
When M matches, the step of setting the antenna terminal to II t l+ and returning to the main program is executed. 'A8KJ' flowchart) 't-ab. The master side microcomputer 2/ transfers data to the slave side microcomputer 31 in this subroutine 'I'A8Kj'. Referring to
vinegar? 7y tex, 77 tena terminal AN in tr3
'l' @OII upper set subroutine'' CTN
CLFL" is performed, and (26) "o" of point/7 is sent. Next step 71trt
At t, data transfer of /2 bits consisting of pinto points 7g to 7g is performed, and FIG. 76 is a flowchart of the subroutine "DA'l'A OU'l'". Already at step tλ of the main program,
Since the data to be transferred is stored in RAM1vcrs, the subroutine "DA'l"A OUT" reads the data and serially transfers it according to the data management number. As shown in FIG. The data management number is cleared in step 94, and the RA corresponding to the predetermined data management number is cleared in steps 97 to 19.
The data stored in the low cable of M/ is read out and then set to the antenna terminal ANT, O" or "/" depending on whether the data is 10" or 1".

After the assigned l focus period is controlled by the subroutine "CNTCLR" (see FIG. 1.theta.) of step 200, the data management number is incremented in step 1 .theta.l. Next, when the transfer of the data corresponding to the data management numbers "θ'" to "//" is completed, it is detected in step 2o2, so the execution of the subroutine "DA'L'AOUT" is completed, and the subroutine "DA'L'AOUT" is completed. Control is transferred to step /Ij of ``TASKJ''. As described above, one lens pin is made up of three pins, ie, pins 30 to 32, and steps /IS to /II are for determining the value of pin 3o, which is the pinto of the check pins. It is checked whether the focus is "l" in step l or j, and if it is "l", the antenna terminal ANT is set to I in step /It.
If it is set to O'', it is sent to the antenna terminal ANT at step /17. Here, step tll (D qj full f y ” CN
'l'CLR''&j, /(tare Similar to 7-tl≠, this is a subroutine that controls the l focus transfer period.

Step ゛/1 that flashes in the first focus of Chieji 7 Kubinto
9~/92 is almost the same as STETSU 11 zaj~iga', but is there an actual routine that uses all the values of focus B as they are and the values of focus 31? ′]′ is done. In step I-3, the 77 tenor terminal ANT is set to θ'', and in step 15'≠ the subroutine "CN'I!"CLR" is executed, the third focus of the check bit, focus 3, is sent to the transmission line. In the final step 19j of the subroutine "TASK3", the antenna terminal AN'I
' is 1 cent per cent.

17 and 7g are flowcharts of the subroutine "TAsx4t" in step 72 of the main program. In this subroutine "TASK≠", the serial data transferred from the slave side is received and stored in tAM3, and after checking all the data to see if there is a transfer error, if there is no transfer error. The step of transferring the data stored in RAM J to RAM 2 is executed. Referring to the flowchart in FIG. 77, first, the interrupt counter is cleared in step 203, and steps 204 and 205
The contents of the interrupt counter are transferred at the lock cycle TM.
and the antenna terminal AN'
A check is made to see if l' is set to 6pa. Even if the transfer lock period TM is twice as long, if the slave l')Q) side does not start data transfer, that is, if the antenna terminal AN'I' does not fall to O'', the master side microcomputer 21 returns control to the main program without doing anything.

In this way, when there is no data transfer from the slave side, input data is not transferred from RAM 3 to RAM 2.

However, at step "2θj, the antenna terminal AN
When it is detected that '11 is 60'', the transfer cycle starts from that point, and the subroutine ``CN'P CIJt'' is actually executed at step 1θt.

Then, when the period corresponding to bit 34I has elapsed, the transferred data starts to be captured, but in order to sample the data at the midpoint of the transfer tarlock cycle TM, the timing is adjusted in step 12Q7, and then step , 2Or subroutine ``DA'l!A I
N" is executed. This subroutine"DA'11A
IN'' is the step 2.24' to 23 in which the input data is read into the RAM 3 according to the data management number.
Consists of 0.

(3θ) Therefore, in step -22'A, the data management number is cleared, and in step 2.26-. In 2.27, the data transferred to the antenna terminal ANi' is stored in the location determined by the required data management number (AM 3).In the next step, the blueprint transfer lock is Period TSF (: The corresponding Mtl-il is side controlled, and the data management number is further incremented (+z) in steps 7 and 2j9. Then, in step 230, the data management number is "/2". If it is less than 12'', control is returned to step 223, and if it is /2'', the control is transferred to subroutine ``FASK4''.

At this time, in the subroutine "'l'AsK4'", Zanfu ring is performed at the midpoint of the bin) 4'7 (tV4 in Figure μ), and this focus is the 3rd/focus of the 3-bit check focus. The value is set in a complementary relationship with the value of Bindog≦. Therefore, stets 7, 2
From 2009 to 2/3, this check is performed, and if the pintogua is 10'' in step 20, step 21 is performed.
At 0, check whether the focus N is "Pa".

As a result, if bintoge 6 is 60", there is no complement relationship with the value of focus & 7, so if you check in step 2/2, the flag register will be sent, and in the next step the control will be in step 2/3, the subroutine. ” CN'l!
CLIL”. However, the focus is “/”
If so, control should be transferred directly to Stella 12/3. Also, pintogua is “Padebin”
Also when 4'7; is l'', step 209.

2// will be detected and the flag register will be sent.
If focus 17 is l'' and bin) F4 or θ'', the control is Stellar. 20 zo, 2// is directly transferred to step 2/3.

Next step. 27≠～. In 27K, a check is made to see if the second focus of the check focus is the same as the second focus. Furthermore, step 277
It is checked whether the check focus is 81!3 in focus, which is the bin+1' or l'', and if it is l'', it is sent to the check miss flag register or at step -22θ, but if it is 1θ'', the control is sent to step 22.
/ Transferred to VC. Finally, step. In 221, it is checked whether the check miss flag register is "/",
Check whether there are any errors in the data transfer VC. If the check miss flag register is not "/", the data in RAM 3 is saved to RAM 2, but if it is ol+, the control is returned to the main program after the check miss flag register is reset. Therefore, data in RAM 3 is not written to RAAi 2. By the way, referring to Figures 1S to 7G, the master side subroutines "TASK3" and "TASK4'"
Have you explained the subroutine on the slave side?
4t'' (Mei 7 program's Stesohu 73) +
`` `` `` I'A8KJ '' (Step 7 of the main program ≠) is almost the same, so its explanation will be omitted. In addition, for example, a photoelectric conversion element is used for the antenna terminal ANT, and the transmission line is configured with an optical fiber. I can do something.

As described above, according to the present invention, the copying machine main body (33) and its attached devices perform serial-to-parallel conversion and parallel-to-serial conversion of data, respectively. J! ．． By providing microcomputers with
The number of data transfer devices is extremely small, and a highly reliable data transfer device can be provided.

Moreover, since the present invention has a simple configuration, it can be easily applied to existing copying machines.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional data transfer device, Fig. 3 is a block diagram showing an example of the configuration of the main part of a data transfer device according to the present invention, and Fig. Signal waveform diagram showing Yonfuo-Man TF, Figure J & 1 Main part block diagram of the 71K computer applied to the present invention, Figure 6 is a flowchart of its main program, Figures 7 to 11 are flowcharts of subroutines. 〃... Transmission/reception capital for copying machine body, 21... Master side microcomputer, (3ri) 〃, 32... Master/slave 11 exchange switch, 2
3 to 2, 33 to 36... amplifier, 3θ... transmitting/receiving unit for dosing device, 31... slave side microcomputer, ji...
・Control storage unit, j2... RAM capital, j3...
Arithmetic cooking unit, J Hiro...accumulator, R
AM...random access memory, DCR...decoder, ROM...read-only memory, PC...frame counter, S'l'K...stack. Patent applicant Canon Corporation (3S) JP 11H58-80733 (13) JP 11H58-80733 (14) JP 11H58-80733 (14) JP 11H58-80733 (14)
Bff 58-80733(15) Ward-204- Fig. 17 (TASK4 L+7- Sliding force layer 21
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Claims (1)

[Claims] The copying machine main body and its attached device are equipped with microcomputers each having a program for serial-parallel conversion and parallel-serial conversion of data, and the copier main body and the additional device are connected by a single wire, and Re-? A data transfer device characterized by serially transferring data using a microcomputer.