JPH0587851B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication method for transmitting and receiving data between a first data processing device and a second data processing device. The present invention relates to a data communication system in which each of the first and second data processing devices can communicate data with each other in a synchronized mode.

In general, copying machines that improve operability and precisely control copy quality include a data communication device that exchanges various data between the copying machine itself and additional devices equipped with a sorter, input sensor, etc. is necessary. This type of conventional data communication device has a first
As shown in the figure, the copying machine body 11 includes a central processing unit (CPU) 12, an I/O controller 13, an output driver 14, an input interface 15,
It has a CPU power supply circuit 16 and an additional device power supply circuit 17. The additional device 18 includes a sequence controller 19 and an input interface 20.
A, an output driver 21A, an output load 22A, and an input sensor 23A, and for example, a flat cable consisting of a number of connecting wires corresponding to various signals is used for mutual data transfer.

Input interface 15 of copying machine main body 11 and input interface 20A of additional device 18
As a noise prevention measure, as shown in Figure 2,
It can also be configured using a photocoupler.
However, in any case, as the number of types of signals to be transferred increases, the number of connector pins also increases, which not only increases the cost of connectors and cables, but also causes deterioration in device reliability. . Also, universal asynchronous
It is called receiver transmitter (UART).
There are data communication devices that can perform serial communication at transmission speeds of 10K to 20K (bits/second), but they are expensive and, although they are versatile, they are not suitable for use as data communication devices between the copying machine and its additional devices. There are many unsuitable points.

Therefore, in order to eliminate the above-mentioned drawbacks, the copying machine main body and its additional devices are each equipped with a microcomputer for serial data transfer, and the copying machine main body and its attached devices are connected to each other by regenerating the period of the transfer clock pulse sent and received via a single-wire transmission line. When data is serially transferred to and from an additional device, there is a problem in that communication cannot be established due to a discrepancy in the operating times of the microcomputers on the sending and receiving sides. Furthermore, when data is serially transferred programmatically, there is a problem that, due to the structure of the program, reproduction of the period of the transfer clock pulse cannot cope with changes in the transmission state of the transmission line at one transmission speed.

The present invention eliminates the drawbacks of the prior art described above, and makes it possible to select a communication mode such as a communication speed when performing data communication between a first and second data processing device, and further enables selection of a communication mode such as communication speed. After the synchronization is completed, each device is able to send data to the other device, so the first and second
An object of the present invention is to provide a data communication method that can reliably perform two-way data communication between two data processing devices in a synchronized communication mode between both devices.
Furthermore, the present invention allows only the master device to set the communication mode for the above-mentioned two-way data communication and start processing for synchronization, so that each device that performs data communication can do so automatically. To provide a data communication method that prevents inconveniences such as when the data communication mode becomes inconsistent due to changing the data communication mode, and that allows two-way data communication to be reliably performed in a consistent mode. purpose.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an example of the configuration of the main parts of the data communication device according to the present invention. This data communication device has compatible transmitting/receiving units 20 and 30.
are provided in the main body of the copying machine and additional devices, respectively. The transmitting/receiving sections 20 and 30 each have a microcomputer 21 and 31 and an interface circuit built into a single printed circuit board. The transmission line connecting the transmitting and receiving units 20 and 30 includes a connecting line connecting the antenna terminals of each other, and
It consists of a common ground. Therefore, in implementation, a single connection line can be used as a transmission line.

The microcomputers 21 and 31 have the function of serial-parallel conversion and parallel-serial conversion of data, and the switches 22 and 32 connected to the port R4
Switch the master/slave setting with . In the illustrated case, the microcomputer 21 of the copying machine main body transmitting/receiving section 20 is the master, and the microcomputer 31 of the additional device transmitting/receiving section 30 is the slave. Microcomputer 21,3
1 has a power terminal V _CC , a ground terminal V _SS , and control terminals RT, EX, and X. When power is supplied to the power terminal V _CC , a reset signal is sent to the control terminal RT to initialize the system. Furthermore, an oscillating oscillator is connected to the control terminals EX and X to oscillate a clock pulse of, for example, 2 MHz. by the way,
The microcomputers 21 and 31 include, for example, ROM (read only memory) and RAM.
A microprocessor containing random access memory (random access memory) on one chip can be used.

In this data communication device, the transmitting/receiving section 2
Input terminal consisting of 0 terminals P113 to P124
When data is supplied to IN1 from the copying machine,
The data is amplified by amplifiers 23 and 24, and read by the microcomputer 21 through each terminal of the R2 port, R3 port, and K port, converted into serial data, and then sent from port R1 to the antenna terminal.
It is transmitted to the transmitting/receiving section 30 via ANT. The transmitter/receiver 30 receives the serial data via the antenna terminal ANT, and transmits the serial data to the microcomputer 3.
Input to R1 port of 1. The microcomputer 31 converts the serial data into parallel data again and supplies it to amplifiers 33 and 34 via the O port and P port terminals. And amplifier 3
3 and 34 amplify the parallel data and connect it to the terminal P20.
It is transferred to the output terminal OUT2 consisting of 1 to P212.

Similarly, when the transmitting/receiving section 30 on the slave side transmits data to the transmitting/receiving signal 20 on the master side, the additional device transmits the data input to the input terminal IN2 consisting of terminals P213 to P224 to the amplifier 3.
5, 36, the microcomputer 31, the antenna terminal ANT, the microcomputer 21, and the terminals P101 to P via the amplifiers 25, 26, respectively.
112 to the output terminal OUT1. In this case, the microcomputer 31
performs parallel-to-serial conversion of data, and microcomputer 21 performs serial-to-parallel conversion of data.
In this way, the transmitting/receiving sections 20 and 30 can perform bidirectional data transfer.

40 is R4 of one microcomputer 21
This is a master side transmission speed selection switch connected to the port. When this switch 40 is in the "open" state as shown in the figure, "TM" is selected as the transfer clock cycle, and when it is switched to the "closed" state, the transfer clock cycle is set to "TM'".
can be selected. Similarly, 41 is a slave-side transmission speed selection switch connected to the R4 port of the other microcomputer 31, and by opening this switch 41, the transfer clock cycle can be selected as "TM". Also, by setting it in the "closed" state, the transfer clock cycle can be selected as "TM'".

However, master/slave selector switch 2
By setting 2 and 32, microcomputer 3
1 is a slave, the transmission rate is selected on the master side, so the slave side transmission rate selection switch 41 stops its function and does not operate. Therefore, the switch 41 is activated only when the microcomputer 31 is the master.

FIG. 4 is a signal waveform diagram showing an example of a communication format applied to the data communication device of FIG. 3. Microcomputer 21, 31
As shown in the figure, one frame of data can be transferred by executing 11 steps. In step 1, the master side microcomputer 21 and the slave side microcomputer 31 perform synchronization control of the transfer clocks. Therefore, the microcomputer 21 starts from the step where the transmission line is open, by changing bit 0 of one frame from "1" to "0".
The step is started, and a transfer clock pulse consisting of 8 bits is set as TASK1 with a periodicity as described later.
TM and transmits it to the microcomputer 31.

During this period, the microcomputer 31
TASK2 is activated from the rising edge of the bit, and the period of the transfer clock pulse sent from the master side
TM is measured 8 times for bits 0 to 7, and calculated to obtain the average value TS of the transfer clock period, which is returned to the microcomputer 21 at bits 8 to 15 in step. The microcomputer 21 then checks whether the transfer clock period TM and the average value TS are equal. If TM≠TS
If so, communication with the microcomputer 31 is not possible, so in step bit 16, the transmission line is set to "0" and is notified to the microcomputer 31, so that the microcomputer 31 recognizes the failure of mutual communication and returns from the initial state. Start over. However, if TM=TS, the microcomputer 21 sets bit 17 to "0" to determine the starting point of the true data in step,
Start running TASK4. The microcomputer 21 starts counting the transfer clocks from bit 17 in step. Therefore, this bit
The transfer bit cycle starts from the falling edge of bit 17, and the cycle of each bit from bit 17 to bit 49 is TM=TS.

In the next step, the microcomputer 21 executes TASK3 and first bits 18 to
The 12-bit serial data consisting of 29 bits is transferred to the microcomputer 31, and then the check bit consisting of 3 bits 30 to 32 of the step is transmitted. Of these check bits, bits
Although 30 may be an even parity bit, in this embodiment, it is set to "0" so as to set the complement of the previous bit 29, thereby clarifying the distinction between bit 29 and bit 30. bits in check bits
31 is set depending on the content of the data, and in this embodiment, the 7th bit of 12-bit data is set.
It is set to "1", which is the same value as bit 25, which is the second bit. The check bit of bit 32 is set to “0” to represent the final bit, and when this bit 32 ends, it is set to “1” and the check bit is
33 opens the transmission line.

The microcomputer 21 steps ~
During the period in which TASK3 is being executed, the microcomputer 31 executes TASK4 to read the transferred data. In this way, the microcomputer 21 operates at the terminal P of the transmitter/receiver 20.
The parallel data supplied to P113 to P124 are converted to serial data, and the antenna terminal ANT
The microcomputer 31 receives the serial data, converts it into parallel data again, and sends it to the transmission line via the terminal P201 of the transmitting/receiving section 30.
~P212 respectively. Therefore, the terminals P112 to IN1 of the transmitting/receiving section 20
The data supplied to P124 is sent to the corresponding terminals P201 to P2 of the output terminal OUT2 of the transmitter/receiver 30.
It will be distributed to 12 people.

By the way, in step, the microcomputers 21 and 31 prepare to switch the transmission/reception mode and change the transmission direction of the data. Then, in step, the slave side microcomputer 31 starts transmitting data.
Bit 34 is set to "0" and counting of transfer clocks begins. Microcomputer 31
Since the transfer clock has already been synchronized in step , 12-bit serial data (bits 35 to 46) can be sequentially transmitted to the microcomputer 21 in the transfer clock period TM in step.

Also, in step, microcomputer 31 sends 3 check bits (bits 37 to 39) to microcomputer 21 in the same manner as in step. Thus, while the microcomputer 31 is executing TASK3 for transmitting data, the microcomputer 21
Execute TASK4 to receive the data. Therefore, the data supplied to the terminals P213 to P224 of the input terminal IN2 of the transmitter/receiver 30 is transferred to the corresponding terminal P1 of the output terminal OUT1 of the transmitter/receiver 20.
01 to P112, respectively. In the step, both microcomputers 21 and 31 open the transmission line and enter TASK0, waiting for the start of the step of the next frame for data transfer.

FIG. 5 is a block diagram showing the configuration of essential parts of the microcomputers 21 and 31. The microcomputers 21 and 31 each have a control storage unit 51 and a RAM (random access memory).
52, an arithmetic logic unit 53 and an accumulator 54. Here, the control storage unit 5
The ROM (read only memory) No. 1 stores information necessary for controlling microinstructions and data transfer clock cycles. Decoder DCR
decodes the data read from the ROM, and the program counter PC specifies the OOM address. Also, the stack STK is for example
A set of registers used in a LIFO (last in first out) format.

Next, the RAM section 52 consists of a plurality of memory areas, the addresses of which are designated by X and Y address registers. Among the plurality of memory areas, RAM1 stores data supplied to the input terminal IN1 or IN2, and RAM2 stores data supplied to the output terminal OUT1 or OUT2. The RAM 3 is a memory area that stores serial input data transmitted from the other party's computer to the R1 port via the antenna terminal ANT. In addition, the RAM section 51 includes an interrupt counter that increments by +1 when there is a timer interrupt, a memory area that stores the transfer clock cycle TM, and a memory area that stores the measured transfer clock cycle.
There is a memory area for storing TS, a memory area for storing management numbers of input/output data, etc.

Next, the operation of this data communication device will be explained with reference to the main program flowchart in FIG. 6 and the subroutine flowcharts in FIGS. 7 to 19.

When power is supplied to the microcomputers 21 and 31 and initialization is performed by a reset signal, the main program shown in FIG. 6 is started. First, the RAM is cleared in step 61, and the subroutine ``IO DATA'' is executed in the next step 62.This subroutine ``IO DATA'' is executed by the microcomputers 21 and 31, respectively, to input information to the input terminals IN1 and IN2. is read into RAM1 and output terminal OUT
1. This is a routine that supplies output information read from RAM2 to OUT2. In step 63,
The transfer clock period TM is set in the RAM and the interrupt counter is activated. Transfer clock period TM
As mentioned above, is written in the ROM and determines the serial data transmission speed. The interrupt counter increments its contents by +1 every time a timer interrupt occurs.

In step 64, each microcomputer 21, 31 determines whether it is a master or a slave. And the microcomputer 21
Since the microcomputer 31 is the master and the microcomputer 31 is the slave, the process moves to the next step and executes the subroutine "TASK1" at step 64 and the subroutine "TASK2" at step 66, respectively.
Therefore, the microcomputer 21 first calculates the period.
A transfer clock pulse is sent to the transmission line using 8 bits from bit 0 to bit 7 in TM, and the microcomputer 31 measures the transfer clock period (see the steps in FIG. 4).
Next, microcomputer 31 returns a transfer clock pulse from bit 8 to bit 15 based on the measured transfer clock period TS, and microcomputer 21 receives the transfer clock pulse (see steps in FIG. 4).

In this way, the microcomputer 21,
31 performs synchronization control of the transfer clock cycle;
As a result, if the clock period TM≒TS, mutual communication is possible. This determination is made in the subroutine "ERROR" at step 67, and when the clock period ≠ TS, "1" is input to the error flag register. The microcomputer 21 determines whether this error flag is "1" at step 68. If the error flag is "1", the process moves to step 69, resets the error flag register, and then returns to step 62.
However, if the error flag is "0", control is transferred to the next step 70.

Here, if the error flag becomes “1”, the fourth
As indicated by the step in the figure, the microcomputer 21 drops the transmission line to "0" and informs the microcomputer 31. However, even if an abnormality occurs in the microcomputer 31 and the transfer clock period cannot be measured, it will be detected in the subroutine "ERROR", the error flag register will become "1", and the transmission line will also become "0".

Now, in step 70, it is determined whether the microcomputers 21 and 31 are masters or slaves again, and the microcomputer 2 on the master side
1 executes subroutines "TASK3" and "TASK4" in steps 71 and 72, and at the same time, the microcomputer 31 on the slave side executes subroutines "TASK4" and "TASK3" in steps 73 and 72.
Execute on 74. That is, the microcomputer 21 first sets the transmission line to "0" in the steps shown in FIG. Transfers 3 check bits. At this time, the microcomputer 31 enters a data receiving operation in steps, and reads in 12-bit serial data and 3-bit check bits in steps.

In this way, the microcomputer 21 executes the subroutine "TASK3", and the microcomputer 31 executes the subroutine "TASK4". Then, after the transmission line is opened in the step shown in FIG. Execute subroutine “TASK4”. When the microcomputers 21 and 31 complete the subroutines "TASK4" and "TASK3" at steps 72 and 74, respectively, control is transferred to step 62 for the next data transfer.

The steps of the main gram are as described above, and each of its subroutines will be sequentially explained next.

First, in the subroutine "IO DATA", the microcomputers 21 and 31 transfer input data to the RAM 1 according to data management numbers 0 to 11.
The output data is read out from RAM2. Therefore, as shown in the flowchart of Figure 7, the subroutine “IO
When "DATA" is called, the management number is cleared in step 81, and the management number is cleared in steps 82 to 86.
The input data is loaded into RAM1 at step 87, and the management number is cleared again at step 87.
Output data is read from RAM 2 in steps 88-92. That is, in step 82, input data is checked in accordance with the data management numbers "0" to "11" respectively assigned to the input terminals P113 to P124 of the copying machine main body transmitting/receiving section 20 (FIG. 3), for example. be done. For example, depending on whether the data at the input terminal P113 with the data management number "0" is "1" or "0", the process branches to step 83 or step 84, and the process goes to the location of RAM1 corresponding to the data management number "0". The input data is written.

In the next step 85, the data management number is incremented by +1, and the data management number changes from "0" to "1". Therefore, in step 86, it is checked whether the management number is "12" or not. NO” and control is returned to step 82. Similarly, the input data is taken into the RAM 1 according to the data management number, and when the data management number becomes "12", the check at step 86 becomes "YES", so control is transferred to step 87. In steps 88 to 92, the output data read from the RAM 2 according to the data management number is distributed to, for example, the output terminals P101 to P112 of the transmitter/receiver 20, but the control thereof is substantially the same as in steps 82 to 86. Since they are the same, their explanation will be omitted.

Next, in step 63 of the main program, the subroutine "TM SET" of FIG. 8 is called, and steps 93 to 97 are executed. That is, first, in step 93, it is determined whether or not the microcomputer 21 or 31 has been selected as a master by the corresponding master/slave changeover switch 22 or 32. If it has not been selected as a master, the process proceeds to step 94, in which the microcomputer 21 or 31 is stored in the RAM. The value of "TM" is set in the memory area of a certain period TM, and the process advances to step 97. On the other hand, if the master is selected, the process advances to step 95, and the corresponding transmission speed selection switch 40 or 41 is set to "open".
It is determined whether the state is as follows. If the corresponding switch 40 or 41 is in the "open" state, that is, the switch flag has a value of "1", the process proceeds to step 94, where the value of "TM" is set in TM at a certain period in the RAM, and the process proceeds to step 97. . That switch 4
If 0 or 41 is in the "closed" state, that is, the switch flag has a value of "0", step 96
Set the value of “TM′” to the periodic TM in RAM,
Proceed to step 97. Subsequently, in step 97, an interrupt counter is started and the process returns to the main program shown in FIG.

By using the above-mentioned "TM SET" method, the master side can switch the transmission speed to match the transmission speed of the slave side, so the problem of communication failure due to the difference in operating time between the master side and slave side is solved. It is possible to solve this problem, and it is also possible to easily cope with changes in the transmission state of the transmission path.

In step 63 of the main program,
As mentioned above, the clock cycle TM transferred to RAM
Alternatively, TM' is set and the interrupt counter is enabled. When a timer interrupt occurs, this interrupt counter calls the interrupt routine shown in FIG.
3 will be executed. That is, each time an interrupt occurs, the contents of the interrupt counter are incremented, and when the interrupt counter overflows, the error flag register is set.

The microcomputer 21 executes the subroutine "TASK1" at step 65 of the main program.
Execute. FIGS. 10 to 13 are flowcharts of the subroutine "TASK1".
By executing the subroutine "TASK1", the microcomputer 21 connects the antenna terminal
After sending a transfer clock pulse with a period TM consisting of repeating "0" and "1" to the transmission line via ANT, the period TS of the transfer clock pulse returned from the microcomputer 31 is measured. The 8-bit transfer clock pulse consisting of bits 0-7 is achieved by alternating the setting of the antenna terminal ANT and the subroutine "CNT CLR" in steps 104-120.

Here, the subroutine “CNT CLR” is the first
As shown in Figure 0, steps 134, 13
The transfer clock cycle TM is controlled to be constant by clearing the interrupt counter and checking whether the contents of the interrupt counter match the cycle TM (set in RAM).

Step 121 of subroutine “TASK1”
At step 128, the master microcomputer 21 alternately executes subroutines "MEASURE0" and "MEASURE1" in order to measure the period TS of the 8-bit transfer clock pulse sent back by the slave microcomputer 31.

FIG. 12 is a flowchart of the subroutine "MEASURE0". In step 136, the contents of the error flag register are checked and set to "1".
If it is "0", the interrupt counter is cleared in step 137. Next, in step 138, the antenna terminal ANT is
A check is made to see if the value of the interrupt counter is "1", but since the antenna terminal ANT has been formatted in advance so that the initial value is "1", the process advances to step 139 and the contents of the interrupt counter are set to the transfer clock. A check is made to see if the period is twice the period TM, and if the content of the interrupt counter is less than or equal to 2×TM, control is returned to step 138 described above.
Therefore, the antenna terminal ANT changes from “1” to “0”
Within the period TS until it falls to
Step 8→Step 139... is looped and repeated. However, at some point the antenna terminal
“0” is transmitted to ANT, and the antenna terminal
ANT falls to “0”. At that time, step 1
Proceeding to step 40, the contents of the interrupt counter are stored in the corresponding area of the RAM as the measurement clock period TS, thereby making it possible to measure the period TS during which the antenna terminal ANT is "1".

Also, as mentioned above, even during the loop of step 138 → step 139 → step 138 → step 139, etc., the interrupt routine continues asynchronously, and the interrupt counter is incremented each time. However, the antenna terminal remains
If ANT does not fall to "0", the interrupt counter will eventually count a count value of 2 x TM. Since this indicates a communication failure, an error flag is set in the error flag register at step 141, and control is returned to the main program. However, only when measuring bit 8, the antenna terminal ANT
The measurement result is not adopted because the operation is only to detect the fall from "1" to "0".

The subroutine "MEASURE1" is the same as the subroutine "MEASURE0" except that the branching conditions of steps 142 and 143 are reversed, as shown in FIG.

In this way, when the return clock cycle consisting of 8 bits 8 to 14 is measured, the interrupt counter is cleared in step 129 of the subroutine "TASK1", and the error flag register is checked again in the next step 130. It is done. As a result, if the content of the error flag register is "1", control is returned to the main program, but if the content is "0", control is moved to step 131. In step 131, the average value of the measurement clock period TS is calculated. Here, the approximate value is calculated by majority vote and is set as the average value of the measurement clock period TS. In step 132, it is already stored in the RAM. The current transfer clock TM is rewritten. In the next step 133, the contents of the interrupt counter and the transfer clock TM are compared, and the interrupt counter continues counting until they match, at which point control is returned to the main program.

In parallel with the above-mentioned subroutine "TASK1", the slave side microcomputer 31
Execute subroutine “TASK2”. FIG. 14 shows the flowchart, and steps 145 to 157 for measuring the period TM of the transfer clock pulse sent from the master side and processing the measurement results are steps 121 of the subroutine "TASK1". - 133, and steps 158-173 for returning clock pulses to the master side based on the measurement transfer clock cycle are also almost the same as steps 104-120 of subroutine "TASK1". However, the transfer clock cycle of bit 0
As for TM, the measured value itself is meaningless because it only detects the falling edge of the antenna terminal ANT. Further, after the measurement of the transfer clock TM of bit 6 is completed, since bit 7 is "1", the interrupt counter is cleared at the rising edge of bit 7 in step 153. Therefore, the transfer clock period TM
The measurements are made for bits 0-6, and steps 153-157 are executed during bit 7.

The subroutines "MEASURE0" and "MEASURE1" in steps 145-152 consist of the steps in the flowcharts shown in FIGS. 12 and 13, and the subroutine "CTR CLR" in steps 158-173 consists of the steps shown in FIG. It consists of the steps of a flowchart.

FIG. 15 is a flowchart of the subroutine "ERROR" at step 67 in the main program. This subroutine "ERROR" is executed after the microcomputers 21 and 31 finish "TASK1" and "TASK2", respectively, and is executed after the microcomputers 21 and 31 finish "TASK1" and "TASK2", respectively.
This routine determines the value of step (in the figure).
Referring to the flowchart of FIG. 15, the interrupt counter is cleared in step 174, and in step 175 the contents of the interrupt counter and the transfer clock period TM are compared to see if they match. If they match, the antenna terminal ANT is set to "1" in the next step 176 to indicate that the transfer clocks have been synchronized. However, if they do not match, it is checked in step 177 whether the error flag register is set to "1". the result,
If the error flag is “1”, step 178
After the antenna terminal ANT is set to "0" at step 175, control is returned to step 175.
However, if the error flag is "0", the antenna terminal ANT is set to "1" in step 179, and a check is made again in step 180 to see if the antenna terminal ANT is "1". The reason is that the antenna terminal ANT is always “0” on the master or slave side to indicate an abnormality.
This is because there is a possibility that the data will be used in the future, and it is necessary to check this.

If the antenna terminal ANT is "1" in step 180, the control goes to step 175.
If not, the error flag register is set to "1" in step 181 and control is returned to step 175. In this way, in the subroutine "ERROR", it is checked whether the error flag register was set in the subroutines "TASK1" and "TASK2", and if the error flag is set to "1", the antenna terminal ANT is set. Set to “0”. In addition, if the error flag is not set to "1", an error transmission from the other party is detected, and the other party is connected to the antenna terminal ANT due to an error.
If it is set to "0", set the error flag register to "1", wait until bit 16 is completed, and when the contents of the interrupt counter and the transfer clock period TM match, turn the antenna terminal " 1”
A step is executed in which the program is set to 0 and returns to the main program.

16 and 17 are flowcharts of the subroutine "TASK3" in step 71 of the main program. In this subroutine "TASK3", the master side microcomputer 21 executes the slave side microcomputer 31.
transfer data to. Referring to the flowchart of FIG. 16, in steps 182 and 183, the antenna terminal ANT is set to "0" and the subroutine "CTN CLR" is executed, and bit 17 is set to "0".
is sent. In the next step 184,
A 12-bit data transfer consisting of bits 18 to 29 is performed, and FIG. 17 is a flowchart of the subroutine "DATA CUT". Already in step 62 of the main program,
Since the data to be transferred is stored in the RAM 1, the subroutine "DATA CUT" reads out the data and serially transfers it according to the data management number. As shown in FIG. 17, the data management number is cleared in step 196, and the data stored in the location of RAM 1 corresponding to the predetermined data management number is read out in steps 197 to 199, and then the data is " Antenna terminal depending on whether it is “0” or “1”
ANT is set to either “0” or “1”.

The period of the allocated 1 bit is controlled by the subroutine "CNT" in step 200.
CLR" (see Figure 10), the data management number is incremented in step 201. Next, when the transfer of data corresponding to data management numbers "0" to "11" is completed, Since it is detected in step 202,
The execution of the subroutine “DATM OUT” is completed,
Control is transferred to step 185 of subroutine "TASK3". As mentioned above, the check bit consists of three bits 30-32, and steps 185-188 are for determining the value of bit 30, which is the first bit of the check bit. In step 185, it is checked whether bit 29 is "1", and if it is "1", step 186 is performed.
At step 187, the antenna terminal ANT is set to "0", and if it is "0", the antenna terminal ANT is set to "1" at step 187. Here, the subroutine "CNT CLR" of step 188 is a subroutine for controlling the transfer period of 1 bit, similar to step 184.

Steps 189 to 192 regarding the second bit of the check bit are almost the same as steps 185 to 188, but the value of bit 25 is used as is.
A routine with a value of 31 is executed. Step 1
The antenna terminal ANT is set to "0" at step 93, and the subroutine "CNT" is executed at step 194.
CLR” is executed, the third check bit
bit 32 is sent out onto the transmission line. Final step 1 of subroutine “TASK3”
At 95, the antenna terminal ANT is set to "1".

Figures 18 and 19 show the subroutine "TASK4" in step 72 of the main program.
This is a flowchart. In this subroutine "TASK4", serial data transferred from the slave side is received and stored in RAM3, and after checking whether there is a transfer error in the data, if there is no transfer error, the data stored in RAM3 is A step is executed to transfer the data to RAM2.

Referring to the flowchart of FIG. 17, first, in step 203, the interrupt counter is cleared, and in steps 204 and 205, it is checked whether the contents of the interrupt counter match twice the transfer clock period TM, and the antenna terminal is checked. A check is made to see if ANT is set to "1". If the slave side does not start data transfer even after twice the transfer clock period TM,
In other words, if the antenna terminal ANT does not fall to "0", the microcomputer 21 on the master side
returns control to the main program without doing anything. In this way, when there is no data transfer from the slave side, the data is transferred from RAM3 to RAM
2, input data is not transferred.

However, when it is detected in step 205 that the antenna terminal ANT has become "0", the transfer cycle starts from that point, and in step 206 the subroutine "CNT CLR" is executed. Then, when a period corresponding to bit 34 has elapsed, the transferred data starts to be captured, but the timing is adjusted in step 207 in order to sample the data at the midpoint of the transfer clock period TM, and then step 207 is started. The subroutine "DATA IN" at 208 is executed. This subroutine "DATA IN" consists of steps 224 to 230 in which input data is read into the RAM 3 according to the data management number.

Therefore, in step 224, the data management number is cleared, and in steps 225 to 227, the data transferred to the antenna terminal ANT is cleared according to the predetermined data management number.
Stored in RAM3 location. In the next step 228, the subroutine "CNT CLR"
is executed, the transfer clock period TM
Control is performed for a period corresponding to , and further, in step 229, the data management number is incremented (+1). Then, in step 230, a check is made to see if the data management number has reached "12". If it is less than "12", control is returned to step 225, and if it is "12", control is transferred to subroutine "TASK4". .

At this time, in the subroutine "TASK4", sampling is performed at the midpoint of bit 47 (see Figure 4), and this bit 47 is the first bit of the 3 check bits, and its value is
It is set to a value of 46 and a complement function. Therefore,
This check is performed in steps 209 to 213, and first, in step 209, bit 47 is set to "0".
If so, step 210 checks to see if bit 46 is "1". As a result, if bit 46 is "0", there is no complement relationship with the value of bit 47, so the check miss flag register is set in step 212, and control is then transferred to the subroutine "CNT CLR" in step 213.
will be moved to However, if bit 46 is "1", control is directly transferred to step 213. Also, when bit 47 is "1" and bit 46 is "1", steps 209 and 2 are executed.
If bit 47 is "1" and bit 46 is "0", control is directly transferred from steps 209 and 211 to step 213.

In the next steps 214 to 218, bit 48, which is the second bit of the check bit, and
A check is made to see if 42 are equivalent. Further, in step 219, it is checked whether the third bit of the check bit, bit 49, is "1", and if it is "1", the check miss flag register is set in step 220.
If it is "0", control is transferred to step 221. Finally, in step 221, it is checked whether the check miss flag register is "1", and it is checked whether there is any error during data transfer. If the check miss flag register is not “1”, the data in RAM3 is
If it is "0", control is returned to the main program after the check miss flag register is reset, and data from RAM3 is not written to RAM2. By the way, while the subroutines "TASK3" and "TASK4" on the master side have been mainly explained with reference to FIGS. 16 to 19, the subroutine "TASK4" on the slave side has been explained.
(Step 73 of the main program), “TASK3”
(Step 74 of the main program) is also substantially the same, so its explanation will be omitted.

Note that a photoelectric conversion element such as a photocoupler can be used for the antenna terminal ANT, and the transmission line can be constructed of an optical fiber.

As described above, according to the embodiment of the present invention, by providing microcomputers that perform serial-to-parallel conversion and parallel-to-serial conversion of data in the main body of the copying machine and its attached device, respectively, it is possible to serially transfer data between each other. The number of pins in the connector that connects microcomputers has become extremely small.
A highly reliable data communication device can be provided. In particular, according to the embodiment of the present invention, since the transmission speed selection means for matching the transmission speeds on the master side and the slave side is provided, it is possible to eliminate the inability to communicate due to differences in operating time between the respective microcomputers. Moreover, it is possible to easily cope with the deterioration of the transmission condition of the transmission line.
Moreover, since the embodiment of the present invention has a simple configuration,
It can be easily applied to existing copying machines.

As explained above, according to the present invention, the first,
When performing data communication between the second data processing devices,
The communication mode of the communication speed can be selected, and furthermore, after the synchronization is completed in the selected desired communication mode, each of the first and second data processing devices can communicate data to the other device. As a result, it is possible to reliably perform two-way data communication between the first and second data processing devices in a synchronized communication mode between the two devices. Furthermore, according to the present invention, only the master device can set the communication mode for the above-mentioned two-way data communication and start processing for synchronization, so that each device that communicates data can Inconveniences such as mismatching of data communication modes due to arbitrary data communication mode changes are prevented, and it is possible to reliably perform two-way data communication in a matched mode.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a conventional data communication device, FIG. 3 is a block diagram showing a configuration example of the main part of the data communication device according to the present invention, and FIG. 4 is a communication format thereof. FIG. 5 is a block diagram of a main part of a microcomputer to which the present invention is applied, FIG. 6 is a flowchart of its main program, and FIGS. 7 to 19 are flowcharts of subroutines. 20... Transmission/reception unit for copying machine main body, 21... Master side microcomputer, 22, 32... Master/slave changeover switch, 23-26, 33-
36...Amplifier, 30...Transmission/reception unit for additional device, 31
... Slave side microcomputer, 40... Master side transmission speed selection switch, 41... Slave side transmission speed selection switch, 51... Control storage unit,
52... RAM section, 53... Arithmetic logic unit, 54
…Accumulator, RAM…Random access memory, DCR…Decoder, ROM…Read-only memory, PC…Prime counter, STK…Stack.

Claims (1)

[Claims] 1. In a data communication system in which data is transmitted and received between a first data processing device and a second data processing device, the first and second data processing devices each communicate data. a data communication means for setting a mode of data communication by the data communication means; a processing means for performing synchronization processing with a partner processing device in the set mode; or a selection means for setting it as a slave, and a determination means for determining whether or not it is selected as a master by the selection means, and the first and second processing devices are configured by the determination means to When it is determined that the device itself is the master, it determines the data communication mode of the data communication means according to the setting mode set by the mode setting means, and performs synchronization in the determined mode. After starting processing and completing synchronization, the first and second data processing devices each transmit data to the other device in a mode in which both devices are synchronized. Communication method.