JPS5879171A - Logic function tester - Google Patents

Abstract

PURPOSE:To shorten the testing time of a circuit to be tested providing a n- valued logic output by binary coding the results of evaluation of test outputs with a plurality of comparators to compare with expected value. CONSTITUTION:A test output of a circuit 1 to be tested according to outputs of an input pattern memory circuit 2 of a logic function tester A is evaluated with comparator circuits 41-43 connected to limit power sources 51-53 for setting a threshold corresponding to each of some logic values to be covered such as 3 valued logic. The results of the evaluation are binary coded with a binary conversion circuit 9 and compared with an expectation read from an expectation pattern memory circuit 6' synchronizing the circuit 2 through a control circuit 8 by means of a comparison evaluation circuit 7' to test the quality of the circuit 1. This eliminates the necessity of two testing procedures in the use of only one comparator circuit for logic value such as 3-valued logic which requires the operation of varying the threshold twice and reading out of an expectation pattern for each variation thereof. Thus, the testing of n-valued logic output can be completed by only one operation without repeating testing procedures n-1 times thereby shortening the testing time.

Description

[Detailed description of the invention]

The present invention relates to a logic function testing device for determining the quality of 1 (111) (111) (111) (111) (111) (111)) (10) functions of digital ICs. When testing, it is important to supply a human input signal to test the logic function and make sure that the 4A output signal output from the digital IC is functionally correct. The logic function testing device will be explained with reference to all the drawings. Fig. 1 is a block diagram including metals of an example of a conventional interpolation test equipment. The circuit under test 1 shown in Fig. 1 is , which is tested with Ethics Iso RQ Examination Equipment A, and this logic + iIf: Testing Equipment A
is a complete list of pattern data consisting of logical signals corresponding to human signals 1. The human cover turn memory circuit 2 that performs t and the logic signal output from the human cover turn memory circuit 2 is converted into the human power level by the failure test circuit 1 to perform the operation. 3 and 1llj test circuit 1 output from test ``r+j output signal bow 11 threshold level appears I', 1is5
And, I'm in front of you.
'ii''、＼It level and previous 1st attempt, 1st time Ni
Test piJ1 Kawa Kai that outputs from 1 "Continued to compare the level of No. 1 A with the level of No. 1 A" circuit 4 and the circuit under test 1, IA Riiso 111 (to t + (1 - C - River] J to be Jt Jl wait 1 period 1 consisting of direct signal 9.!j, putter/data Kinki 1 buzzing Rono j samurai pattern me (: turn bI name 6 and jjif self output from comparator circuit 4 )・Icon pare-1・Signal d↓and low converter output signal and I!ff A: Iυ1 Samurai pattern memory circuit 6 to M1 511a)+tll r:j if
+ 1st issue, 2nd edition, 21st edition to determine the quality of the pass/fail 21''
36. Ii-Yohimei1kiHishukanashiki1'i In order to operate 7 in synchronization, I supplied all of the same Ru1hakuyumi1゛M)'+
ttlJ control circuit 8 and all circuits 84N formation J 0 Next, to the 1st PA 7J < 7ii a 19 iiF; test kg
% Wash(/,)! IIIJ Sakukin 2nd Deposit 2nd Time Chart Full Month 4 Explanation - No Ru. Human cover turn memory circuit 2 jJ-yo and Tomo Samurai pattern memo January r! For the circuits, there are 1, "1b" of 1, "1b"
Each pattern data is programmed in advance. The input butter 7, relay 1, river path 2 outputs the 1liil+tI4 signal outputted by the control circuit 8, and the data programmed at the timing of 1 in succession Ai. The data is converted to an operating level by the human power signal conversion circuit 3 and supplied to the failure test circuit β"i'+1. That is, the circuit under test 10 operates according to the programmed human power pattern C, and its 1f1 filling υvJ As a result of the operation, the test 1 detection power signal a is output. On the other hand, the limit power supply 5 is set in advance to the threshold level (high limit LB, low limit C) of the circuit under test 1, and the comparator circuit 4 is set to the test output signal 8
It compares with high limit b and low limit C and outputs a high comparator signal -Qd and a low comparator signal e. At the same time, the Expected Pattern Memo January 4th Road 6 is also the same υ
All expected value signals 9 are output at the timing of 1 signal Ji4if. Comparison judgment circuit 7, at the timing of judgment strobe 11, if the previous = self-expected value signal g is the logic I novel "11", the high comparison signal d is %, and if the logic level is 1], the low comparison signal Toy, '4 bow e is theory 1': jj
It is fully determined that the level is "I-1,'. In other words, the pass/fail is determined according to the expected pattern data in which the test output 1 item a is programmed and whether the argument Jail fails or not. In this way, The conventional logic function test equipment 1ffi tests a circuit under test that outputs two-valued logic. However, with this If there is a function to output the 1RunJill value, it is necessary to change the threshold level using the limit signal ξ and conduct the test many times with the same person cover turn. The test operation of one path under test that outputs ternary logic using such a conventional logic function testing device will be explained using drawings. Figures 3 and 4 show ternary logic 3 is a time chart for explaining the test operation of a conventional logic function test device for a digital IC having 111 power functions. Then, by testing with the same input pattern under the conditions of high limit b, low limit C and expected value signal g shown in Figure 4, the three-value logic output It can be determined that the intermediate level is being output as expected.In this way, conventional logic function test equipment has to reset the limit power supply and all expected patterns n-1 times for the circuit under test with n-value logic output. It is necessary to repeat the test, which increases the test time by a factor of n-1.Also, there is a drawback that the expected pattern is complex and difficult to understand. The object of the present invention is to provide a logic function test device that can reduce the test time. 6. In other words, the present invention overcomes the drawbacks of 1' kJ convex, 'id; and provides a logic output function of 3 or more values. An object of the present invention is to provide a logic function test device that can perform pass/fail judgment in a test time of TT-J-1 in a logic function test of a digital IC. Logic function test device of the present invention〆r &, I: ,+1 logic function test device of digital IC having a logical value output function
In the IL test, the test subject [111 to be tested/comple's human power (+-j to supply 4) - the means of supplying Test output output from the circuit
If a judgment signal is output for each logical value of , the comparator means (M number σ), the conversion means for converting into a binary conversion signal corresponding to the previous i self publication (November Isuwa 2), and s −11
1f fil; 2 r corresponding to the logical value of the test output signal
11! The L storage means that stores the expected value signal of the candy, and the previous 1 self 211 ft conversion 1M and l! If N, the ratio to compare and judge with the expected value signal is t'r! , '1・1と、前i
The supply of the own input signal and the waiting value A, January's 111 force F, - and the previous day's comparison judgment are immediately 1 at the same timing.
The apparatus includes control means for supplying a synchronization signal to be generated. That is, the logic function testing apparatus of the present invention includes means for supplying all human signals to operate the functions of the circuit under test, means for outputting all judgment signals for each logical value, and any one of the judgment signals. a converting means for outputting binary value data corresponding to the logical value; a means for memorizing an expected pattern in advance using binary data corresponding to the logical value; and comparing and determining the binary output value from the converting means and the expected value. and a control means for operating at the same timing for comparing and determining the outputs of the input Gj and the expected value. Next, embodiments of the present invention will be explained in detail with reference to drawings I.
FC will be explained. FIG. 5 is a block diagram showing one embodiment of the present invention, and in particular, is a block diagram including a logic function test apparatus A' for testing a digital IC having a ternary logic output function. In FIG. 5, functional parts that are the same as those shown in FIG. 1 are designated by the same numbers. , comparator circuits 41-43: birizzutto'ungen 51-5
3 is the output logic of the circuit under test 1 (if number wraps repeatedly, 3
It is equipped with a binary conversion circuit 9' (t7) which converts the output signals of the comparator circuits 41 to 43 into binary data, and one expected pattern memory circuit fi. 'J'-, ↓ and comparison/judgment circuit 7' function using binary data.Next, the test operation based on the logic function test value IKtA'VC shown in Fig. 5 is shown in Fig. 6. An explanation will be given using time data.The circuit under test 1 is supplied with an input signal of 11 grams in advance. Threshold level of output logic value (high limit!・l), ~h, , r
+ -IJmitsutoC, -C,) respectively set 1st, comparator

[/-data circuits 41 to 43 compare whether or not the level of the previous test output value A is within the range of the limit level or not, and use the comparison signal as l -K 3 '6r
Output. It's a size. The binary conversion circuit 9 converts the comparator signals 1 (1 to 1 (3)
9- has priority, and the signal with higher priority has logic level'
)-1', it is converted into a corresponding 2-bit binary conversion signal mO,n]l. The expected pattern memory circuit 6' is programmed in advance with binary data corresponding to a logical value and outputs the expected value signal g at the timing of the synchronization signal f. + EI Outputs I. The comparison/determination circuit 7' compares the previous binary conversion signals mo, ml and the expected value signal g at the timing of the determination strobe 1. . Determine whether gl matches. As described above, since the logic function test device of the present invention has a plurality of comparators, the output logic level of the circuit under test is compared by each comparator and the pass/fail of the successive level is determined. Whereas it was necessary for the device to repeat the test n-1 times for a circuit under test having n logical values, only one test is required, resulting in a significant reduction in test time. Yes, it is shorter than the expected pattern used in conventional logic function testing equipment. Another advantage is that pattern data can be created using an easy-to-understand program.

[Brief explanation of drawings]

FIG. 1 is a block diagram including an example of a conventional logic function test device f(r), and FIG.
The value logic output test jbIj is 1 (? Explanation/completion time chart, Figures 3 and 4 V;
Examination in C! jl+saku hI? , a time chart for clarity, 51st column 1 is a block diagram including Embodiment 4 of the present invention, and FIG. 6 is a time chart for explaining the present invention.
(pHtic: Fr 3 (+/F complete explanation of logic output test operation -i)/Full explanation of test operation of f logic output - I)/F-much yard. 1...Circuit under test, A, , A'...Logic machine 11 )]Test device t, 2...Input pattern input circuit, :t...Input signal conversion circuit, 4.41-11;
; ・:I comparator circuit, 5, 51 to 53 ・Limit'1 (L source, (i, (i'...1υ
1 waiting pattern memory circuit, 7, 7'--11', 1
llQ tll'+i゛ circuit, 8...jt control circuit. a...Test output signal, b, h, , 13.
, l),...High limit* cI cI +
02 + cS"'""-Rimi, 1., d--High comparison signal, e...Low comparison signal, f...IUI period signal, g, g,, g, -・Expected value signal, h...judgment strobe, 1, 2
．． 3. Comparator signal, Iη0. ml... 2
Hex conversion signal month.

Claims (1)

[Claims] In a logic function test of a digital IC having a plurality of logical value output functions, a human power means capable of supplying all human power signals to test all circuits under test, and a test output from the circuit under test in accordance with the human power signals. a comparator means for outputting a judgment signal for each logical value of the output (j-), a converting means for converting one of the judgment signals into a binary conversion signal, In contrast to the logical value of the sleep output signal, the expected signal of the 2 null value is 1 in i, and the previous 1j binary conversion (i and previous d expected signal and gold judgment) and a control means for supplying a synchronization signal so as to operate at the same timing as the supply of the human power signal, the output of the forward bending value signal, and the m-ratio 1 bite determination. Characteristic logic function test device ρ