JPS5878464A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the insulated gate type semicoductor device having a high voltage resisting silicon gate structure without major change in general manufacturing processes of the silicon gate structure. CONSTITUTION:On the main surface of a p type silicon substrate 11, active regions (source, drain, and gate regions), which are separated by a field oxide film 12, are formed. Then, an n<-> type region 15, which is a drain region required for high voltage resistance, is formed. Then a polycrystal silicon pattern 16 is formed. With the pattern 16 as a mask, a thermal oxide film 13 is etched away. A gate oxide film 17 having a thickness of about 1,000Angstrom is formed on the exposed surface of the active region, and a thick silicon oxide film 18 is formed. Then the patterning of a gate electrode 19 is performed. With the electrode 19 as a mask, the gate oxide film 17 is etched away. Then with the electrode 19 as a mask, an n<+> type source region 20 and an n<+> type region 21 of a drain region 22 are formed in a self-aligning mode with respect to the gate electrode 19.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an insulated gate field effect semiconductor value pot having a silicon gate structure.

The power supply voltage of insulated gate field effect semiconductor @t (hereinafter referred to as MISll semiconductor device) tends to decrease more and more KT
However, on the other hand, devices that still require high voltage operation form the minute hand of MIa type semiconductor devices. And high voltage-t'l1 production, 6M18m! Drain breakdown voltage is a problem in semiconductor devices, and in order to increase this drain breakdown voltage, a silicon oxide film is used as the gate insulating film in MIa type semi-circular casting equipment with an aluminum gate structure, which has been conventionally adopted in MOa type semiconductor devices. The structure shown in Figure 1 is shown in Figure 1.

In FIG. 1, 1 is a P-type silicon substrate. The P-type silicon substrate IK has an n-shaped source region 2, a drain region formed of an n-shaped region taS and an n-type region 4 with a small diffusion depth provided in contact with the channel side thereof. There is. A thin gate oxide 11g is formed on the surface of the channel region of the silicon cover plate 1, and the surface of the silicon substrate 1 other than the i9 channel region is covered with a thick silicon oxide film 7. This game)lIHEIIEj
A gate electrode 1 consisting of an aluminum pattern is formed thereon, and on the other hand, source regions 2 . Nine aluminum mesh patterns a9, 9 are formed in ohmic connection with the n medium-sized region 4 of the drain region 5.

On the other hand, 1 MO8 with a normal aluminum gate
The structure of the W1 semiconductor device is as shown in Figure 'a2. In this figure, the same parts as in FIG. 1 are given the same reference numerals.

As is clear from a comparison of the structures in FIGS. 1 and 2, the MOa semiconductor W in FIG. 1 is different from the one in FIG. However, as will be described next, the existence of this n-type region 4 improves the drain breakdown voltage. The breakdown development between the drain region and the PM1v9 conductive substrate I is caused by the area 1 where the strongest electric field is large at the Pn junction between them.
This occurs in the shallow junction portion under the gate electrode 8, where the influence of voltage application by the gate electrode 8 is greatest. This is generally called surface breakdown, but the second
In the structure shown in the figure, the junction where surface breakdown occurs is a P+ n junction, whereas in the structure shown in Figure 1, the junction where surface breakdown occurs is a Pn junction.
It becomes a junction. Therefore, in the structure shown in FIG. 1, the depletion layer at the junction where surface breakdown occurs spreads further inside the drain region 5 than in the case shown in FIG. Therefore, the electric field strength in the depletion layer decreases accordingly, and the surface breakdown voltage increases. In addition, n in the form of surface breakdown or channel current
When a current flows at the tip of the type region 4, the potential at the tip of the n-type region 4 becomes lower than the drain/applied voltage due to a voltage drop in the shallow n-type region 4 with high resistance. Due to the above two reasons, the MOg type semiconductor shown in Figure 1! Electric and M in Figure 2
In an Og type medium conductor device, the structure shown in FIG. 1 with the same effective channel length can withstand a higher drain voltage type.

Incidentally, in recent high-density variable integrated circuits, the so-called silicon gate structure using polycrystalline silicon has become mainstream rather than the aluminum gate structure. Therefore, there is a great need to apply the structure shown in FIG. 1 to a semiconductor device having a V9 conjugate structure. In this case, a manufacturing method must be established that does not impair the general features of the manufacturing process of silicon gate structures.

The present invention has been made in view of the above circumstances.

Figure 1: A method for manufacturing a semiconductor device that can achieve improved breakdown voltage with a similar structure and obtain an insulated gate field effect semiconductor device with a northern silicon gate structure, and that does not require major changes to the manufacturing process of the silicon gate structure. This is what we provide.

That is, one aspect of the present invention is to provide a diffusion layer having a conductivity type opposite to that of the substrate with a low concentration change and a shallow diffusion depth of 1 in at least the drain side portion on both sides of the expected channel region in the element region of a semiconductor substrate having a -conductivity type. A step of forming a first impurity region, a step of forming a polycrystalline silicon butter covering the first impurity region, and a step of thermal oxidation (to grow a gate oxide film on the exposed surface of the element Q4 and to remove the polycrystalline silicon butter) A step of oxidizing the crystalline silicon pattern to form an oxide film thicker than the gate oxide film on the first impurity region, and a polycrystalline silicon layer covering the first impurity region from the channel region region. A step of forming a gate electrode, and a second impurity region with a high g11f and a deep diffusion depth that becomes a source region by doping with an impurity of a conductivity type opposite to that of the substrate using the 1wI gate electrode as a mask, and the first impurity region. III, which is connected to the impurity region and becomes a drain/region together with the impurity region.
9. A method of manufacturing a semiconductor device, comprising a step of forming a third impurity region having a Ii concentration and a deep diffusion depth.

An embodiment of the present invention will be described below with reference to FIGS. 3(II) to 3(f).

In the example, first, a well-known selective oxidation method is applied to the main surface of a P-type silicon substrate 1 to form field oxides 1 and 12. , drain and gate regions) are formed (
FIG. 3(a) (illustrated).

(11) Next, thermal oxidation is applied to the surface of the active region with a film thickness of 100%.
After forming the OA thermal oxide film 13, a resist film J-y 14 having an opening on the planned nil region of the drain region necessary for a high breakdown voltage structure is formed. The acceleration voltage was 150 KeV using the #resist pattern 14 as a mask.

Phosphorus is ion-implanted at a dose of lXl0”/- (
The same figure (crow shown in b).

(Jilt) Next, the resist pattern 14 is removed.

The n-type region 1 of the drain/region necessary for high breakdown voltage is formed by heat treatment to activate the previously ion-implanted phosphorus.
form 5. Subsequently, polycrystalline i/
After depositing a silicon layer, the polycrystalline silicon layer is patterned to leave a polycrystalline silicon pattern 16 with a thickness of 150 OA on the n-type region 15.

At this time, the end of the polycrystalline silicon pattern Ill is n-
The thermal oxide film 13 is desirably located slightly inside the mold region #15. Next, the thermal oxide film 13 is removed by etching using the polycrystalline silicon pattern 16 as a mask (see figure c1).

Note that plasma etching using a resist pattern as a mask may be used to form the polycrystalline silicon pattern 16.

IVI Next, dry oxidation is performed at 1000° C. for 250 minutes, which results in a film thickness of about 1 mm on the exposed surface of the active region.
A gate clearing layer 11 of 0.000 mm is formed, and at the same time, the polycrystalline silicon pattern 16 is quantified and converted into a silicon oxide layer. As a result, a thick silicon oxide @1tt with a film thickness of 400 OA is formed on the n-type region 15 (as shown in FIG. 1d1).

(Vi) Next, a film thickness of 3000% was applied to the entire surface by CVD method.
After depositing the polycrystalline silicon layer A, it is patterned to form a gate electrode 19, and then,
Using the gate electrode 19 as a mask, gate oxidation gir
y is removed by etching (see figure e1).

At this time, the gate electrode 19 is patterned to cover the intended channel area and the thick silicon oxide film 18 as shown in FIG.

(V-Next, phosphorus is diffused using the gate electrode 19 as a mask, and the n medium-sized source region 2o and drain/region 2J are
The n medium-sized region 21 is formed in a self-aligned manner with respect to the gate electrode 19 (FIG. 2(f)).

At this time, if the end of the thick silicon oxide film 11 is located inside the n-type region 15 as described above, the n-medium region 21 of the drain region 2-2 and the n-type region will be connected and formed.

(vl) Next, CVD-8 is applied to the entire surface as an interlayer insulating film.
After depositing 10,1ljJ, contact holes are opened, aluminum is evaporated and patterned to form an aluminum arrangement 1124°24, thereby obtaining an MOa type semiconductor device with a silicon gate structure (see FIG. g) As shown).

The thus obtained MO8 type semiconductor device with silicon gate structure shown in FIG.
It has all the necessary structural requirements to achieve high breakdown voltage and can therefore withstand high drain voltages.

By the way, in the MOa type semiconductor devices shown in FIGS. 1 and 3(g), a thick oxide film is formed on the n-type region in order to prevent the voltage of the gate electrode from affecting the n-type region of the drain region. It is necessary to intervene. In the manufacturing process of the silicon gate structure, the problem is how to form this thick oxide film, that is, the thick silicon oxide IIJg. This is similar to the manufacturing process of the aluminum gate structure, as shown in Figure 4 (ms (bl), a thick heat-deposited film 1g' is formed on the entire surface, and then this is selectively etched to form a thick silicon oxide film 11EJJt. However, in this case, there is a problem that it takes a long time to grow 1g' of thick thermal oxide film, and also because only a thin thermal oxide film grows on the oxide pattern under the fiber. There is a problem in that the field oxide film 12 is etched and becomes thinner during selective etching.

On the other hand, if the method of oxidizing the polycrystalline silicon pattern 16 by dry oxidation to form a gate oxide layer is used as in the above embodiment, the above problem does not occur.

Note that in the MO811 semiconductor device, the 4th fin 111
Not only 11 go but also so. - High breakdown voltage may be added to the junction on the source side, but according to the present invention, a silicon gate structure with a similar high breakdown voltage structure on the source side is also used.
Oa type semiconductor devices can be manufactured.

91. The present invention is applicable not only to n-channel.

Needless to say, the present invention can also be applied to manufacturing a P-channel MOa type semiconductor device having a similar structure.

As described in detail above, according to the present invention, an insulated gate semiconductor device with a 9V recon gate structure can be manufactured with a high withstand voltage structure without requiring a major change in the general manufacturing process of a silicon gate structure. '4-fi can provide a method for manufacturing a semiconductor device that can obtain □.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing an MOa type semiconductor device with a high breakdown voltage structure on the drain side and an aluminum gate structure, and Fig. 2 is a cross-sectional view of an MOa type semiconductor device with an ordinary aluminum gate structure without a high breakdown voltage structure.
A cross-sectional view showing an a-type semiconductor device, FIG. 3 Ca) to (g) are cross-sectional views showing a manufacturing process according to an embodiment of the present invention, (bl is FIG. 3 1 m) to (g) FIG. 3 is a cross-sectional view showing main parts in the manufacturing process of a comparative example with respect to the example. 11. Il+ p-type silicon substrate, rz...field blurring, 13.. thermal oxide film, 14.. resist pattern, 15.''-n type region, 16. axial striated crystal silicon pattern, xr -... Gate ambiguity, 18 - Thick silicon oxide 11. J9... Gate electrode, 20...
- Nsu region, 21... n medium-sized region of the drain region. zz-Yv4 region, zs-CVD-810, membrane. 24.--Aluminum wiring.

Claims (2)

[Claims] (1) - A step of forming tal impurity regions having a conductivity type opposite to that of the i-substrate with a low concentration and a shallow diffusion depth on at least the drain side portions on both sides of the intended channel region in the element region of the semiconductor substrate having a conductivity type; , forming a polycrystalline silicon pattern covering the first impurity region, growing a gate oxide film on the exposed surface of the device region by thermal oxidation, and oxidizing the polycrystalline silicon pattern to remove the impurity 1111. forming an oxide film thicker than the gate oxide film on the region; forming a gate electrode made of a polycrystalline silicon layer covering the first impurity region from the planned channel region; A second impurity region with a high diffusion depth of 11 degrees and a deep diffusion depth is doped with impurities having a conductivity type opposite to that of the substrate using the mask as a mask, and is connected to the second impurity region with a high diffusion depth of 11 degrees and a deep diffusion depth, which becomes the source region, and the drain region together with the impurity region. A semiconductor device and a manufacturing method characterized by comprising a step of forming a third impurity region with a high concentration and a deep diffusion depth. (2) A method of manufacturing a semiconductor device according to claim 3, characterized in that the polycrystalline silicon pattern is formed such that its end in the channel length direction is located inside the first impurity region.