JPS5878240A - Data processing device having program memory - Google Patents

Data processing device having program memory

Info

Publication number
JPS5878240A
JPS5878240A JP56176036A JP17603681A JPS5878240A JP S5878240 A JPS5878240 A JP S5878240A JP 56176036 A JP56176036 A JP 56176036A JP 17603681 A JP17603681 A JP 17603681A JP S5878240 A JPS5878240 A JP S5878240A
Authority
JP
Japan
Prior art keywords
rom
address
contents
section
program memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56176036A
Other languages
Japanese (ja)
Inventor
Takao Kamisuzu
神涼 隆男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56176036A priority Critical patent/JPS5878240A/en
Publication of JPS5878240A publication Critical patent/JPS5878240A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring

Abstract

PURPOSE:To output the contents of an ROM to the outside and to protect the security of a program, by detecting an optional specific address given to the ROM and changing the contents of the program read out from the ROM when this specific address is detected. CONSTITUTION:A data processing unit consists of a CPU part 1 where a one- chip microcomputer is connected to an internal data bus 5, an RAM part 2, ROM part 3, and input/output circuit part 4, and the CPU part 1 and the ROM part 3 are connected by an ROM address bus 6. The ROM part 3 is provided with an ROM cell part 11 and address detecting circuit part 12 which are connected to an address bus 15, and an ROM output circuit part 13 is connected to the cell part 11 and the circuit part 12. A specific address given to the cell part 11 through the bus 15 is detected by the circuit part 12; and when this specific address is detected, the contents of the cell part 11 are changed and are outputted to an internal data bus 14 from the circuit part 13, thus protecting the security of a program.

Description

【発明の詳細な説明】 本発明はプログラムメモリを日賦したデータ処理装置に
関し、管にフログラムメモリに誓さ込まrt、*プログ
ラムを第3者が容易に利用出来ないような秘智保持機能
をもったデータ処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that stores a program memory, and has a secret-keeping function that prevents a third party from easily using the program. The present invention relates to a data processing device.

従来絖み出し専用メモリ(以下、R(JMという)にプ
ログラムを記憶したデータ処理装置の代異としてlチッ
プマイクロコンピュータがある。こ扛はi(、(7M内
容、O検査やプログラムデ/(ラグのためにR(7M内
容を外部端子へ出力できるような回路’t4している場
合が多い、しかしながらこの機能を有している挙によっ
て、第3省によって容易にhuMO内谷を知られて利用
さrしると言う欠点が有る。又h(JMの内容を外部端
子に出力する機能″fr:秘曽保持Oために削除すると
、九〇Mの内容がテスト不可能となりマイクロコンピュ
ータの選別時の不良恢出単が低下する。
There is an l-chip microcomputer as an alternative to the conventional data processing device that stores programs in a memory (hereinafter referred to as R (JM)) dedicated to alignment. Due to the lag, there are many cases in which a circuit that can output the R(7M contents to an external terminal) is installed. However, by having this function, huMO Uchitani is easily known by the It has the disadvantage of being overused.Also, if the function to output the contents of JM to an external terminal is deleted for security reasons, the contents of 90M will become untestable and the selection of microcomputers will be difficult. The defective yield of the time decreases.

本党明υ目的はKOM0M内容部へ出刃する機能を有し
7’C”ffi”!で、ROMに誓き込まnだプログラ
ムの装置保持機能をもったデータ処理装置を提供するこ
とにるる。
The main party's purpose is to have the ability to attack the KOM0M content department and 7'C"ffi"! Therefore, the present invention aims to provide a data processing device having a function of storing n programs stored in a ROM.

本発明はROM内w、olチ、グマイクロコンピュータ
においてkL(JM部に供給されるR(JMアドし哀の
うち特定のアドレスを有し、この特定アドレスと11.
(JM検査蒔にKUMへ与えらnるアドレスとを比較し
1両者が一致している時にはその時読み出さnる′kL
OMの内容を強制的に及更する出力回j!+8′fr含
む。
The present invention has a specific address among the R(JM addresses) supplied to the kL(JM section) in the ROM in the microcomputer, and this specific address and 11.
(Compare the address given to KUM in the JM test and if the two match, then read n'kL
Output time to forcibly change the contents of OM! +8'fr included.

次に本発明の一部り例について図面を参照して説明する
Next, some examples of the present invention will be described with reference to the drawings.

第1図は本発明によるlチク1マイクロコンビ、−po
ブa、、/構1i1.IgでhD、CLJPii、 ′
kLAM部2.RUM部3%人出力1路部4が1チツク
上に集積化さnて靭成さn、内部データバス5によって
互いに接続さnている。またCPU@1よりR(JMア
ドレスバス6が80M部に供給さnている。第2図は本
来施例の80M部の一部をよシ詳細に説明したブロック
図でおる。図から明らかなように九(JMセル部11.
アドレス検出回路部12.凡OM内谷出力回路部13と
を含み、アドレスバスがi&(JMセル部11とアドレ
ス検出回路部12とに供給さγしるように配線さnてい
る。
FIG. 1 shows the l-chiku-1 microcombination according to the present invention, -po
Bua,,/structure1i1. Ig with hD, CLJPii, ′
kLAM section 2. The RUM section 3, output section 4 is integrated on one chip, and connected to each other by an internal data bus 5. In addition, the R (JM address bus 6) is supplied from the CPU@1 to the 80M section. Fig. 2 is a block diagram explaining in detail a part of the 80M section of the original embodiment. Yoniku (JM cell part 11.
Address detection circuit section 12. The address bus is wired such that the address bus is supplied to the JM cell section 11 and the address detection circuit section 12.

アドレス検出回路部12からはアドレス一致時にに印加
さnるよりになさ扛ている。本来施例の基本的な動作H
e)’Li部lより出力さnたルOMアドレスによって
決定さ扛るR(JM3内の命令によってCPU部1が動
作する。この時ROM部3にプログラムさnた内容はア
ドレス指定さnて九〇Mセル部11から出力回路13と
は別の鮭路金経てePu部lに供給さnる。
The address detection circuit section 12 applies no more than n when the address matches. Basic operation H of the original example
e) The CPU section 1 operates according to the command in JM3, which is determined by the OM address output from the Li section 1. At this time, the contents programmed in the ROM section 3 are specified by the address. The signal is supplied from the 90M cell section 11 to the ePu section 1 via a circuit separate from the output circuit 13.

本央抛例によるとh(JM検食時にアドレス検出U%に
プログラムさnycアドレスと同じアドレスがCPυ部
lよりアドレス検出回路部に印加さnるとアドレス検出
回路部から九〇M出力tblJ御イぽ号16が九(JM
出力回路13に印加さnて、九(JMセル部11から読
み出さnた命令と違う命令を出力−wr13によって作
り出す。従って、アドレス恢出1gl路に設定した特定
アドレス全知らない第3省がR(JMのアドレスを指定
しても、正常お内容を知ることはできない。
According to this example, h (when the same address as the nyc address programmed into the address detection U% during JM inspection is applied from the CPυ part l to the address detection circuit part n, the address detection circuit part outputs 90M tblJ control Ipo-go 16 is nine (JM
The input signal is applied to the output circuit 13, and an instruction different from the instruction read from the JM cell unit 11 is generated by the output -wr13. (Even if you specify the JM address, you cannot know the normal content.

即ち、マイクロコンピュータの使用者が任慧に前記ブト
レス検出回路のアドレスをROM部へのプログ2ム誉込
み時と同時にプログラムする事により、itOM部の内
容を外部端子へ出力する機能が有ってもi−LCJM部
のプログラムの秘密保持が達成できる。又、前記アドレ
ス検出回路部に設定さnるアドレスOvlを複数個用意
すると、よシ強い秘冨保持が可能となる。同、冥除の使
用者が80M部の内容を外部端子に出力する時扛アドレ
ス検出回路のアドレスを知っているため、七〇によって
異なろR(JM内答が出力さnたとしても正常の内容を
知ることは容易でめる。同、前記アドレス検出回路部の
動作を糸上して14(3M部の内谷通りの出力を外部へ
出力するようにしてもよい41扛盲う筐でもない。
That is, the microcomputer user has the ability to output the contents of the itOM section to an external terminal by programming the address of the buttress detection circuit at the same time as writing the program into the ROM section. It is also possible to maintain the confidentiality of the i-LCJM department's programs. Further, by preparing a plurality of n addresses Ovl to be set in the address detection circuit section, it becomes possible to maintain strong confidentiality. Similarly, when the user of the Meiyoke outputs the contents of the 80M part to the external terminal, he knows the address of the address detection circuit, so it may vary depending on the 70 (even if the JM internal answer is output, it is normal). It is easy to know the contents.In the same way, the operation of the address detection circuit section can be explained in 14 (the output of the Uchitani street of the 3M section may be outputted to the outside). do not have.

又、ROM部のプログラム6答の秘密保持のうえで、l
チップマイクロコンピュータυ外−を顕I&鏡等でm察
する拳によりわかる方法で前8dアドレス検出回路4C
特定アドレスをプログラムす名j−pは、イオン注入技
術等外観上の違いの生じない方法でプログラムする串に
よりより確実になる挙・はあらためて説明するまでもな
、い。
In addition, in order to maintain the confidentiality of the ROM department's program 6 answers,
The front 8d address detection circuit 4C can be detected by checking the outside of the chip microcomputer υ with a microscope and mirror.
There is no need to explain that the specific address can be programmed more reliably by using a method such as ion implantation technique that does not cause any difference in appearance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の1チツプマイクロコンピユ
ータのブロック構成図でろv、第2図祉第λ図の80M
部のより詳細なブロック構成図である。 l・・・・・・CPU部%2・・・・・・RAMg、3
・・・・・・i−1,(3M部、4・・・・・・入出力
回路部、5・・・・・・内部データバス、6・・・用ア
ドレスバス、11・・・・・・i−L(JMセル部。 12・・・・・・アドレス検出回路部、13・・・・・
・I(、(JM出力回路部、14・・・・・°内部デー
タバス、15・・・・・・アドレスバス、16・・・・
・・R(JM出力制御信号。
Figure 1 is a block diagram of a one-chip microcomputer according to an embodiment of the present invention.
FIG. 3 is a more detailed block configuration diagram of the section. l...CPU section %2...RAMg, 3
....i-1, (3M section, 4 .... input/output circuit section, 5 .... internal data bus, 6 ... address bus, 11 .... ...i-L (JM cell section. 12...Address detection circuit section, 13...
・I(, (JM output circuit section, 14...°internal data bus, 15...address bus, 16...
...R (JM output control signal.

Claims (1)

【特許請求の範囲】[Claims] プログラムメモリと、このプログラムメモリの内容を外
部へ出力する制御回路とをMするデータ処理装置におい
て、前記プログラムメモリに与えら扛たアドレスのうち
ttX&−)%定アドレスを検出、する手段と、前記v
斌アドレス悦出手段によって特定アドレスが恨邑さnた
時は前記ツーログツムメモリから読み出される内容全変
化する手段と會具備することを%徴とするプログラムメ
モリ會有するデータ処理装置。
In a data processing device having a program memory and a control circuit for outputting the contents of the program memory to the outside, means for detecting a ttX&-)% constant address among the addresses given to the program memory; v
A data processing device having a program memory, characterized in that the program memory comprises means for changing the contents read from the two-log memory when a specific address is detected by the instant address display means.
JP56176036A 1981-11-02 1981-11-02 Data processing device having program memory Pending JPS5878240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56176036A JPS5878240A (en) 1981-11-02 1981-11-02 Data processing device having program memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56176036A JPS5878240A (en) 1981-11-02 1981-11-02 Data processing device having program memory

Publications (1)

Publication Number Publication Date
JPS5878240A true JPS5878240A (en) 1983-05-11

Family

ID=16006597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56176036A Pending JPS5878240A (en) 1981-11-02 1981-11-02 Data processing device having program memory

Country Status (1)

Country Link
JP (1) JPS5878240A (en)

Similar Documents

Publication Publication Date Title
JP3124278B2 (en) Inspection method of memory cell contents of program memory
JPS6055857B2 (en) How to identify memory
JPS5878240A (en) Data processing device having program memory
JPS6319901B2 (en)
US5497481A (en) Microcomputer computer system having plural programmable timers and preventing memory access operations from interfering with timer start requests
JPS61182150A (en) Memory trouble detecting system for microprocessor system
JP2978658B2 (en) Program development support device
JPS6260035A (en) Artificial trouble generation system
JPH01286028A (en) Microprogram patching system
JPH03211619A (en) Data processor
JPH01162094A (en) Key telephone system
JPS59226955A (en) Program debug device
JPH0619631A (en) Initialization system for storage device
JPH10333992A (en) Flash memory write data and flash memory loading equipment
JPS62293582A (en) Memory device
JPS5918798B2 (en) memory device
JPS6284500A (en) Microcomputer
JPH0353370A (en) Parallel processor for information processor
JPS59133613A (en) Software verifying method of process controller
JPS60549A (en) Memory testing system
JPS59128619A (en) Microcomputer device
JPH03175538A (en) Duplex processor
JPH05274284A (en) Recognizing device for inter-processor communication
JPS6284341A (en) Address coincidence detecting circuit for inputting/ outputting device
JPS59123054A (en) Initial detecting system