JPS5875915A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To obtain hysteresis width by performing selective channel doping for gates of inverters applied with an input signal. CONSTITUTION:An input signal is supplied to inverters 11 and 12 in parallel. Those inverters 11 and 12 have C-MOS structure obtained by connecting a P- MOS transistor (TR) and an N-MOSTR in series. For the gate of TRs constituting the inverter 11, channel doping is carried out. Therefore, the inverters 11 and 12 have difference input and output voltage transfer characteristics. Owing to the difference in characteristics, hysteresis width is obtained. Therefore, the gate size of each TR is unchanged, so the chip area is unchanged and reduction in size is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a C-MOS Schmitt trigger circuit used for shaping voltage waveforms having noise or the like or for configuring a stable multivibrator circuit.

When a Schmitt-Tori circuit is constructed using C-MOS, an input signal is supplied to a pair of inverters, and
The outputs of this pair of inverters are configured to provide a logical output. In this case, the input/output voltage transfer characteristics of the pair of inverters are set as shown in FIGS. 1 and 2, respectively, and a Schmitt trigger circuit having a hysteresis width as shown in FIG. 3 is constructed. It is intended to do so. Here, the input/output voltage transfer characteristics of other circuit parts are μ■Dil, and the negative side power supply voltage is VB8 (=OV),
Let the positive side power supply voltage be VDD.

The inverter that makes up the above Schmitt trigger circuit is
Normally, P-MO8) Rannostar and N-MOS) transistors are connected in m columns between the power supplies ■DD and vss, and an input signal is supplied to r-) of both transistors, and from the interconnection part. Configure to extract an output signal.

Normally, when configuring an inverter using a C-MO8 circuit, the input and output voltage transfer characteristics of the input inverter of μ between the power supply voltages (vDD-■88) are set as the first In order to do as shown in Figures and Figure 2, P
-MOS) Set the Lanzostar channel width to the same (N-
The channel width of the P-MOS) transistor and the N-MOS) transistor constituting the other inverter are set to be larger than the channel width of the MOS) transistor, and the relationship between the channel widths of the P-MOS) transistor and the N-MOS) transistor constituting the other inverter is set to be opposite to the above. In other words, P-MOS transistors and N-MOS transistors that constitute the inverter
) By making the channel widths of the transistors different, the channel width of one transistor is intentionally made wider than the channel width of the other transistor, which inevitably results in a larger pattern size. Further, the hysteresis width shown in FIG. 3, which is determined by the input/output voltage f]2 transfer characteristics in FIGS. 1 and 2, is determined by the ratio of the pattern sizes of each of a pair of inverters. Therefore, in order to obtain a stable hysteresis width, complicated calculations and control of process parameters are required to manufacture this semiconductor device.

This invention was made in view of the above-mentioned points.
MO8) It is possible to set the input and output voltage transfer characteristics of each transistor and obtain the hysteresis width without changing the channel width of the transistor, and it is possible to obtain the hysteresis width effectively without increasing the pattern size. The present invention attempts to provide a Schmitt trigger circuit that facilitates centralization.

That is, the Schmitt trigger circuit according to the present invention is
Channel doping is selectively performed on the gates of P-MOS transistors and N-MOS transistors constituting the first and second inverters to which input signals are supplied in parallel, and Alternatively, the threshold voltage of the N-MOS transistor or both of these transistors may be changed to obtain a hysteresis width.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows its configuration, where input signals 1 and 2 are input to the first and second inverters 1 and 1, respectively.

12 in parallel, and the output signal from the second inverter 12 is further inverted by an inverter 13. The output signals from the inverters 11 and 13 are respectively supplied to NAND circuits 14 and 15, the output signal from the NAND circuit 14 is coupled to the NAND circuit 15, and the output signal from the NAND circuit 15 is coupled to the NAND circuit 14. Configure a flip-flop as follows, and convert NAND circuit 1
Output signal from 4■. This allows the UT to be taken out.

5- In such a circuit, the first inverter 1 to which the input signal is supplied is configured as shown in FIG. 5, for example. That is, between the power supplies ■DD and ■ss, there is a P-MOS
) Transistor 16 and N-MOS) Transistor 17 is connected by rotation, and the input signal 1N is coupled to the gate of both transistors 16.17, and the interconnection point of both transistors 16.17 is also connected. ■Output signal from. UT
The purpose is to take out the . In this case, P-MO
Channel doping is applied to each of the S) transistor 16 and the N-MOS) transistor 17 f-). However, in the following description, the channel dope is assumed to be a trivalent element such as boron.

On the other hand, the second inverter 12 is constructed by connecting a P-MOS transistor 18 and an N-MOS transistor 19 between the power supply vDD and the voltage source 88 in the same manner as described above, as shown in FIG. There is, but this transistor 1
Do not apply channel dope to the 8.19 date.

6- i.e. P-MOS with channel doping)
The input/output voltage transfer characteristics of the first inverter 11 composed of the transistor 16 and the N-MOS transistor 17 are as shown in FIG. 1, whereas the transistor 18. The input/output voltage transfer characteristics of the second inverter 12 configured with the inverter 19 are as shown in FIG. Therefore, in a Schmitt trigger circuit configured by combining inverters 11 and 12 having such input/output voltage transfer characteristics, a hysteresis width as shown in FIG. 3 can be obtained.

Generally, an inverter constituting a C-MOS is composed of a P-MOS transistor and an N-MOS transistor, as shown in FIGS. 5 and 6. Here, P− after channel doping to dirt
MOS transistor threshold voltage ■TP
Then, P− before channel doping is applied to the date.
The threshold voltage of the transistor (MOS) is [V
TP+ΔV,, j (However, Δ■TP is the variation before and after channel doping to the gate, and ■
It is known that TP and Δ''TP are positive values).

Furthermore, the threshold voltage before channel doping to the dirt of the N-MOS transistor is
Then, the threshold voltage after applying channel P-de to the gate is "■TN+Δ■TN" (ΔvT
It is also known that N is the variation between before and after channel doping, and ■TN and Δ■TN are assumed to be positive values.

In the following, the operating point of this C-MOS inverter is calculated and the hysteresis width is calculated. Now, when the output of the inverter is (DD-Vs8)/2, the P-MOS () transistor and the N-MOS () transistor that constitute the inverter are in the saturation region. At this time, the output current of the P-MOS) transistor is IP, N-
If the output current of a MOS (MOS) transistor is represented by the output current, then the following equations (1), (2), and (3) generally hold true.

IP=IN
...(3) However, ε. Gate oxide dielectric coefficient rox; Date film thickness wP; P-channel transistor channel width WN: N-channel transistor channel width IN S input voltage (V88 reference) μ, ; Mobility (P channel) μ, ; Mobility (N-channel) LP ; Channel length of P-channel transistor LN ; To simplify the calculation of the channel length of N-channel transistor, assuming KrV8.=OVJ, the above formula (1) (2) (3) Therefore, the following formula holds true.

9- In the above equation (4), if “α=1”, then “■
If TP=■TN'', then.

Now, in a C-MO8 circuit, the normal P-MOS transistor is channel-doped to r-), and the N-MOS transistor is not channel-doped to dirt. I'll think about it. Invert the output of the C-MOS inverter at this time (
The input voltage (for which the output voltage is VDD/2) is shown by equation (4).

Here, as described above, the first inverter 1110- is configured as shown in FIG.
2 is configured as shown in FIG.
The input voltages ■1NI and ■1N■ for inverting the respective outputs are as follows.

Therefore, the first inverter z1ij: exhibits an input/output voltage transfer characteristic as shown in FIG.
2 exhibits input/output voltage transfer characteristics as shown in FIG.

Then, using such inverters 11 and 12, the fourth
When the seamit trigger circuit shown in the figure is constructed, its hysteresis width becomes rV, -V2J, and the following equation holds true.

Here, the actual division is Δ■TN=Δ■TP−Δ■. However, Δ■7 is the change in threshold voltage that occurs in P-Mo8 due to channel doping. Therefore, . In this way, it is determined by the channel doping amount, without depending on the shape parameter α of Mo8. In other words, a hysteresis width with good reproducibility can be obtained.

In the embodiment shown above, channel doping is applied to each of the P-Mo8) transistor and the N-Mo8) transistor r-) constituting the first inverter 1,
P-R40S and N-Mo8 of second inverter 12
) The transistor r-t is shown without channel doping. However, the second inverter 12 is left as is, and the first inverter 11 is
8) A similar hysteresis width can be obtained by applying channel doping only to r-) of the transistor 17. Equation (7) in this case becomes as follows.

Contrary to the above case, P-Mo8 of the first inverter 11
) When channel doping is applied to the date of transistor 16, equation (7) becomes.

Further, the first inverter 11 is configured as explained in FIG. 5, and when channel doping is applied to the date of the p-Mo5) transistor 18 of the second inverter 12,
7) The formula is as follows.

On the contrary, when channel doping is applied to f-) of the N-MOS transistor of the second inverter 12, (7)
The formula is as follows.

That is, by selecting transistors to be channel-doped, Schmidt
Hysteresis can be obtained in the trigger circuit.

In the above embodiment, the output signals from the first and second inverters 11 and 12 to which the input signals are combined are taken out by the logic flip-flop output using the NAND circuit, as shown in FIG. The output may be taken out by a NOR logic flip-flop that combines the NOR circuits 20 and 21 and the inverter 22. Furthermore, as shown in FIG. 8, instead of using the flip-flop configuration, the OR circuit 23
, a NAND circuit 24, and an inverter 25 may be used.

As described above, according to the present invention, the input voltage ■, which inverts the output of each of the pair of inverters to which the input signal is supplied;
The 14-hysteresis width is obtained by selectively channel-doping the P-channel and N-channel Mo8) transistors constituting the inverter so that 2 is rv, -v2>o, 1. Yes 'i P-MOS
.

This allows a Schmidt-Tori circuit to be effectively configured without affecting the pattern size of each N-MOS transistor.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams showing the input/output voltage transfer characteristics required for a pair of inverters constituting a Schmitt trigger circuit, and Figure 3 is a diagram showing the hysteresis width required for the Schmitt trigger circuit. FIG. 4 is a configuration diagram illustrating a Schmitt trigger circuit according to an embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing specific circuits of an inverter used in the above embodiment, respectively. FIGS. 7 and 8 are block diagrams showing other embodiments of the present invention, respectively. 11...First inverter, 12...Second inverter, 16.18...P-MOS) transistor, 1
7.19...N-MOS) transistor. Applicant's agent 9F Takehiko Suzue 15- Figure 1 Figure 2 Figure 3 Figure 4 Figure 9-

Claims (1)

[Claims] In a circuit comprising first and second inverters to which input signals are supplied in parallel, and means for logically outputting the first and second inverter outputs, the first and second inverters are connected between power supplies. A P-MOS transistor) and an N-MOS transistor are connected in series, and the first and second p- constituting the second inverter
MOS) transistors and N-MOS transistors are selectively channel-doped, and the input voltages at which the outputs of the first and second inverters are inverted are made different so that a hysteresis width is formed between them. Seamit trigger circuit characterized by: