JPS5875401U

JPS5875401U - Commutation margin angle detection circuit

Info

Publication number: JPS5875401U
Application number: JP1981168942U
Authority: JP
Inventors: 上西　明
Original assignee: 三菱電機株式会社
Priority date: 1981-11-12
Filing date: 1981-11-12
Publication date: 1983-05-21

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の転流余裕角検出回路を示すブロック図、
第２図は第１図に示した転流余裕角検出回路の動作を説
明するためのタイミング図、第３　　　　′図はこの考
案の一実施例を示すブロック図、第４図は第３図に示し
た実施例の動作を説明するためのタイミング図である。ＭＴは変圧器、ＭＴＳ　ｌ〜ＭＴＳ　３は分割された。二次巻線、ＭＣＲ１〜ＭＣＲ３はサイリスタブリッジ整
流器、１は基準クロック発生器、２は電源同期信号発生
回路、３Ａ〜３Ｃは比較回路、４Ａ〜４Ｃはパルス化回
路、５はカウンタ回路、７は制御演算部、８はオア回路
、９はメモリ回路である。ＴＨ４上置　　　　　　　　乙第４図Figure 1 is a block diagram showing a conventional commutation margin angle detection circuit.
Fig. 2 is a timing diagram for explaining the operation of the commutation margin angle detection circuit shown in Fig. 1, Fig. 3' is a block diagram showing an embodiment of this invention, and Fig. 4 is similar to Fig. 3. FIG. 4 is a timing diagram for explaining the operation of the illustrated embodiment. MT is a transformer, and MTS 1 to MTS 3 are divided. Secondary windings, MCR1 to MCR3 are thyristor bridge rectifiers, 1 is a reference clock generator, 2 is a power synchronization signal generation circuit, 3A to 3C are comparison circuits, 4A to 4C are pulsing circuits, 5 is a counter circuit, 7 is a A control calculation section, 8 is an OR circuit, and 9 is a memory circuit. TH4 Upper part Otsu Figure 4

Claims

[Scope of utility model registration request]

A transformer in which the secondary winding is multi-divided;
A thyrisk bridge rectifier connected to each of the next windings, a reference clock generator, a power synchronization signal generation circuit that generates an output pulse at the zero point of the power supply voltage, and a voltage between the input terminals of each of the thyrisk bridge rectifiers. a plurality of comparison circuits that generate a signal when the voltage is positive; a plurality of pulsing circuits that generate a pulse signal synchronized with the output pulse of the reference clock generator when the signal of each comparison circuit rises; and the power source synchronization circuit. A single counter circuit that performs counting by applying the output pulse train of the reference clock generator from a preset value for each output pulse of the signal generation circuit, and an output pulse of one of the plurality of pulse generators is generated. A commutation margin angle detection device comprising: a memory circuit that stores both all the signals of the plurality of pulsing circuits and the value of the counter circuit at the time when the output pulse is generated. circuit.