JPS5875251A - Malfunction detecting circuit - Google Patents

Malfunction detecting circuit

Info

Publication number
JPS5875251A
JPS5875251A JP56172231A JP17223181A JPS5875251A JP S5875251 A JPS5875251 A JP S5875251A JP 56172231 A JP56172231 A JP 56172231A JP 17223181 A JP17223181 A JP 17223181A JP S5875251 A JPS5875251 A JP S5875251A
Authority
JP
Japan
Prior art keywords
control signals
signal
control signal
exclusive
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56172231A
Other languages
Japanese (ja)
Inventor
Tetsuo Kanai
金井　徹郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56172231A priority Critical patent/JPS5875251A/en
Publication of JPS5875251A publication Critical patent/JPS5875251A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To increase the detection ratio of a defective integrated circuit, and to reduce a test pattern by providing input terminals for control signals for detecting malfunction, and an exclusive OR operation part for said control signals. CONSTITUTION:Various control signal input terminals A, B, C-Z of an integrated circuit show control signals themselves at the same time. When the control signal A is ''1'' and other control signals B-Z are ''0'' in normal operation, outputs of exclusive OR circuits (EOR) 1, 13, 19, and 22 are ''1'', and outputs of EORs 2-12, 14-18, 20, 21, and 23 are ''0'', so the test signal of an EOR24 is ''1'', judging that various control signals are in normal operation. If even one of the control signals B-Z goes up to ''1'', the test signal of the EOR24 goes down to ''0'', judging that the control signal is in erroneous operation.

Description

【発明の詳細な説明】 本発明は誤動作検出回路に関する。[Detailed description of the invention] The present invention relates to a malfunction detection circuit.

最近の集積回路に於て回路規模が大きくなるに伴い完全
に不良品を検出することが困難になっている。また必然
的にテストパターン数も増す方向にある。As the circuit scale of recent integrated circuits increases, it has become difficult to completely detect defective products. Also, the number of test patterns is inevitably increasing.

従来集積回路では、レジスタ等の選択信号で１つのレジ
スタを選択している時に、他のレジスタ選択信号がどの
ような状態にあるかということを調らべるには、後で全
レジスタの内容を検査する方法があるが十分ではなかっ
た。In conventional integrated circuits, when one register is selected by a register selection signal, in order to find out what state the other register selection signals are in, it is necessary to check the contents of all registers later. There are methods to test this, but they are not sufficient.

本発明は従来のもののこのような欠点を除去し各々のレ
ジスタ制御信号を論理回路で演算し少ない信号数にし、
各レジスタ制御信号に異常があればこれを検出すること
を可能としたもので、集積回路の不良品検出率を上げる
とともにテストパターンの縮小化が可能になる。The present invention eliminates these drawbacks of the conventional ones and reduces the number of signals by calculating each register control signal with a logic circuit.
This makes it possible to detect any abnormality in each register control signal, thereby increasing the detection rate of defective products in integrated circuits and making it possible to reduce the size of test patterns.

本発明によると誤動作を検出さるべき複数の制御信号の
入力端子を有し、前記複数の制御信号の排他的論理和演
算部を含むことを特徴とする誤動作検出回路が得られる
１１ 本発明を図を用いて詳細に説明をする。第１図は本発明
の一実施例の回路図である。図に於いて、号の入力端子
であって、同時にＡ％１１．　Ｃ・・・２は制御信号自
身を示すこととする。ことで例えばＥＯＲＩは制御信号
Ａ、Ｂを入力とし、ＥＯＲ２は制御信号Ｃ，Ｄを入力と
し、ＥＯＲｌ３はＥＯＲｌとＥＯＲ２の出力信号を入力
とするものとする。According to the present invention, there is obtained a malfunction detection circuit characterized in that it has input terminals for a plurality of control signals whose malfunctions are to be detected, and includes an exclusive OR operation section for the plurality of control signals. A detailed explanation will be provided using . FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, it is the input terminal of the number A%11. C...2 indicates the control signal itself. For example, assume that EORI receives control signals A and B, EOR2 receives control signals C and D, and EORl3 receives output signals of EORl and EOR2.

今制御信号Ａが１１″でその他の制御信号Ｂ〜Ｚが＃Ｏ
′で正しい動作するものであるとするとＥＯＲ，１％　
１３．１９．２２の出力は１＃であり、ＥＯＲ１１２，
１４〜１８．２０．２１．２３の出力は＃θ′であるか
ら、ＥＯ１％２４のテスト信号は＃１＃となり、各種制
御信号が正しく動作していることがわかる。Now control signal A is 11'' and other control signals B to Z are #O
′ if it works correctly, EOR, 1%
13.19.22 output is 1#, EOR112,
Since the outputs from 14 to 18, 20, 21, and 23 are #θ', the test signal for EO1% 24 is #1#, indicating that the various control signals are operating correctly.

ここで制御信号Ｂ−Ｚが１つでも誤動作し１′になると
ＥＯＲ，２４のテスト信号は＃Ｑ１となり制御信号が誤
動作していることがわかる。If even one of the control signals B-Z malfunctions and becomes 1', the test signal of EOR, 24 becomes #Q1, indicating that the control signal malfunctions.

本発明によると、小規模な回路で１つのテスト信号によ
り複数の制御信号が正常に動作しているかどうかがわか
り、１つのテスト信号で複数の制御信号の誤動作が判断
できるために少ないテストパターンで不良品を検出する
ことができる。According to the present invention, it is possible to determine whether multiple control signals are operating normally using a single test signal in a small-scale circuit, and malfunctions of multiple control signals can be determined using a single test signal, thereby requiring fewer test patterns. Defective products can be detected.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す回路図である。 Ａ−Ｚ・・・・・・制御信号入力端子　１〜２４・・・
・・・排テスト帛号 猶１回FIG. 1 is a circuit diagram showing an embodiment of the present invention. A-Z...Control signal input terminal 1-24...
...Exhaust test code 1 time

Claims (1)

【特許請求の範囲】[Claims] 誤動作を検出さるべき複数の制御信号の入力端子を有し
、前記複数の制御信号の排他的論理和演算部を含むこと
を特徴とする誤動作検出回路。A malfunction detection circuit having an input terminal for a plurality of control signals whose malfunctions are to be detected, and comprising an exclusive OR operation section for the plurality of control signals.
JP56172231A 1981-10-28 1981-10-28 Malfunction detecting circuit Pending JPS5875251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56172231A JPS5875251A (en) 1981-10-28 1981-10-28 Malfunction detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56172231A JPS5875251A (en) 1981-10-28 1981-10-28 Malfunction detecting circuit

Publications (1)

Publication Number Publication Date
JPS5875251A true JPS5875251A (en) 1983-05-06

Family

ID=15938028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56172231A Pending JPS5875251A (en) 1981-10-28 1981-10-28 Malfunction detecting circuit

Country Status (1)

Country Link
JP (1) JPS5875251A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5345833B2 (en) * 1973-02-05 1978-12-09
JPS55166749A (en) * 1979-06-15 1980-12-26 Nec Corp Decoder circuit
JPS5653232B2 (en) * 1974-12-09 1981-12-17

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5345833B2 (en) * 1973-02-05 1978-12-09
JPS5653232B2 (en) * 1974-12-09 1981-12-17
JPS55166749A (en) * 1979-06-15 1980-12-26 Nec Corp Decoder circuit

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