JPS61134845A - Error detecting system - Google Patents

Abstract

PURPOSE:To detect the errors of a microprocessor in early stages by comparing value obtained before data processing with the value obtained after data processing at prescribed time intervals for a microprocessor and checking the processing time. CONSTITUTION:When a timing generator 4 gives the interruption generation timing to an interruption generator 3, an interruption is produced to a microprocessor 1 via an interruption line 11 for start of the interruption processing. The processor 1 reads an interruption processing program out of a control memory ROM30 and executes it as follows. That is, the processor 1 shifts successively the fixed data among all internal register groups 9 and stores the result of said shift to a fixed data holding register 6. The generator 4 sends the comparison timing to a signal line 19 and compares a fixed data holding register 5 with the register 6 for detection of errors of the processor 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to WI! This invention relates to an error detection method for detecting errors in output data of a single-chip microprocessor using simple hardware. '1-chip microprocessors have come to be used in a variety of fields as an effective means of making devices smaller and cheaper. However, as the scope of its use has expanded, there has been a demand for a one-chip microprocessor that can withstand devices requiring higher reliability.

[Problems to be solved by conventional technology and inventions] The introduction of microprocessors not only makes devices smaller and cheaper, but also reduces the number of component parts, which improves device reliability. I also have a lot of responsibilities.

However, on the other hand, no one-chip microprocessor itself is equipped with an interference detection circuit for its internal address lines, data lines, internal registers, etc.

Furthermore, when used as a device 2 that requires a higher degree of reliability, such as a main processor, there is a problem in terms of reliability.

Therefore, when using a microprocessor in a device that requires higher reliability, the microprocessor's external circuit 2
For example, in devices that require error detection circuits for each memory, register, etc. that stores and transfers data from a microprocessor, and that require even higher reliability, multiple microprocessors may be operated simultaneously, and each Error detection was performed by comparing the output lines using, for example, a comparator circuit.

Therefore, there was a problem in that the amount of hardware increased and the price increased.

[Means for solving problems]

The present invention aims to realize a novel error detection method that solves the above problems.

The problem lies in an interrupt means that generates an interrupt to the microprocessor at predetermined time intervals, and a movement control that moves a plurality of fixed data predetermined by the separate interrupt between a plurality of registers inside the microprocessor. output means for outputting the data moved by the movement control means to the outside of the microprocessor; comparison means for comparing the fixed data with the data output from the output means; and movement between the plurality of registers. measuring means for measuring the execution time of the microprocessor until the fixed data is output from the output means, and a measuring means for measuring the execution time of the microprocessor until the fixed data is outputted from the output means, and a measuring means for measuring the execution time of the microprocessor until the fixed data is outputted from the output means. This problem is solved by the error detection method according to the present invention, which detects errors in the data output from the microprocessor by determining whether the fixed data has been moved between the plurality of registers and output.

[Effect]

That is, multiple fixed data to detect errors.
] interrupts the microprocessor at predetermined time intervals.

Comparing data sent to an internal register group consisting of a plurality of registers in the microprocessor and output after being moved between the internal register groups with the plurality of fixed data before being sent to the internal register group; Errors are detected based on the execution time required for the plurality of fixed data to be moved through the internal register group and output.
By forming an error check circuit compatible with a one-chip microprocessor, it becomes possible to perform early error detection at appropriate time intervals with simple hardware.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 shows an embodiment of a microprocessor incorporating an error detection circuit according to the present invention.

The one-chip microprocessor 1 in this embodiment has an internal register group 9.
It includes an arithmetic circuit (not shown), an address control circuit (not shown), and the like.

Note that the timing generator 4 provides the interrupt generator 3 with timing to generate an interrupt to the microprocessor 1 at predetermined time intervals.

Further, the timing generator 4 takes in the signal of the common bus 2,
The time from when the microprocessor 1 reads the contents of the fixed data holding register 5 to when the data is written to the output data holding register 6 is measured. This time is determined by counting the operating clock of the microprocessor 1.

Next, the operation of the ninth embodiment will be explained. In addition, codes 11 to 22
indicates signal lines between each functional block.

When the timing generator 4 gives the interrupt generator 3 the timing for generating an interrupt number.

The interrupt generator 3 generates an interrupt to the microprocessor 1 through an interrupt signal line 11. When microprocessor 1 receives this interrupt, it starts interrupt processing.

That is, the microprocessor 1 stores the program for interrupt processing in the control memory (ROM) via the common bus 2.
) 30, and the interrupt processing is executed as follows using the interrupt processing program.

First, the 74C processor 1 loads fixed data from the fixed data holding register 5 into one of the internal register group 9. The loading of this fixed data is detected by the timing generator 4, after which it starts counting operation clocks.

Next, the microprocessor 1 repeats the operation of sequentially moving the fixed data loaded into one of the internal register group 9 to other registers of the internal register group 9.

This data movement is performed in all the registers of the internal register group 9, and upon completion, the microprocessor 1 stores the data in the output data holding register 6.

This data store is detected by the timing generator 4, and the timing generator 4 stops counting the operating clocks, and the timing generator 4 determines whether the counted clock number is normal or not based on a preset reference clock number (or reference time). ) to make a judgment.

Note that the reference clock number (or reference time) is the number of locks (or processing time) necessary for the microprocessor 1 to perform normal processing. If it is determined that the above determination is not normal, an entertainment detection signal is outputted to a processing section (not shown) via the signal line 22.

When the timing generator 4 is normal and detects the number of locks,
The data comparison timing is sent to the signal line 19. At this comparison timing, the contents of the fixed data holding register 5 and the output data holding register 6 are compared, and if they do not match, a mismatch signal is sent to the signal line 20 and set in the flip-flop 8.

The flip-flop 8 thereby outputs an error detection signal to a processing section (not shown) via the signal line 21. still,
It is more effective to read a plurality of types of fixed data into the internal register group 9 in order to increase the error detection rate.

〔Effect of the invention〕

According to the present invention as described above, the microprocessor
Diagnosis for detecting errors can be executed using interrupts even when the sensor is in operation, making it possible to discover errors in the microprocessor early, and realizing a highly reliable microprocessor sensor with simple hardware. It has the effect of saying.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a microprocessor incorporating an error detection circuit according to the present invention. In fig. 1 is a microprocessor, 2 is a common bus. 3 is an interrupt generator. 4 is a timing generator. 5 is a register for holding fixed data. 6 is a register for holding output data. 7 is a comparator. 8 is a flip-flop, and 9 is a group of internal registers. 10 is a clock generator, and 11 to 22 are signal lines. 30 is a control memory (ROM). are shown respectively.

Claims (1)

[Claims] Interrupt means for generating an interrupt to a microprocessor at predetermined time intervals; movement control means for moving a plurality of fixed data predetermined by the interrupt between a plurality of registers within the microprocessor; and the movement control means. output means for outputting the data moved by the means to the outside of the microprocessor; comparison means for comparing the fixed data with the data output from the output means; measuring means for measuring the execution time of the microprocessor until it is output from the output means, and determining whether the fixed data has been moved between the plurality of registers without apology;
An error detection method characterized in that an error in the data output from the microprocessor is detected by determining whether the fixed data is moved between the plurality of registers and output at a predetermined time.