JPH04184681A - Simplified fault simulation system - Google Patents

Abstract

PURPOSE:To perform the diagnosis of a fault appropriately by eliminating indefinite transient phenomenon by storing the state transition data of the output value of each logic gate and eliminating an event within designated time width in simplified simulation for a circuit. CONSTITUTION:The state change of the logic gates MA-ME in circuit information are performed, and the patterns of them are stored. Thence, the time width 10 is designated, and the events MC, MD, and ME with indefinite state are eliminated. It is detected whether or not the logic gates are operated as 1 0 or 0 1 by an input pattern, and when the state change such as 1 0, 0 1 occurs, it is assumed that the logic gate is operated. It is assumed that the logic gate MA is operated necessarily. It is decided that the logic gate MB is not operated by only the operation of 0 1, and the logic gate MC from which '6' is deleted and is not operated by only the operation of 1 0, and the logic gate MD from which '4' and '6' are deleted and is operated since change 1 0 1 occurs, and the logic gate ME is operated by eliminating '8'. Thereby, the simplified fault simulation can be accurately performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a simple fault simulation method for semiconductor integrated circuits, and more particularly to a simple fault simulation method for determining the detection rate of test patterns used in logic verification.

[Conventional technology]

Conventionally, a circuit diagram is input using a circuit diagram input device, and the quality of the test pattern is verified by performing logic simulation using the circuit diagram connection information generated from the data and input test patterns created manually. Ta. There is a fault coverage rate that indicates the quality of this test pattern, but it is difficult to accurately calculate this fault coverage rate because it takes simulation time, so we have implemented a method called simple fault simulation as an alternative. . When performing such verification, after executing a logic simulation, it is detected whether each logic gate in the circuit connection information is operating based on an input test pattern. The output of each logic gate is 1 → 0, 0 →
The logic gate is considered to have operated when both state changes of 1 occur. Further, when the state of the logic gate changes only from 1 to 0 or from 0 to 1, or when no state change occurs at all, the logic gate is considered to be inactive. In this way, the number of gates that operated by detecting the state change of each logic gate was divided by the total number of gates in the circuit to obtain the test pattern detection rate.

As mentioned above, in this simple fault simulation, it is not possible to expect an accurate fault detection rate of the test pattern, but since the quality of the test pattern can be easily determined indirectly, it is particularly useful for ASIC (Application spec).
It is often used when designing test patterns for IFIC IC).

[Problem to be solved by the invention]

However, in the conventional simple fault simulation method described above, the logic gate is considered to have operated only when both state changes of 0→1 and 1→0 occur in the logic gate. In logic simulation, a transitional state exists between a low level and a high level or between a high level and a low level when the state of a logic gate changes. For example, consider a case where the pressures of two transfer gates are connected to an equipotential net and the gate input signals of both transfer gates are switched at the same time.

The gate input signal of one transfer gate is l→0
When the gate input signal of the other transfer gate is switched to O-1, both transfer gates may be in the ON state, and the output signal becomes momentarily unstable.

Even in such a normally operating circuit, if a spike like 0→X→1.1→X-+O occurs in the logic gate, it is considered to be non-operating and cannot be detected.

Furthermore, when the input signals of a logic gate operate simultaneously, noise may appear momentarily on the output signal. For example, two-person NA
In an ND circuit, one input goes from 1 to 0, and the other input goes from 0 to
1 at the same time, the output changes momentarily from 0 to 1 to 0. The conventional method has the disadvantage that even in such a malfunction, the logic gate is detected as operating.

[Means for solving the problem] In a simple fault simulation method that detects test patterns based on state changes of each logic gate in circuit connection information, data on state transitions of output values of each logic gate in circuit connection information is A step of storing, a step of specifying an arbitrary pulse time width, a step of deleting an event in a certain state within the specified pulse time width, and a step of detecting the state transition of the output value of each logic gate in the circuit connection information. have.

[Example 1] Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a timing chart for explaining the simple failure simulation method of the present invention.

MA, MB, MC, MD, and ME are the element names of each logic gate in the circuit connection information. The numerical values in the timing chart are the times during which each logic gate is in an undefined state. The shaded area represents an undefined state. In this embodiment, a case will be explained in which an undefined state within an arbitrary pulse time width is deleted.

When performing a simple fault simulation according to the present invention, a logic simulation is performed using circuit connection information and an input test pattern as input, and the logic gate M in the circuit connection information is
Data on state changes of output values of A, MB, MC, MD, and ME are stored for all patterns. Next, the pulse time width “
Specify 10”.

Logic gates with an undefined state within the specified pulse time width "10" are MC from the timing chart.

MD and ME. Delete events in an undefined state for MC, MD, and ME. The time when the output changed and the changed value for each logic gate in the circuit connection information are stored for all patterns, and from the data it can be determined whether the gates of MA to ME operated from 1 to 0 or from 0 to 1 due to the input cover turn. Detect and count. When there is a state change of both l→0 and 0→1, the logic gate is considered to have operated. For example, among the five logic gates of MA-ME, MA is 1→0.
Since there is a state change of 0-1, it is assumed that it has operated. MB is regarded as not operating if only one state changes from O→1, 1→X→0. The MC deletes this event in an undefined state with a pulse time width of "6", and considers the state change of only 1→0 to be inactive. The MD deletes these events in an undefined state with pulse time widths of "4" and "6", and considers it to have operated since there is a state change of 1→0, 0→1. The ME deletes this event in an undefined state with a pulse time width of "8", and since there is a state change from 1 to 0.0 to 1, it is considered to have operated. Therefore, the logic gates that are considered to have operated are MA, MD, and ME. In other words, the detection rate of this input test pattern is (315) * 100
=60.0%.

As described above, by specifying an arbitrary pulse time width, events in an undefined state within the specified pulse time width are deleted, and a pattern detection rate that takes into account the transient state of each logic gate in the circuit connection information is calculated. I can do it.

[Embodiment 2] FIG. 3 is a block diagram for explaining a second embodiment of the present invention. 10.11 is a fankunyong block with functions such as latches. 12 is a two-man powered NAND circuit.

FIG. 4 shows a timing chart of this embodiment.

In this embodiment, a case will be explained in which a determined state within an arbitrary pulse time width is deleted. Assume that the output of the funkunyong block 10 changes from 0 to 1 and the output of the function block 11 changes from 1 to 0 at the same time, and racing occurs with the input of the two-man NAND. The output of the two-person NAND circuit is timing.

As shown in the chart, a momentary 0→1→0 noise is generated. Events within the specified pulse time width”
There is an advantage that an accurate detection rate can be obtained by deleting 1'' and excluding it from detection.

FIG. 1 shows a flowchart of the procedure for implementing the present invention as described above.

〔Effect of the invention〕

As explained above, the present invention deletes events within the specified pulse time width by specifying an arbitrary pulse time width, and even in normally operating circuits, 0→X
→When a spike like 1 occurs, the logic gate turns O→
It can be detected that the operation is performed as follows. Furthermore, if a logic gate remains in an undefined state due to a circuit configuration error, it can be considered as non-operating. Therefore, when a spike like O→X-11 occurs, it is possible to test the circuit by taking into account the transient state.

Furthermore, when noise is generated due to simultaneous operation of logic gate inputs, it is possible to test the circuit in consideration of malfunction. This reduces the time required to check undetected gates. Furthermore, gates that have been erroneously detected due to circuit malfunction can be excluded from the target, resulting in the effect that more accurate simple failure simulation can be performed.

[Brief explanation of the drawing]

FIG. 1 is a flow chart of the present invention, FIG. 2 is a timing chart for explaining a method of implementing the present invention, and FIG. 3 is a diagram for explaining another method of implementing the present invention. FIG. 4 is a timing chart for explaining another implementation method of the present invention. MA, MB, MC, MD, ME... Unique name of each logic gate in circuit connection information, l... Undefined state with pulse time width "30'", 2... Pulse time width
6" undefined state, 3... undefined state with pulse time width "4", 4... undefined state with pulse time width "6'", 5... pulse time width ° “8” undefined state, 1
0.11...Function block, 12.
...NAND circuit. Agent Patent Attorney Uchihara Oto No. 1 No. 2

Claims (1)

[Claims] In a simple fault simulation method that detects a test pattern based on the state change of each logic gate in the circuit connection information, the first step is to store data on the state transition of the output value of each logic gate in the circuit connection information. a second step of specifying the pulse time width; a third step of deleting events in a certain state within the specified pulse time width; A simple failure simulation method that has a fourth step of detecting from the data stored in the step.