JPS5874069A - Semiconductor ic device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simultaneously control the threshold voltage to approx. the same value by a method wherein P type and N type wells of approx. the same densities are formed on an N<-> type Si substrate, the same conductive type gate electrodes are provided, and conductivity conversion layers are provided on channel parts of both FETs. CONSTITUTION:N and P type wells 33, 39 of approx. the same densities are provided on the N<-> type Si substrate 30 in clearance and covered with an oxide thin film 37. B ions are implanted resulting in the formation of conductivity conversion layers 38, 39, and a poly Si 40 added with P and a low temperature oxide film 41 are superposed. A resist mask 42 is provided, and layers 41, 40 and the oxide film 37 are etched. After the mask 42 is removed, a PSG 43 and a thermal oxide film 44 are selectively provided, P<+> layers 50, 51 are formed on the N well by B diffusion and N<+> layers 52-54 on the P well by P diffusion from the PSG 43. The PSG 43 and the oxide films 41, 44 are etched, Al electrodes 55-58 are laid on the layers 50-53, the electrodes 56, 57 are short-circuitted by an Al wiring 59, and the gate electrode is led out of the region by the poly Si 40 and covered over the entire surface with a silane 60. In this constitution, the threshold voltage of a C-IGFET can be easily controlled to approx. the same value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuit devices, particularly P-channel and N-channel devices.
Complementary lid silicon gate field effect semiconductor integrated circuit device (hereinafter referred to as silicon gate) formed by forming channel type silicon gate field effect transistors on the same substrate 0MO8・I
(abbreviated as C) related to K.

-Are you cool? In the type CMO8-IC, except for the special 0M011 circuit, the normal circuit threshold voltage is approximately 1/1 of the power supply used.
2K, it is required that the threshold voltages of the P-channel and N-channel noble silicon gate field effect transistors be equal to each other.

However, in order to properly control the threshold voltages of both transistors to approximately the same value, a so-called channel is added by adding a predetermined conductive lid impurity in an appropriate amount and distribution to the channel region directly under the gate electrode of each transistor.・
By doping, the impurity concentrations in the channel regions of both transistors are controlled, and the threshold voltages of the transistors are controlled to a value lower than each other. If the silicon gate field effect transistor and the silicon gate field effect transistor are controlled separately, the photolithography process and the channel dovetailing process will be required twice each, which increases the number of control processes.Also, it is required to control the threshold voltage of both transistors at the same time. ing.

By the way, in the past, the ninth method that satisfies these two tatami conditions is the silicon game (0MO8・IC) as shown in Figures 1 and 2.
It is formed as shown in the figure. In other words, the N-type silicon substrate (1) has an impurity of about 2
The area (2) is approximately I x 10” atoms/a11
@degreesc, sot.

Lever N* silicon substrate (1) and P-shaped island region (2)
At least a portion corresponding to the channel region of the transistor is simultaneously channel-doped with a phosphorescent material, and the same conductivity conversion layers (1) and 121) are formed in those portions, respectively. Boron impurities are then diffused into this N-type silicon substrate (1) using the gate oxide film (3) and polycrystalline silicon (4) as masks, and the source (5) and drain regions (
6), while P-type island region (2) K gate oxide film [(3γ and polycrystalline silicon (4γ) was used as a mask to perform Linnean blunt diffusion to form the source of the N-channel lid silicon gate field effect transistor (7) and drain region (8)
It forms. And this source area (5), (
7) and drain region +6), +8) respectively) source electrode (9), Ql) and drain electrode Q(1)
, αa, for example, connect the drain electrode α and the ring to each other via the KAj wiring I, and connect the gate electrode (3) of polycrystalline silicon ゛1... (3F is the source and drain region 11' Simultaneously at the time of formation (converted into a low-resistance O conductive layer by introducing impurities into each layer), the conductive waves are different from each other, and as shown in Figure 2, they are connected to each other via the KAj connection body α◆. Become.

As mentioned above, the impurity density of the Nll silicon substrate (1) is selected to be about 2X10 at(2)l/(IIg), and the impurity density of the P-type island region (2) is selected to be about lXl
By selecting the 0 at-axis type, for example, the gate oxide film (3) (3F film thickness (TOX) can be set to approximately tzooX
8 degrees, 5i-sto, fixed charge amount (N
ss) to about 5 x 1010/ll 9 degrees, and the impurity concentration of polycrystalline silicon to about I x 10 aloms
/d, the threshold voltage of the N-channel silicon gate field effect transistor is about 1.25 V 9 degrees, as shown in Figure 3, while the threshold voltage of the P channel silicon gate field effect transistor is approximately 1.25 V 9 degrees. The value voltage is about -
The voltage will be approximately 0.75V. Therefore, the threshold voltages of both transistors should be set to suitable equal values, for example 11. OVl
, in the same negative direction and by the same amount, for example lO
, 25Vl, it is sufficient to control the white value voltage of both transistors to shift. That is, for an N-channel lidded silicon gate field effect transistor.
In this case, the impurity concentration in the channel region is reduced by a threshold voltage of about 0.25V, while for the 11-channel silicon gate field effect transistor, the impurity concentration in the channel region is reduced by a threshold voltage equal to about 0.25V. I thought it would be better if I raised it.

As shown above, the rounding is approximately 0.2 in the channel region of the KN channel and P channel silicon gate field effect transistors. An amount corresponding to a part of the flexibility value of SV, that is, an acceleration voltage of 130 @V, and a dose of 9 x 1
The conductivity conversion layer (to) and Q
If K is provided, the threshold voltages of N-channel and P-channel silicon gate field effect transistors will be approximately 7×011,1·rnS/d and approximately 4×10” mtoma, respectively. The threshold voltage 1 obtained when using a substrate with a concentration of %-, for example +1.OVl
Then, the values are equal to each other, for example, 11.0 VIK.

As described above, in the conventional silicon gate MO8-IC, the N-type silicon substrate is approximately 2 XIO" atoms/- and the P-type island region is approximately I X 1G" atoms/-.
By doping the same amount of the same Linnean obtuse into the channel regions of N-channel and P-channel silicon gate field effect transistors, depending on the impurity concentration of the d-radius selected, the OL conductivity of both transistors can be improved. Value voltage: can be controlled to a desired value that is approximately equal, but the rounding selected for the impurity concentration of the KP shape region of about 1X10'' atomsz-1 as described above has the following problems: The impurity level of the P-shaped region which becomes the substrate of the N-channel silicon gate field effect transistor is approximately I x 10''
atoms/a11 and the impurity concentration of the N-type silicon substrate, which is the substrate of the P-channel silicon gate field effect transistor, are higher than the 2X10"M decoy/dK, and the junction capacitance of the source and drain regions of each transistor and the substrate The bias effect depends on the impurity concentration of the substrate, and if the impurity concentration of the substrate becomes high, the junction capacitance and substrate bias effect will also be similar to each other.臘When the source and drain regions of a silicon gate field effect transistor are formed with dimensions of approximately 30 s x 20 s 0, the junction capacitance of the source and drain 1 of an N-channel silicon gate field effect transistor is approximately 0.1.
9PF, while the junction capacitance of the source and drain regions of an r-channel silicon gate field effect transistor is approximately 0.085PF, whereas the junction capacitance of an n-channel silicon gate field effect transistor is that of a p-channel silicon gate field effect transistor. Approximately 2.3 of
There is a problem that the substrate bias effect is large (especially in silicon games like this) 0MO8-IC
If a 4-bit silicon gate CMOI random access memory is configured using, for example, a 4-bit silicon gate CMOI random access memory, the problems of the junction capacitance and substrate bias effect of the N-channel gate field effect transistor described above become extremely serious. In other words, 0M01 random access memory (4 bits silicon game) has a memory memory as shown in Figure 4.
Since it is constructed by using cells as basic units, let us now consider the memory cell unit shown in the figure. This memory cell unit is a general KP
Memory cell M with channel QsmQs and N-channel silicon gate field effect transistor QaeQs
configuring C, its memory cell MC and digit line,
A switching silicon gate field effect transistor Q@*Q@ is connected between each of the switch transistors QseQ and QseQ, which are opened and closed by the bit signal applied to the bit line BK.Usually, this switching transistor QseQ is a P-channel silicon (gate field effect transistor) N-channel type silicon gate field effect transistor with high switching speed is used. and digits-D, DK
The connecting capacitances CD and CD are composed of the junction capacitance of the ON-channel silicon gate field effect transistor, the gate capacitance of the R- transistor, the wiring capacitance, etc.; however, these capacitances cD and ci are mostly due to the N-channel silicon gate field effect transistor. It is no exaggeration to say that it is determined by the junction capacitance of the transistor. Therefore, this CD, Ci5 is r
This is approximately 2.3 times larger than when using a channel type silicon gate field effect transistor, and by the way, the 4mC pit random access time is 64 ONf.
Yasonel 臘 silicon gate field effect transistor Qse
When Q is connected to digits 5 and 5 respectively, its co and ci5 are the sum of the junction capacitances of the N-channel silicon gate field effect transistor Q@*Q@, for example, 5.4PFK. Despite trying to improve the access time using a monolithic N-channel heavy silicon gate field effect transistor Qs*Qs, the capacitance cD and cE charging/discharging time becomes long and the access time becomes extremely slow. . The N+ field effect transistor Qseq6 has drawbacks such as a large substrate bias effect, rounding that makes it difficult for current to flow, and slow access time.

By the way, as a method of reducing the junction capacitance and substrate bias effect of the source and drain regions of such an N-channel silicon gate field effect transistor, N
It is conceivable that the impurity concentration of the P-shaped region (2), which is the substrate of the channel-type silicon-gate field effect transistor, can be lowered to 1, for example, I x 10 '' a tome, AtS. The O-junction capacitance of the source and drain regions of a silicon gate field effect transistor is reduced from about 0.19PF to about 0.08PF.
It is possible to reduce 5PPK and also to reduce the substrate bias effect. However, in order to form the P-shaped region (2) with a concentration such as
/d is lower than 1, for example about 2X1014
Atoms, of the order of %, will be selected. Konoto I! , as shown in FIG.
11. In the case of OVIKm, t, the direction and amount of shifting of the voltages are different from each other. There is a problem in that it requires doping with impurities of different channel numbers for different voltages, which increases the number of voltage control steps.

In other words, in the conventional silicon group) 0MO8 IC, N
When attempting to control the threshold voltages of the channel and P-channel silicon gate field effect transistors to equal values, the junction capacitance of the source and drain regions of the N-channel silicon gate field effect transistor and the substrate bias effect will be affected. On the other hand, when trying to obtain t with a small junction capacitance difference and substrate bias effect, it is troublesome to control the voltage at an arbitrary value, and it is easy to control the threshold voltage, and N-channel silicon It has not been possible to obtain a gate field effect transistor that satisfies both the junction capacitance of the source and drain regions and the small substrate bias effect.

The present invention has been made in view of the above points, and includes N-channel and p(, channel type silicon gate field effects, 11":'1
, the white value voltages of the transistors can be set to extreme values that are approximately equal to each other by JIK control, and the junction capacitance and substrate bias effect of the source and drain regions of an N-channel silicon gate field effect transistor are extremely small. The following is an embodiment of the present invention, which is intended to provide a circuit. Figure 0, which will be explained with reference to the manufacturing process shown, is an example in which an N-type silicon substrate is used. First, the substrate @) has a crystal plane of (10G> Using an N-type silicon substrate containing impurities, a thin oxide film (up to 810 mm) is formed on the entire surface of this substrate (CJD), and the oxidation process is carried out using ion implantation using a Linnean blunt material using the photoresist film (2) as a mask. mlF@) through the film to form an island-shaped N-type semiconductor layer of approximately 2 x 10" atomsAa11@degrees. This state is the fifth state.
Next, using the photoresist film as a mask, boron impurities were implanted into the substrate (3o) through the oxide film C, and the N-type semiconductor layer was formed as shown in Figure 5 (→). approximately the same time, i.e. approximately 2XIO”atons
An island-like OP-shaped conductor layer having an impurity of about /II is formed separately from the N-type semiconductor layer. After removing the oxide film a1 and the photoresist film, a thick filled oxide 1IcII is formed on the gold surface of the substrate (3G) as shown in Figure 5(C), and the N-type semiconductor layer and the P-type semiconductor layer are formed. The zero-order exposed N-type semiconductor formed by removing the filled oxidation Jl [CII] of the part forming the N-channel and P-channel silicon gate field effect transistors and the PN junction boundary part of the KP-type conductor layer (to), respectively. Layer (to) and P-type semiconductor layer (to) portion and KPNP
A gate oxide film (b) having a thickness of about 1200 μm is formed at the junction boundary, and the threshold voltages of the N-channel and P-channel silicon gate field effect transistors are adjusted to appropriate values, for example, l1. Ninth K to set the threshold voltage to OV l.

For example, if a boron impurity is applied at an acceleration voltage of 55 KeV and a dose of 9.5 XIO" at 6 ms/csl,
70 K) Channel-dope the N-type semiconductor layer (to) and P-type semiconductor layer (to) through the oxide film (b) simultaneously by ion implantation to form a conductivity conversion layer of the same conductivity type (to). ,
Form each @ and leave. And this gate oxide film (
(to) and Tzird Oxide Genus (to) K # I X 10
” atoms, #species o member g.

It contains Linnaeus dull material and forms nine polycrystalline silicon. By the way, the amount of impurities doped with the channel is sufficiently small compared to the amount of impurities introduced at the ninth stage of forming the source and drain regions, so there is no problem even if the impurities are formed in areas other than the channel region, that is, in the source and drain regions. Nine-channel doped 0rlAKP type semiconductor layer - PNi
The conductivity conversion layer is also doped with Linnaeus blunt material at the boundary portion of the 1st layer, but since this layer does not overlap 41, illustration thereof is omitted. This state is shown in Figure 5 (4 shows yam, then 1 II
(As shown in →, apply low-temperature oxidation lI and photoresist on the exposed carbon surface of the polycrystalline silicon 1, and apply 04 to 04 on the 1 part to form each gate of N-channel and P-channel silicon gate field effect transistors. The photoresist layer is left and the other portions are removed.Then, as shown in FIG. is removed by plasma etching method to obtain 0, 1, 1
As shown in Figure (2), the gate oxide film φ is then removed by etching, and the N-type semiconductor layer 2 and the P-type semiconductor layer to form the source/drain regions of the N-channel and P-channel type silicon gate field effect transistors are removed. The PN welding boundary portion of the KP-type semiconductor layer and the KP-type semiconductor layer are exposed, and then the photoresist is etched away, and as shown in FIG. Substrate 00 with nona oxide (PJIG genus) I and low temperature oxide film
) is formed over the entire surface, and after death, the PIIG and low temperature oxide films are used to form the source and drain regions of a P-channel silicon gate field effect transistor. K"O is left on the PN junction boundary part of (to), and the rest is removed. Next, the fifth
In the state of 11(h), poron impurities are diffused into the N-type semiconductor layer (1) by vapor phase diffusion using the gate oxide film (1), polycrystalline silicon, and low-temperature oxidized metal layer 9 as masks, thereby forming a P-channel type semiconductor layer. The P-type saw xf4 and the drain region 61 of a silicon gate field effect transistor are formed to a size of, for example, about 430β x 20μ, and at the same time, P2O is formed using Goo 1 oxide metal (b), polycrystalline silicon... and low temperature oxidation metal 4 as one screen.
For example, the N-type source and drain regions of an N-channel silicon gate field effect transistor can be formed by spreading a Linnaeus blunt material into the P-type semiconductor layer. form at a time. If you ask yourself this question, an N-type region is also formed in the OWN junction boundary of the P-type semiconductor layer (toward). The impurities in the drain and N-type regions are rounded and converted into such regions. After that, this PIG film I and low-temperature oxidation IH1,- are removed by etching, and this state is shown in #lEs diagram ( After forming a low-temperature oxide film, the source (to), f4 and drain regions an,
61, for example, by evaporating Aj to form the source and drain electrodes on the source and drain regions 6 of the P-channel silicon gate field effect transistor, and also on the N-channel silicon gate field effect transistor. Source (to) and F° drain electrodes are provided in the north and drain regions of the effect transistor, respectively, and the drain electrodes and (to) are connected by a wiring body. .

In this case, game) O'IIl! ? For the outgoing electrodes, polycrystalline silicon is preliminarily cut into an arc length in the transistor region, and then provided at the same time as the source and drain electrodes are formed.After this, a silane coat is applied, as shown in Fig. 5. (
j) As shown in K, a silicon gate CMO8 IC is completed.

According to the present invention as described above, the N-type silicon substrate is
Assuming a substrate with a low concentration of 0" to 101014ato/d@degrees, the P-type semiconductor layer that will become the substrate of an N-channel silicon gate field effect transistor is approximately 2X10'"
Formed at low concentration of atoms/cd, therefore N
The junction capacitance of the source and drain regions of a channel type silicon gate field effect transistor is approximately 0.085PF when the source and drain regions are formed to have dimensions of approximately 30μ×20s, which is approximately 0.111PF in the conventional case. '/2.3 times, which is extremely small. Moreover, the substrate bias effect also depends on the concentration of the P-type semiconductor layer, and has the effect of being extremely small compared to conventional ones. etc.0M08
When the circuit is constructed in the same manner as in the previous example, the operating speed is faster and the power consumption due to charging and discharging currents is also extremely small. In 41, a bit serial gate CMO II random access memory is constructed using such %O of the present invention, and in the case of 9, the capacitance CD connected to the digits, CD has a deviation of about 1.8Pν kind. The N-channel silicon gate field effect transistor has an extremely small substrate bias effect compared to the conventional O of about 5.4 PPK, which has the effect of significantly speeding up the access time compared to the conventional one. In the present invention, N
2 x 10” a to
An N-type semiconductor layer having an impurity concentration of 110 ml/a is provided, and this N-type semiconductor layer is used as a substrate of a P-channel type silicon gate field effect transistor.
1□Nf channel and polycrystalline silicon that will become the gate electrode of the P channel 11 silicon gate field effect transistor are both made of the same impurity #IFIL and the same conductive layer, that is, about 1 x 10 atoms/r containing Linnean obtuse. It is formed in Nil. Therefore, as shown in the Is6 diagram, the threshold voltages of the N-channel and P-channel silicon gate field effect transistors are about 0°25V and about -1, respectively.
,7! When controlling the comfortable value voltage of both transistors to an appropriate value, for example +1.0VIK, it is sufficient to shift the threshold voltage of both transistors in the same positive direction and by the same io, 75Vl. Become.

However, the P-type semiconductor layer and the N-type semiconductor layer, which are the channel regions of the N-channel and P-channel type silicon gate field effect transistors, each have a thickness of about 0.7.
61 to shift the threshold voltage of 5V! amount, i.e.
Accelerating voltage is 55 @V Te)' - Su quantity is 9.5
A conductivity conversion layer formed by simultaneously channel-doping boron impurities of approximately 10 a tents/csf is provided.ζ4'1. For tt6, the threshold voltages of N-channel and P-channel silicon gate field effect transistors are +1. The effect that OV l and OV l are simultaneously controlled to be equal to each other can be obtained.Furthermore, in the present invention, the silicon gate electrodes of the N-channel and P-channel silicon gate field effect transistors are formed to have the same conductivity 11. Therefore, when the gate electrodes of N-channel and P-channel silicon gate field effect transistors are commonly connected and used as an input terminal, conventionally the gate electrodes must be connected via an n-connector, and for this reason, especially Although a large area is required as a contacting part, in the present invention, there is no need to manipulate this thicker hl connector for connection, and therefore, a number of effects such as increased density can be obtained.

In the above embodiments, the case where the silicon gate electrode of the N-channel and P-channel type silicon gate F field effect transistor contains Linnean blunt material and is formed in 9Nll is explained. A similar effect can be obtained even when the silicon gate electrode of a silicon gate field effect transistor contains boron impurities and forms 9PIIK, i.e., in this case,
As shown in Figure #E1, the threshold voltages of N-channel and P-channel silicon gate field effect transistors are approximately 1.25 V and approximately -0.7 BY, respectively.
Set the threshold voltages of both transistors to a suitable value equal to each other, for example +1. When controlling to OV I, the threshold voltages of both transistors need to be shifted in the same negative direction and by the same lO, 25Vl, so that both the P-type semiconductor layer and the N-type semiconductor layer have approximately 0.0V. The amount required to shift the threshold voltage of 25V, i.e. 1 in terms of acceleration voltage.
A conductivity conversion layer may be formed by simultaneously doping the channel with Linnean blunt material at a dose of 9×10 atcm at 30 KeV.

Furthermore, as in each embodiment, the present invention is not limited to the case where a general silicon substrate is used as a substrate; Alternatively, as shown in FIG. 8, a KN-type semiconductor layer (to) and a P-type semiconductor layer (to) may be formed on an insulating substrate (70) as described above. They may be formed separated from each other via an insulator (71), and P channel and Nf channel silicon gate field effect transistors may be formed in the semiconductor layers (to) and @, respectively.

In the above practical example, the conductivity conversion layer is formed after forming the gate oxide film, but it is also possible to provide it before forming the gate oxide film. Although patterning is performed using an etching method, patterning may also be performed using a normal etching method using a nitride film as a mask.

[Brief explanation of the drawing]

Figures 1 and 2 are conventional silicon games) 0
A vertical cross-sectional view and a plan view of MO8-IC, ls3 diagram is a diagram showing the relationship between conventional silicon gate CMO8/ICO substrate and threshold voltage, and Figure 4 is a diagram showing the relationship between conventional silicon gate CMO8/ICO substrate and threshold voltage. 1. The circuit diagram showing each memory cell unit is an example of an embodiment of the present invention.
A cross-sectional diagram of the process showing one step in the production of O8・IC, 6-diagram line Honshu@〇-Silicon game in the example) 0MO8・IC
0
FIG. 8 is a diagram showing the relationship between substrate concentration and high voltage of MO8IC, and FIG. 8 is a longitudinal cross-sectional view showing still another embodiment of the present invention. In the figure (3G), (70)...board, (to)...N
shaped semiconductor layer. (to)...P-type semiconductor layer, 0 to...gate oxide film,
(To), (To)...Conductivity conversion layer, Ne...Polycrystalline silicon (gate electrode). (4) and 50... source and human train region of a P-channel type silicon gate field effect transistor, 61 and □□□... source and human train region of an N-channel type silicon gate field effect transistor, (to), (to) . . . source electrode, (to), 67) . . . drain electrode. −. (7317) Agent Patent Attorney Noriyuki Chika (81)
73) Agent Patent Attorney Oko Nori Geng-

Claims (1)

[Claims] (1) P-type and N-type formed on the surface of the substrate and having the same concentration
a base region formed together with the semiconductor region on the surface of the base body, and an N channel and a P channel formed in the P type and N type semiconductor regions and having the same conductive layer of the gate electrode, respectively. A semiconductor integrated circuit comprising a type silicon gate field effect transistor, and a leading conductor and a conversion layer formed in the channel regions of the N-channel and P-channel transistors!
(2) A semiconductor integrated circuit device characterized in that the substrate according to claim 1 is a low-concentration ON type semiconductor substrate. In the method for manufacturing a silicon gate field effect transistor OIl, as a method for adjusting the hold voltage O for the threshold of the complementary silicon gate field effect transistor, a deep P-type implant layer with a high concentration and the P-type implant layer are formed in advance in each transistor forming area. 9. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a deep N-type implantation layer of the same concentration, and then forming a shallow implantation layer of the same negative conductivity type so as to match the threshold 1 hold voltage.