JPS5873892A - Electronic timepiece - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an electric circuit and to improve the performance thereof, by conducting the temperature compensation by using a composite signal of a temperature information obtained from the frequency deviation from a time reference signal and of the temperature compensation function of the time piece. CONSTITUTION:A time reference signal source 113, a time counting unit signal composing mechanism 114, a time counting mechanism 115, a time display mechanism 117, an outside operation member, an electric energy supply source 118 and a signal generating means 111 are provided. The temperature compensation is conducted by using a signal composed of an information on a temperature obtained from the frequency deviation of the frequency of a signal of the means 111 from a time reference signal, and of the temperature compensation function of the time piece, by means of an operation circuit 116.

Description

[Detailed Description of the Invention] Conventionally, the limit of what determines the coolness of an electronic watch is the crystal oscillator, pulse motor, electronic display element, or battery. He took the path of reducing his size while giving up his position as fc.

The operating life of a watch is determined by divided power, pulse motor power, and crystal oscillator power, and there is leakage current loss of the battery that is combined with these □, and the relationship between these and the current capacity of the battery used The operating life of the clock was determined.

In terms of the marketability of battery-powered watches, the performance is impressive, and the external dimensions and operating life of 1:M pi are extremely impressive, and only recently have they reached the level of self-winding mechanical watches. 1.

Furthermore, according to recent technology, the power required to drive a watch is about to drop from 10 μW a few years ago to less than 1 μW due to improvements in the characteristics of motors and rationalization of the design of single-row mechanisms. Furthermore, the power required to display the time on an electronic clock has become less than 095 μW, taking a liquid crystal display as an example. If we only consider the power required to display the time, the battery capacity can be reduced to 1/10, or it is now possible to design a clock with an operating life of 10 years. Power consumption of battery clock other than display is 3μW
~1.5 μW exists, which means that 2/3 of it is used by the firing circuit and 1
/3 is consumed by the clock circuit system other than the branch office and other parts that are not overlooked. Therefore, it can be said that two-thirds of the current difficulty in making watches thinner and extending their life span is the electric circuit.

The present invention relates to the configuration of a system that can reduce the power consumption of an electric circuit, which is the above-mentioned problem, and can also be expected to significantly improve performance. The gist of the invention is to connect a capacitor in series with the power supply voltage to store energy, then connect them in parallel to average the potential difference across the capacitor, and use these switching operations to create a highly efficient low voltage source. By using this low voltage to perform crystal oscillation and information processing for clocks, the information processing performed by conventional electronic circuits is reduced to the square of the original voltage, and - 1/
4 to 1/25, and the total power consumption is 1/1 of that of conventional electronic watches.
/10, and provides a thin electronic watch with a long operating life. Furthermore, according to this configuration, the electronic components can be used for a long time with low I/V da/s, and the effects are significantly improved in terms of the accuracy, low distortion, and ease of maintaining accuracy of the crystal oscillator. In addition, this configuration is a multi-function clock that features increased functions using electronic circuits, such as a multiple alarm clock and calculation! - 6 clocks with 4 clocks, or pure pocketable equipment such as a notebook type calculator, the effect is dog, and depending on the situation, high voltage or low voltage can be used / Stem, for example, always low voltage By measuring the time at the source and increasing the contrast of the display element,
When displaying numerical values or paralysis results, it operates at a low speed, and if you want to increase the calculation speed only during calculation commands, switch the calculation section power supply and use the high voltage section to improve the frequency of the paralysis meter. When the frequency of the clock pulse is set to <1 or more, it can be used to improve the calculation speed, and it is possible to achieve both low power consumption and high performance, which is highly effective.

Next, one embodiment of the present invention will be described based on the drawings. 1st
In the figure, thick black lines indicate energy flow paths, and thin black lines indicate signal paths.

In Fig. 1, reference numeral 111 is an ultra-low power development oscillator for the voltage conversion circuit of the present invention, which is made by, for example, connecting C7MO8 inverters of image mutual co/conductance in 3 to 5 stages in a ring. . A switching circuit 112 is switched in synchronization with the signal obtained from the development oscillator 111. Reference numeral 113 denotes a time reference signal source for the clock, which is realized by, for example, a crystal oscillation circuit. 114 is a timekeeping unit signal synthesis mechanism that outputs the output of the time reference signal source 113, for example, 32768Hz.
A signal that is the unit of clock ticking, for example for household use 1)
For tarographs, IHL is synthesized because it only needs to be accurate to the second, and for chronographs, 100H2 is synthesized so that it can measure to the 1/100th unit. 115; is a timekeeping mechanism, which is composed of a counter that can set an initial value, and counts the signal of the timekeeping unit signal synthesis mechanism 114 to hold the time starting from the initial value time. 1161
In the ri level converter, the crystal oscillator 113, the count signal synthesis mechanism 114, and the clock mechanism 115 have Vs s', for example, 0.
Operates at 3V, and the /stem after display device 117 is Vss
For example, when the operating voltage level is different, such as when operating at 1.55 Volt, only the voltage level is converted without changing the signal transmission angle information. The level converter 116 is inserted between the counting signal synthesis mechanism 114 and the clock mechanism 115, and the timing mechanism 115 is operated at Vss+. It is also conceivable to operate the level converter 116 between the front stage and the rear stage. Depending on the location of the person, the signal path for level conversion differs, and the frequencies handled differ. In general, it is better to install the level converter 116 on the higher frequency side than the clock mechanism because it requires fewer level converters, but the power consumption increases, and it is better to install it on the lower frequency side because the number of level converters is smaller The display device 117 is a block that displays time information held by the clock mechanism 115 or other instruction information, and includes a decoder, a display drive circuit, and a display element. . Reference numeral 118 denotes an electrical energy source, such as a silver peroxide battery or a system combining a solar battery and a secondary battery.

The switching pulse that controls the switching element can be easily taken out from the middle of the dividing stage in the case of a quartz clock, but there is a method that uses four extremely low-power glue/glow generators independently of this, and a high Q value crystal oscillator. Compared to the slow start-up characteristics of low-power crystal oscillators using
An oscillator is prepared as a sub-oscillator, and voltage conversion switching can be performed using this function.

Figure 2 shows the sub-oscillator (A) for voltage conversion in Book 1.
, a waveform shaping circuit (B), and a switching circuit (C). 201 is a 1.6 Volt battery, 5,
: Pa, ;.

211 is a low Gmi P channel Rosewood/Sment F/E
T, 212 is an N-channel performance FET. In Figure 2, P channel
T, 211 and N channel E/C/Sume/) FET21
The second pair forms an inverter circuit, and if the gain is sufficient, it oscillates at a frequency whose half cycle is three times the response time of the circuit.

Using oscillation as a sub-oscillator is effective because a capacitor is not required when integrating the circuit.

The frequency is, for example, 1000 H2 to 1.00 H2, and the current consumed by this oscillation is 01 μ8 to 001 μA. The low-phase U-co/ductanos FET of 211 is a process to reduce the component of current that passes through FETs 211/1 and 212 during oscillation and shorts the power supply, and simply connects the inverter source and power supply with a high resistance. The reduction in the through current can also be achieved by connecting the through current.

The signal φD213 is also shaped into a wave q'@ by the inverter 221 of low Gm, and the switch 77 circuit (φ,
It is supplied as a signal pair F.

The signals supplied to the switching circuit +c)vd do not necessarily have to be mutually inverted complementary signals.

If it is necessary to supply m-phase (m is a natural number) number 1 to the switching section, an odd number of oscillation sections (A), for example 2n+1 ((2n+1), >m, m is a natural number), is required. )
By utilizing the fact that the output signals of the inverters have the same phase but different phases, the inverter circuit performs exclusive OR of the outputs of the adjacent inverters.

It is possible to obtain a number of signals equal to or less than (2n + 1) and their inverted signals.

The embodiment of the switch 77 circuit (C) in FIG. 2 only needs to be single-phase and have two complementary signals.

231, 233, 232, and 234 in Figure 2 are all switching circuits.Functionally, the switches 232, 234 with even numbers are turned on, and the switches with odd numbers 23
1.233 switch is turned off.

In this state of φ=H, conde/C, 241 and C224
2 are connected in series, and both ends thereof are y i+ n and V
Connected to ss and photoelectrically operated.

Vss 1/2 fx Le output terminal 251 and power supply node VIH
If a load is connected between J or Vss, C1
If the capacitance ratio of
Then, the odd numbered switches 231.233 are turned ON, the even numbered switches 232.234 are turned OFF, and the capacitors CI (2411C2 (242)) are connected in parallel and V, = 2 (\0).

By alternately switching H and L of φ, Vas1 of 251
A voltage of 1/2 of Vsgl is obtained from the /2 output terminal, measured between vDD and Vss ]/2. C,=2.5
Although capacitors having very different values such as ttF and C2=0.1 μF may be used, the closer the capacitance values of C1 and C are, the higher the utilization efficiency is.

This is because when the switching operation of the switching circuit causes charge to move between capacitors with Joule loss, the gravitational efficiency decreases. If the values of capacitors 241 and 242 are completely equal, the charging voltages of the capacitors immediately before they are connected in parallel phase are equal, and no charge transfer occurs between the capacitors when they are connected in parallel.
31 is a switch using a P-channel FET, and in the ON state, it is necessary to read directly to vDD, and in the OFF state, the drain potential is between vDD and Vss1, and the impedance between the source and drain must be a dog. figure,
The leakage current must be so small that it can be ignored.

FET234 and FET231 are complementary ONgl and O.
becomes FF, and when φ=H, N-channel FET 234 turns ON.
, the P-channel FET 231 is turned off.

232 and 233 are transmission gates, and since the potential at the point to be switched is between vDD and Vss, a pair of P-channel and N-channel FETs are used to ensure that they are turned on. In Figure 2, the substrate of the P-channel (hereinafter abbreviated as P-CH) FET is all v
N-channel (hereinafter abbreviated as N-CH) FET in DD
All substrates are connected to v881.

Instead of using the oscillator in Figure 2 (4), a crystal oscillator, which is a clock time reference signal source, is directly driven by battery voltage, and the oscillation output signal is used to drive a voltage conversion circuit using the frequency-divided signal. It is also possible to use a driving system. The purpose of creating a low-voltage source in this case is, for example, to supply a low voltage for a liquid crystal matrix drive, to lower the IA voltage of a crystal oscillator that is already oscillating at a low threshold voltage, or to reduce the electric field. It is used to supply a bias voltage to be applied to a resistor using an effect transistor.

The oscillator section in FIG. 2 (4) is a developed oscillator for reducing KR consumption, so care must be taken to reduce the current consumption here. The output waveform of the oscillation output signal 213 is a blunt waveform, and when the blunt waveform is directly applied to the inverter 221, the through current component (the power supply short-circuit current component that flows through both the P-CHFET and the N-CHFET) increases. Therefore, by using two adjacent inverter outputs of the oscillation section, waveform shaping without a through-current component can be performed as shown in FIG.

FIG. 3 (4) is an example of obtaining 1/3 voltage,
301 is a battery, 313 is an oscillator, 321 is a waveform shaping device, 3
24 is an inverter for obtaining a successful waveform. φ=H
, N-CHFET332, transmission gate (hereinafter T
When the capacitors 342 and 344 (referred to as G) are turned ON', the three capacitors 351, 352 and 353 are connected in series to the power supply and charged. Next, when φ=L, FE
T 332, T, G342.344 are OFF, P
- CHFET 331.341 and TG 343.345 are turned on, and the three condensers/s 351.352.353
are connected in parallel to average the voltage. Due to this averaging device, the variation in voltage during charging of the three capacitors due to variation in the capacitance of the desu is corrected, and the voltage that is exactly 1/3 of the power supply voltage is It will be done. As already mentioned, in order to achieve high efficiency, it is preferable that the ratio of the values of the three capacitors is l, and in order to reduce the low voltage source output power and impedance, the capacitor capacity should be small. It is better to have one, and from the standpoint of realizing a low-voltage circuit with a small volume and at low cost, it is better to have a smaller capacitor capacity. FIG. 3B is a system that satisfies these conflicting demands.

Here, a 31d capacitor using a small capacity capacitor is used for voltage conversion.
- Using the system of A as is, the voltage converter output is
A possible method is to use the switch circuit 389 in the large-capacity capacitor 399 and transfer the charge in a state where a low voltage output can be obtained. Since charge transfer is performed in the low voltage output phase, in steady state, the voltage of the large capacitance capacitor and the output voltage of the low voltage circuit almost match; Almost no joule loss component occurs. Also, the differential output chi/petance seen from the output load is 1/2.

FIG. 4 generally shows n7m (m) of a given power supply voltage.

A diagram to explain the principle of a circuit that creates a circuit (n is a natural number). The capacitance of each capacitor from 411 to 4 mn is all equal to C
It is assumed that the power supply voltage (potential difference between vDD and Vssl) is VO. 411 to Nihashi for simplicity
Assuming that there is no electric charge in the capacitor of ~4mn and the wires are connected as shown in Figure 4A, each capacitor will have an equal charge of Qo=CoVo/n stored at both ends of the capacitor. A voltage of VO/n appears. Next, if we change the wiring so that m columns are connected in series while keeping the directions of the conductors/des/des the same, then if we do not change the total number of condensers/disconnects, then the number of m columns in series will be reduced to n.

When these n columns are connected in parallel, the voltage across the columns in the parallel-connected state is (m/n)Vo,! Ni Naru. Obviously, in the process of the above operation, no current is generated due to the connection of the capacitor, so theoretically the voltage is converted with 100% efficiency. Since each capacitor has the same capacity, 100% efficiency is expected. The above is an example to explain the operating principle in an easy-to-understand manner; in reality, the number of capacitors can be much smaller.

■ When n7m>1/2, 1-n7m<1/2. Therefore, Vo (1
-n7m) and use the voltage difference between vO and Ayu.

If the 1 replacement capacitor is used as explained in the principle explanation, mn equal capacitances are required, but if the number of n is greater than m, the 7J formula saves 1 m/2 - n 1. Ru.

■ Replacement of series capacitors When reconnecting a column of m capacitors with n capacitors in series to a column of n capacitors with m capacitors in series, the capacitors that remain in series I/C are replaced with small capacitors. It is possible to directly replace the capacitor with one capacitor. At least n nine condenser columns in series, ie, n2 1/2 columns, can be replaced by n capacitors with a capacity of l/n.

FIG. 5 shows an example in which the voltage conversion circuit according to the present invention is further combined with a voltage control circuit based on the threshold value of the circuit element. The configuration shown in Figure 5 shows that a battery such as a lithium battery, which has a large power capacity and a very good shelf life, has a high voltage (approximately 2.6 to 3.2 Volt) for use in watches.
) and has a higher voltage fluctuation rate than silver batteries, this is a very convenient circuit for effectively utilizing batteries. 500 is a battery, 501, 502, and 503 are 14 low current inverters, three of which are connected in a ring to make one swing. The output of each inverter has a phase of 2 and 7. Since this is an oscillation waveform that has not been shaped, the 5040 waveform shaping gate can be used to shape the waveform with a small through current. 504 and 50
When the outputs of ``3'' are both 1H'', the output of 504 is ``L''
The output power balls of 504 and 503 are both set to ``L''
In , the output of 504 is set to 1H". 50
The output of 4 is further waveform-shaped, and the 5085090 two capacitors are switched in series and in parallel using the already explained switching circuit of the capacitor connection path to obtain a voltage of 172 VaS (D).Furthermore, 510 is a C/MOS This is a combination of inverter input and output, p-Ch-FET, N-ch
For voltages that exceed the FET's threshold value of absolute unity, it exhibits voltage (source-to-source) current characteristics similar to those of a Zener diode, so a pressure control circuit is constructed based on the sum of these threshold values. teψ). The voltage of C/MOS Inonoku Ichiyo 510 is (lyrp l + VTN l, (to P-c
Voltage component 1v due to source follower of h-FET513
rP15E power becomes 21Vrpl 5-vrtv. FET 511 is a high resistance N-ah-FET. 512 is p-ch of thick tm volume 41
-FET, which is a source follower.The output voltage has a voltage difference of v7P from the node due to the gate voltage, and the P-ch-FET5
13, the voltage f) i p −c h
- Used to compensate for differential voltage across FET 512.

The output voltage of the control output 519 is approximately 1 vrp lmo vT
This circuit takes care of the fluctuation of the threshold value during IC manufacturing by controlling the power supply voltage, and after performing a wide voltage conversion using an efficient voltage conversion circuit, By making fine voltage adjustments based on the FET threshold, an extremely energy efficient system can be achieved.

520 is a crystal oscillation circuit, 521 is a waveform shaping circuit that generates a time reference signal, 523 is a frequency dividing circuit, and waveform shaping circuit 5
A clock unit signal is synthesized from the outputs of 21. 524 is a clock circuit that handles low frequencies and consumes less current, so it uses the power source of the crystal oscillator 520, which has a lower impedance than the frequency divider 523.

525 is a level lid which converts the logic output signal of the clock circuit 524 into a static voltage and supplies a signal for driving the display device 526.

6-A is a block diagram of a system combining a temperature correction circuit and a voltage conversion circuit according to the configuration of the present application. 60
0 is a silver battery, 601, 602, and 603 are inverters with low transconductance, 604 is a resistor, and 605 is a capacitor. If the conductance and stray capacitance of 601, 602, and 603 in the integrated circuit cannot be made with good reproducibility, the resistor 604 is externally attached to adjust the oscillation frequency or correct the temperature-oscillation frequency characteristic. To adjust the oscillation frequency, 6-05 may be used as an external adjustment capacitor of the integrated circuit, or inverters 601 and 602 may be used.
, 60.3 may be adjusted to change the mutual conductance. 610 is the voltage conversion circuit according to the present invention, which has already been explained. 614,6
If the LM if coefficient of the oscillation frequency of the rooting circuit using the 02.603゛ inverter is large, it is sufficient to directly supply the stable and unchanging voltage of the 600 silver battery to the inverters 601, 602゜603. I; External temperature-sensitive elements 601 and 602 that constitute an oscillation inverter, for example, when a thermistor resistor is not used in 604 or a temperature-sensitive capacitor is not used in 605, or in the case of a household clock or clock that uses manganese batteries, 601 and 602 constitute an oscillation inverter. It is better to supply power from a simple regulator circuit that uses the dark value of the control terminal of the transistor, which is an active element used in the . . 6
11 is a time reference signal source, which is a crystal oscillation circuit.

612 is a frequency divider, and 613 is a data type flip-flop, which is an example of a circuit for obtaining a frequency difference.

If the frequency difference is very large, the output of the data type flip-flop 613 will give an integer multiple of the difference frequency.
When (Z, 1.023) IZ is connected to the clock power φ, a difference frequency signal of l 6'X (1,024-1,023)H2 is obtained. A square multiplication path 614 is provided for synthesizing a signal for correcting the second-order temperature coefficient of the crystal resonator.

616 is an example of a frequency addition circuit, which is an exclusive logic circuit or its ethical negation, a coincidence circuit.
y gate ) is the simplest. 623 is the output 606 of the second signal generation circuit for the temperature-sensitive oscillator-coulometric conversion circuit.
This is a circuit for synchronizing with the phase of the signal of 623, and the frequency of the data output and the output of 623 are almost equal, and only the phase has changed from synchronization with 606 to synchronization with the output of frequency addition circuit 616. 624 is a frequency divider that generates a low frequency signal for correction.

The phase of the output signal of the frequency divider 624 has a waveform that is shifted by a half period of the crystal oscillation circuit 611 by utilizing the inversion effect of the L signal to the inverter 622 and the phase of the output signal of the frequency divider 612. 626 is a gate for frequency addition. In the above description, each signal of the output of the multiplier circuit 614 for correcting the secondary characteristic of the temperature characteristic and the output of the frequency divider 624 of the signal generating circuit for correcting the primary characteristic is a signal source for the 3-time reference. Although the signal from the crystal oscillator circuit 611 is also used for synthesis, it is not necessarily necessary to use it.
This is only used because it is a nearby frequency source, and it is also possible to use another oscillator or to combine the 606 voltage conversion signals.

Figure 6B is a square circuit, which is used for quadratic characteristic correction and correction of Figure 6A.
This embodiment corresponds to the multiplication circuit 614.

χ is the squared input signal, REF is the time signal for frequency measurement, and the holder 4618A7) or the divider 61 in FIG.
7 or a frequency divider 615, a divider 612, or a crystal oscillator circuit 611 based on a stable frequency signal.
, synthesize. As an example of the frequency measurement method, the sixth
In IgB, the number of pulses in the χ input during a certain period of REF is counted. This method calculates the average frequency over a relatively long period of frequency measurement, reducing the effects of noise and noise, and making effective use of the constant frequency property of the time reference signal for clocks. It's a method.

In FIG. 6B, 101 is a reset signal that falls for a short time in synchronization with the rise of the REF signal, and is synthesized from the REF signal and the clock pulse φα by a delay by a logic circuit 631 and a gate 632. 633 is a counter which is reset by the REF↑ signal to a count value of 10", and then counts the squared signal pulses χ to increase the count value in a stepwise waveform with a constant slope as the number of strokes of time. REF The pulse width is short during the high level period and long during the low level period.

The signal χ of unknown frequency is counted during the high level period of this REF signal, and this count value is held during the remaining low level period, and the rising differential signal REF of REF is generated at the rising edge of the next REF signal. The count value is repeatedly reset to 0 by ↑. For example, the high level period of REF is 1 second, and the low level period of REF is 15 seconds.
It is best to choose between seconds and 300 seconds. The time constant of heat conduction for a step-like temperature change in a watch housed in a metal case is approximately 8 to 15 seconds, and the minimum time for a temperature change when a person is carrying the watch is several minutes. It takes several hours to several tens of hours for a change to actually appear as a visible change in the time held by the watch, so if you do not care about a time indication error of 0.5 seconds or less, use the REF signal above. - The duration of the level may be as long as one hour. Therefore, in FIG. 6B, the counter 623 always maintains the frequency of one person's input. For example, if a counter configured by seven flip-flops connected in a cassgate is used, the counter 623 maintains the 7-bit frequency of Q+o - Q+a. An example for implementing the square calculation of temperature difference information will be shown below. If the above temperature difference information is θ and expressed as θ'' qo 2°+q, 2'+ ... 19626, then Q11=H (high level) is ql-1
q+t=L (low level) can be set to correspond to 7i-〇. To realize θ2, first θ
Create a signal proportional to 1. The frequency is divided by 1/2 sequentially using the fc signal sound pinari cow/ri of a constant frequency, and
When the logical products of the signals Ci and Qli of the frequency fc are added by the OR gate, a signal C of the frequency fθ1 proportional to θ is obtained.
θ1 is obtained. Next, do exactly the same operation, but instead of C
60, a signal fθ2 proportional to 02 is obtained from the AND sum of the signal Cθ11 with a frequency of 2−1°fθ1 and Q+i.

By continuing the same operation, it is easy to obtain a signal proportional to the east of the power of 3 or more of θ. 0 of θ obtained in this way
By multiplying the signal of power 1 to the power of 36.5 or a higher power by an appropriate coefficient and adding it, it is possible to calculate the value of the Each first-order, second-order, and third-order temperature coefficient can be compensated for. Naturally, it is also possible to compensate for the temperature coefficient of the order of the highest order fixture F. Here, the above principle can be modified to simplify the system. In the explanation in @, fo1 proportional to 01 from constant frequency signal fc
Although I went out of my way to create this, it may be possible to use the χ input as a signal corresponding to fo. The temperature detector is operated intermittently, e.g. RE F signal I)
,/・In the 7-stem system, the temperature sensor is operated only at the level, and the data measured during this time is held in the counter. The corresponding temperature signal is input only intermittently, and a function generation mechanism is required to generate fo1 from fo. If the difference signal between a signal and a signal with a constant frequency can be obtained continuously by using a temperature difference signal, the umbrella 7-stem configuration can be easily achieved by using the χ signal instead of fo. FIG. 6B is an example of a simplified system as described above.

In FIG. 6B, REF is a constant frequency signal that serves as a reference for period measurement, and is a relatively low frequency signal obtained by dividing the crystal oscillator output signal. Figure 114) or holding mechanism i41 Figure 115
) is synthesized from

.chi. is a temperature difference signal created by data type flip-flop 613 in FIG. 6A. C is a clock signal, and any signal with a higher frequency than χ may be used, but DIV■
Since it is necessary to align the phase of the output signal of DIV 612 and the output signal of DIV 615, it is necessary to select the signals according to the purpose.

In the explanation of FIGS. 6A, B, and C, all toggle type knobs (hereinafter abbreviated as T-FF) are falling triggers, and all notches (hereinafter abbreviated as L-FF). )
reads data at the clock signal level,
It is assumed that the data is held at a low level. Further, it is assumed that the data type Frisopfronop (hereinafter abbreviated as D-FF) holds the data value at the moment of falling of the clock signal.

In FIG. 6B, 631 is a digital delay circuit whose output is f#7 in synchronization with the rising edge of C, and the delay time is R.
A gate 632 is used to create a signal REF↑ synchronized with the rise of EF. N(Q+j) 633 is a counter that counts and holds the frequency of χ input, Q+ o -Q+ a
represents a weight of 2° to 26. A D-FF 634 is a circuit for synchronizing the χ input signal into a signal synchronized with the rise of C, and 635 is a D-FF for creating a delayed waveform for differentiation. A counter 633 for frequency measurement and holding receives a signal Cp = A signal for tens is created and counted by a counter 633. The gate 637 uses the output signals 2+ of the flip-flops 634 and 635 and the delay of χ to create a signal χ true↑ synchronized with the rising edge of χX. The pulse width of χ screen↑ is C.
It is equal to the synchronization of the human power signal, and is synchronized with the fall of the C human power, that is, the rise of the output of the oscillator 611 in FIG. 638
is a frequency divider consisting of cascade-connected T-FFs to obtain a low frequency signal by dividing the frequency of χ, and each Qio
= The change in the output of Q+a is synchronized with the fall of ↑ in χ.

639 is a special notation to simplify logical product sum, and if the output of 640 gate is y, )' = Q + a
"Qo+ +Q1. Prisoner,・QQ2 + Qn'Qo+" QQ2 Sukinuta+Q13・Qo1' QQ2 "Q+]3' Qo
(10Q, 2・Qol・QQ2・Qox・Qo4・QC
+5+ Qu″Qo1°Q02°Ql”QQ4・QQ5
・Qo6+ Q+o ” Qo+・Qo2・QJ13
・QQ4・QQs・Qoe・QoT. If we rephrase this as the signal signal Ci mentioned above, the right side above becomes right side = Q, 6・C1 +Q3.・C; +Q, 4・C31 +Q1.・Ci +Q12・C3 +Q11・C6 +QIo−C7. Set the symbol f□ to give the frequency, and ff(4)
If represents the frequency of A, then f (C,) = 2
'・f(χ★)・2-7f(C,)='2'・f(χ1
1)・2-7f(C3)=2'-f(rri・2
−7f (C, l = 2'・f (χri・2−
7f(C'5)=22・f(χ2・2−7f (C61
= 2'・f(χsu・2−7, and f(y)=2'・f(χ2) holds.Special notation is used to make it easier to see the logical product.For example, matrix 639 and gate 640 It is expressed using.

The reason for using the AND-OR gate is that the weighting of 2′f (C) to 2″f (C) corresponding to Q+o −Q+a allows the frequencies of the signals to be added using the intelligent logic gate of the OR gate 640. This is because weighting requires that the sum of all ANDs for any combination of signals is always at a low level.When using an AND gate, the same consideration can be made by using negative logic. If the EXCLUSI VE-OR gate is used for frequency addition, it is only necessary that the waveform changes of the r-j) signals match each other.
) is a timing chart showing the timing of measuring and holding diopter data. The horizontal axis is time, and the vertical axis is a high level in the upward direction. The REF input signal is delayed and inverted to become the QREF signal and the REF signal and QREF
A reset signal R is generated from the signal. R is REF
The rising edge of the signal is the inverted signal of REF↑. The PIdQney signal itself counts at low level of P and holds data at high level of P.

- Cp is a signal for counting temperature data. QHo～Q
In the state from t2 to t in which data is stored in +a, a signal proportional to .chi.2 is obtained by the mechanism already described, and the system shown in FIG. 6 operates.

FIG. 7 shows an embodiment of the level conversion circuit. Input signal A 700 of inverter 701 is level-converted to become output signal A' 72-0. Inverter 1rJ1 operates at a low voltage, and input signal 700 and output signal 702 are complementary signals whose logic levels are vDD and Vssj.

FET711. 712, 714, 715 and FET7
21.722.724.725 constitutes a NAND gate that uses vDD and vSS2 as the output levels of the logic circuit, and the two sets of NAND gates cross each other to form a positive feedback loop, resulting in a bistable There are some who get 7 rip and 6 flop. Complementary signals 702g1 and 700 are human input signals that set the state of the bistable flip 70 tube circuit.

If A=L, P-CH-FET 711 is turned on and N-CH-FET 721 is turned off or in a high impedance state. Since A=H at the same time,
P-CH-FET 715 is turned OFF, and N-CH-
FET 725 is turned ON. In this situation, the output signal 72
0 rapidly rises to a high level due to the positive feedback loop ■D
Approaching D 1, P-CH-FET 712 becomes QN, 71
4 turns OFF, N-C1 (-FET722 turns OFF
, 724 are turned on and stabilized.

In a stable state, A and A' are in an inverse relationship, but FET11
It is clear that if the output signals are extracted from the drains of 4 and 715, a signal that is not in an inversion relationship and that differs only in the ethical level is obtained. When configuring the level conversion circuit shown in FIG. 7, the mutual conductance of the N-CH-FET is made small, the mutual conductance of the P-CH-FET is made large, and the N
The impedance when (Vssj -vssz) chisel pressure is applied to the gate of -CH-FET is as follows:
The impedance is larger than the impedance when a voltage of Vnn −Vssj) is applied, and
Care must be taken to ensure that the clip-flop value can be set by When integrating circuits, FET 7
The channel widths of FETs 11 and 715 may be increased, and the channel lengths of FETs 721 and 725 may be increased. ,,'t'
,,Ill,.

FIG. 8 shows an example of an electronic timepiece having two types of mechanisms: voltage reduction 1 by a voltage conversion circuit and voltage boosting by a booster circuit according to the present invention. 800 is a developed oscillator for voltage conversion, which can be thought of as a ring oscillator as already shown in Figures 2 and 3, or as a time reference if the purpose is simply to convert voltage for display driving. A signal obtained from a signal source or a frequency-divided signal of the signal may be used, or a crystal loss element may be prepared completely separately for rooting. Inverters 801 and 802 are used for waveform shaping, and at the same time are inverters for supplying power to drive the boost mechanism.

803 and 804 are capacitors for voltage division, and it is better to have the same capacitance. 805 is a capacitor for holding the voltage after boosting.

811 is a clamp diode, and 821 is a clamp capacitor. When d=HK, the diode 811 is forward biased, the output end of the inverter 802 of the capacitor 821 is charged positively, and the opposite electrode is charged negatively, and when 1=L, the diode 811 is reverse biased and turns off. , the positively charged side electrode of the capacitor 811, that is, the side electrode connected to the output terminal of the inverter 802, is set to a low level and a potential of 755, so that the negative potential side electrode of the capacitor 821, that is, the side electrode connected to the output terminal of the inverter 802, The potential at the point is (vnn
-Vssj) becomes lower potential. Diode 81 after all
1 and y f 7 821 ramps the output signal φ of the inverter 802 so that its high level becomes the potential of VSS+. Transistor 816 is N-CH-F
ET, the substrate and the source are connected to the capacitor 805 (vl)I), but when the transistor 816 is in the OFF state, the transistor 816
can be considered by replacing it with a diode whose flow direction is the forward direction from the north side to the drain side 11Ui.

In this case, the diode 811 and capacitor 821! 7 VS5. It can be thought of as a circuit that further rectifies the clamped φ signal using the diode 816 and stores the charge in the capacitor 805 by setting the potential of the φ signal to high/bell. Assuming that the output voltage/beadance of the inverter 802 is sufficiently low and is much lower than the impedance of the FETs 812 and 816 in the ON state, the above-mentioned clamping effect is reliably performed and the clamp output The high level at the end 823 is approximately the level of VSS, and the low level is approximately 2.VS2. It is guaranteed that the level will be reached. The expression "approximately" is used here because if the diode causes a forward voltage drop, the flag level will be closer to vDD than vSS1 by that much.

When the potential of the rectifier output terminal 825 is approximately 2.V551, the I/G circuit consisting of FETs 814 and 818 performs an inverter operation with the potential of vSSl and vSSl×2 as the power supply level, and the 8230 level becomes vSSl's Toyu 824 level is 2・VS51 and FET812
Turn on! ='ET 816 is turned OFF, the forward voltage drop of diode 811 is made to disappear under equal constraints, and 823
When 0 level becomes 2 * Vss+, 824 Luher is v
It becomes SSI and turns on FET 816, causing the forward voltage drop of 816 as a diode to fade and disappear. In the end, according to this embodiment, the forward voltage drop component in the diode 9 circuit can be effectively removed, resulting in a highly efficient boosting mechanism.

For example, capacitors 821 and 805 are set to 0.5 μF,
The frequency of the signal φ is 256 Hz, and the FET812
HDIG1030. When the diodes 11 and 816 (which also operate as FETs) were constructed from 3N169, a gravity conversion efficiency of 98% was obtained at a power supply voltage of 1.6 volts for a load of IMΩ. 3 diode 811
When constructed with N169, the gate, substrate, and source are coupled, and a diode is used between the drain/substrate. This configuration is C/MO8-I as is.
Can be made into C. The capacitor 822 and the diode 813 are used when this configuration is operated in a push-pull manner. As a modification of this configuration, a system using a capacitor 822 and a diode 813 by removing the tip 805 and a system using a diode 813 and a diode 822 are used.

The boost system 831γ uses exactly the same principle as above, but the voltage conversion time 1:
11”1.:・.

The only change is to clamp the vSSV2 output of the circuit to the level of □, certain (1/2), and vSS1. In this case, (1:/2)・vSSI to V5. Since (3/2)・vSSl is obtained with the potential shifted by S+,
This is designated as V553/2. By combining the above circuits, vDD (= Q volt ) and vs sl
From the potential of , 1/2.3/2.2 times vSSl
Different voltages are obtained, and considering vSSl as a reference, vS
A potential shifted by 1/2 vSSl in the positive and negative directions from Sl and a potential shifted by exactly vSS+ in the positive and negative directions were obtained, and the liquid crystal display panel was tied with the 1/3 voltage application method.

Driven by the Namitsu Matrix. The meaning of the 1/3 voltage application method is that the ratio of applied voltage at a matrix point selected to be turned on and applied voltage to a point on the matrix selected not to be turned on is 3:1. 841 is a crystal oscillator serving as a time reference source for a clock, and has a frequency of 215'Hz to 2'' Hz.

842 is a timekeeping unit signal synthesis mechanism consisting of a frequency divider; 843
Reference numeral 844 indicates a level conversion circuit, 844 a clock mechanism, 845 a display drive circuit, and 846 a display mechanism.

The feature of this configuration is that information is processed using the low voltage obtained by the voltage reduction circuit, and sufficient energy is applied to only the components that essentially require energy at the most suitable voltage. A device that reliably addresses and drives a low-voltage liquid crystal surface element using a threshold value.
I + 1 ringing, driving a low voltage electromism display element, FE of a pulse motor g@ circuit that requires a large current
By gradually applying a voltage to T to reduce the size of the drive FET, which occupies a large proportion of the IC chip size, partial voltage conversion, which can be expressed as an arbitrary fraction in this application, can be applied to a battery. This is effective in determining voltage and element manochips.

Also, as shown in Motoshu's example, building a low-current ring-on resistor inside the IC, rooting and waveform shaping circuits with low through-current, etc. play an important role in integrating the entire system. Fulfilling.

Figure 9A is a diagram of a matrix of m rows and n columns (m and n are natural numbers) of liquid crystal.
n rows of electrode wires as lower electrodes are formed on the surfaces of the upper electrode glass and the lower electrode glass, respectively, and the electrode wires are stacked facing each other with a narrow gap using an insulating spacer,
Consider a device in which a field-effect liquid crystal is sealed between electrodes facing the nucleus. The explanation will be made regarding lighting and non-lighting of Sij in the i-th row and j-th column (designated segment 1 and J are arbitrary natural numbers) in FIG. 9A. By applying a voltage below the threshold to the portion 901 of Sij when Sij is not lit, and applying a voltage above the threshold for a short period of time when Sij is lit, accurate addressing of display segments can be achieved. Dedicate. In addition to this, in order to achieve matrix drive, it is necessary to have a fast start-up characteristic that allows for short-time drive/curse lighting,
A liquid crystal with a long frame memory time that memorizes the lighting state during the drive pulse cycle, or a liquid crystal with slow falling characteristics, is required, but the above requirements are met here by selecting the liquid crystal cell structure and liquid crystal material. shall be.

φd1 to φdm in FIG. 9B apply potentials to electrode lines specifying rows. The potential φsj specifying the column is obtained by selecting φS and 18 in FIG. 9B.

(...) The specific circuit configuration is shown in Figure 9C. φ3 in Figure 9 specifies the off state, and to turn on only the segment of Sij, it is necessary to turn on only the segment of φdi (6s is specified, and φsj should be set so that φ8 is specified at the low level of φdi, and in order to make only the Sij+i segment light up, when the high level of φdl is set,
φBj+1 so that φS is specified at the old low level
All you have to do is determine. The signal E in Figure 9B is a signal that forms a short circuit that does not go through the power supply circuit when applying an alternating voltage to the liquid crystal segment, and is effective in reducing power consumption when driving capacitive display elements in general. . The voltage applied to the liquid crystal element when it is not lit is expressed as (φdl-φS), and the voltage applied to the liquid crystal element that becomes the lit segment is expressed as (φdi-is), as shown in FIG. 9B. has been done. As is clear from the waveform (φdi−φS), when the lamp is turned on, a voltage three times as high as when the lamp is not lit is applied for a short time.

In FIG. 9C, φsj has Vss1/2 as a high level, vSS] as a midpoint level, and VsS:zo2 as "1".
- Is the signal to be level? , the high level of E is set to the midpoint level, and in other low level states of E, the voltage level is between Vss1/2 and Vss3/2 with a phase equal to φ at the high level of Sj. This becomes a changing signal, and when Sj is at a low level, this changes to a signal with exactly the same phase. φdi sets vDD to high level, VsS2
This is a signal that sets the low level to the midpoint level Vssl at the high level of E or Di, and the low level of 61 sets φ to the midpoint level Vssl.
The signal matches the . In FIG. 9C, signal E93
1. 10933. Di932Di934. φ935, j
sas is at the logical level...Irepel is 'JDD, V
It can be considered as a signal similar to sS2. 91d (:
When the circuit is effective, the relationship between the threshold voltage vTLc of the liquid crystal element and the power supply voltage is as follows, and depending on the value of vTLc, V551/2, VSSL, XVSs372, VsS
By changing the coefficient of the pressure conversion circuit so as to satisfy the above relational expression while leaving the voltage ratio of 2 as -, for example, 1/3 of the power supply voltage,
Create voltages of 2/3, 3/3, and 4/3.

3/3 voltage does not actually require creating a VC, and can be achieved by directly using the battery direct voltage.

In the currently available LCD row A, Vnc = 1.1 vo
lt, so for example 8 in the circuit shown in Figure 9C.
・Rows 2 to 8 rows and 8 columns are driven by IW. In this case, the processing of clearing information t [row 7t at low voltage,
A system in which the display drive signal is, for example, an island voltage whose level is converted to φI-i, is reasonable.

FIG. 10A and FIG. 1'0B show the relationship between the applied pressure and the internal state of a PLZT (zirconate titanate/porous titanate/lead) electrochromic display element. In Fig. 10A, the lighting state is set as point B', the non-lighting state is set as 0 point or Q'=O state, or the lighting status is set as B' and the non-lighting state is set as E'. The methods are different. If Q is the polarization amount, the PLZTFiB' point can be used as a light source, and the points H' to D' can be used as a non-light source, and a voltage of oA' or higher can be applied to light up the area between H' and D'. The use of applying a reverse voltage to turn off the light is interesting. In an electrochromic device, a similar md method is used, where Q is the amount of material deposited electrochemically (the amount deposited on the top surface is defined as positive, and the amount deposited on the back surface is defined as negative).

In the case of PLZT, electrochromism, or elastomer display elements exhibiting the intelligent property shown in Fig. 10B, the charge integral value can be controlled to display even when the light is not lit (triA depending on how it is used).
It is necessary to stop at the position of , or draw a minor loop and stop at the 0 point. If it can be clearly identified as a display element at points B and E, apply a sufficient positive voltage and set it to point B to turn it on, and apply a sufficient reverse voltage and set it to point E to turn it off. It depends on how you use it.

FIGS. 10C and 10E show examples of driving circuits for a PLZT or electrochromic element as a display element having a +20 characteristic as shown in FIG. 1A. The drive circuit is often used even if it is suitable for a display element having the characteristics shown in FIG. 10B.

FIG. 10C shows, for the display signal Sk, the Sk rising differential signal S? which rises slightly at the rising edge of Sk and coincides with the high level of φ and rises at the low level of φ. A circuit for creating a signal So:F that rises in synchronization with the rising edge of φ when Sk falls and falls at the high level of φ. .ST is a signal for turning on the display element, and S0ζ' is a signal for turning off the display element, the waveforms of which are shown in FIG. 10E.

Figure 10 is an example of a drive circuit, in which block 1002 is equivalent to block 1001 in Figure 10C. 10
03 and 10051dP-CH-F'ET, S
7. At the high level of 0z, transistor 003 is O.
The first output of N and φsk can be set to vpD,
80GF high level/l/smell Tetran Sister 00
5 becomes ONK, and the potential of φsk becomes equal to Vs S 1/4. sON and ST″F will never reach a high level at the same time. When SO or STF are both low bells, both transistors/transistors 1003.!=1005fd will be OFF, and the voltage applied to the display element 1006 will depend on the leakage resistance of the element. The inverter 10o4 attenuates to 0 with a time constant determined by the capacitance, or maintains the previously applied voltage.The inverter 10o4 is synchronized with φ, and a signal φCoN that differs only in voltage level in height phase and waveform is obtained. n, this is connected to the common W, +ii potential to the hydrogen element 100 j, ,.In the end, the display confectionery 11
Voltage y applied to a certain segment at a time of 5'7°1006
gc- becomes as shown in FIG.
At the falling edge of k, a boost voltage of 1/2 of the boost voltage for turning on is applied in the opposite direction for turning off the light.

FIG. 11A shows in detail the drive circuit portion of the pulse motor type quartz watch. 1101 is a timekeeping mechanism that operates at low voltage and has functions including crystal oscillation, frequency division, and waveform shaping. Reference numeral 1102 is a level conversion circuit, and in this embodiment, the boost level on the negative potential side is expanded to make it a lower potential.
ll is prepared, Vssl is the level below the negative potential of the ward, and 882 is a double boost output.
=2·Vsst.

Also, Vss1/4 is VSE11/4=1/4 VIl
181 Tel.

1106 and 1104 are FET inverters with a large current capacity t for driving a pulse motor. P-C1(-FET11
11 and 1113 are set to Vss when the input signal is low level.
Since the gate voltage twice l is applied and becomes UN, the ON impedance can be set to fl/4 compared to a normal system without a booster circuit, or the IC for the drive inverter can be
The area ratio of the chip size used internally can be reduced.

, N-/CH-FETs 1112 and 1114 do not have a low ON impedance, but are completely OFF because the low level of the gate power 1106 and 1108 is lower than the source potential in the OFF state. condition is realized and circuit leakage is reduced.

The low voltage operation of the Shinfi1101 for timekeeping and the reduction in output impedance or severe leakage current are significant. To reduce the impedance of N-CH-FET,
The input signals 1105 and 1106 are cut DC with a capacitor, and the low level iV of 1106 is cut with a diode.
It is also possible to clamp it to the level of sθl, connect 1105 directly to the level converter 1102, and connect the input 1106 to the level converter 1102 via an upper dpi capacitor. The same goes for inputs 1107 and 1108, p-CH-FAT human power 1107 is directly driven, N-
CH-lFET input 11υ7 is directly driven, N-CH-F
IT input 1108 may be diode clamped and coupled to input 1104 through a capacitor. V on the positive potential side
Twice as much '-source VDD as DD! It is also possible to drive the inverters 1103 and 1104 with a signal expanded to logic levels vDJJi1 and VB8B by a level converter.

FIG. 11B is a waveform diagram of the signal in FIG. 11A, and FIG. 11C is a waveform diagram of the signal in FIG. 6B.

+2>689 is the output signal of gate 667, Qol...
...QL+6 is the output number 100 of the counter 638, and ρ
6B7C1...ρ68fuC4 is Kara/ri638
is determined from the output of gate 637.

Here, Ch=Qol.

C9=QO1jQQa CB=QO1”Q,) slack・,4oa C4: Qol・Qo2・1.1.08・QO4.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the watch system of the present invention that includes a voltage conversion circuit. Figure 2 is an embodiment of the voltage conversion circuit. Figure 3A is another embodiment of the voltage conversion circuit of the present invention. B is an explanatory diagram of the operation of the voltage converter circuit of the present invention. FIG. 5 is another embodiment of the voltage converter circuit of the present invention. Figure B is an example of a square multiplier circuit in Figure 6. Figure 6 C is an explanatory diagram of the system operation of Figure 6 A. Figure 7 is an example of a level conversion circuit. Example Figure 9A
FIG. 8 is a display element diagram for a liquid crystal matrix drive system using voltage conversion. FIG. 9B is a matrix drive waveform diagram. FIG. 9C is an example of a matrix drive circuit. Type display element characteristic diagram Figure 10 C, L
11A is a circuit example of a pulse 1-motor crystal clock system utilizing the voltage variation shown in FIG. 8. Figure 10E is a waveform diagram for driving an accumulation type display element. FIG. 11B is a drive waveform diagram of the motor drive circuit; FIG. 11C is a signal waveform diagram of FIG. :Level converter 117:Display mechanism 118:Air energy source. Figure 10 (E) 111?1 (B)

Claims (1)

[Scope of Claims] 1) In an electronic timepiece comprising a time reference signal source, a timekeeping unit signal synthesis mechanism, a timekeeping mechanism, a time display mechanism, an external operating member, and an electrical energy supply source, a second signal generation means is provided. Temperature compensation is performed using a signal obtained by combining information about the temperature obtained from the frequency deviation between the frequency of the second signal and the time reference signal and a temperature correction value of the clock using an arithmetic circuit. electronic clock. 2) Stable power supply that suppresses voltage fluctuations in an electronic watch consisting of a time reference signal source, a timekeeping unit signal synthesis mechanism, a timekeeping mechanism, a time display mechanism, an external operating member, an electrical energy supply source, and a second signal generation means. Electronic clock from pressure compensation circuit
supplying electrical energy to some of the components of the temperature measuring circuit, the temperature measuring circuit being driven intermittently to output a temperature measuring signal, and using the temperature measuring data to continuously perform temperature compensation by the front voltage compensation circuit; An electronic clock featuring