JPS6241351B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic timepiece, and more particularly to an electronic timepiece using a lithium battery or the like having relatively high voltage and high internal resistance. The purpose of the present invention is to absorb fluctuations in battery voltage when driving heavy loads such as alarm lamps, and supply a stable constant voltage to the clock circuit even when the battery voltage fluctuates. The objective is to obtain an electronic clock with stable performance. In recent years, the performance of lithium batteries has improved, and they have begun to be used in some watches, and lithium batteries are also attracting attention for extending the lifespan of watches. Lithium batteries usually have a voltage of 3 to 2.8 (V), and the battery capacity is 60 to 3 (V) for watch batteries.
100 (mAH). Complementary MOS/IC for wristwatches
Since it operates satisfactorily at 1.5 (V), we can create a voltage (approximately 1.5 (V)) that is half the battery voltage by direct/parallel switching of the two capacitors and drive the watch IC with this voltage. It is well known that this increases the battery life of a watch. By using this method and the characteristic of a lithium battery having a low self-discharge rate, an electronic wristwatch with a battery life of 5 to 7 years can be realized.
However, when put into practical use, the disadvantage is that the internal resistance of lithium batteries is extremely large. This becomes a problem when the clock has functions such as lamps and alarms that consume a large amount of current during operation. The internal resistance of a normal lithium battery is
It is about 100 (Ω), and the lamp consumption current is reduced to 10 (m).
If A), a voltage drop of 100 (Ω) x 10 (mA) = 1 (V) will occur, and there is a high possibility that the clock circuit will malfunction due to voltage fluctuations. In particular, electronic watches equipped with a liquid crystal drive unit driven by multi-digit multiplex drive require not only the battery power source but also a boosted power level of the battery power source as the liquid crystal drive signal. Even against fluctuations,
This causes a large voltage fluctuation, resulting in a decrease in the contrast of the liquid crystal display. In view of this, the present invention provides a power supply circuit that supplies a stable constant voltage to a clock circuit even if the battery voltage fluctuates during heavy loads such as lamps and buzzers. Hereinafter, an explanation will be given based on one embodiment of the present invention. FIG. 1 is a block diagram of one embodiment of the present invention. Inside the broken line 101 is a watch electronic circuit section, and inside the broken line 102 is a power supply circuit section including a booster circuit. 10
4 is a time standard source such as a crystal oscillator and a frequency dividing circuit for creating a clock signal. A clock signal from 104 is input, and a clock counter 107 counts time. Reference numeral 109 denotes a display decoder and a display drive circuit, which receives count data (1
It may also be the count data of the 08 alarm clock counter. ) and decode it into segment data for display. Reference numeral 111 denotes a display section composed of liquid crystal, LED, etc., which is driven by 109 and functions to perform display based on segment data. 108 is a counter for counting alarm ringing time, which stores the alarm ringing time;
When the time coincidence detection circuit detects coincidence between the alarm setting time and the current time, the buzzer drive circuit 112 drives the buzzer 113. 105 is a group of external input switches, 106 is 10
5 encodes the input signal from the switch group,
This is a switch input encoder that generates various control signals. One of the control signals generated from 106 is input to a lamp lighting control circuit 114, which controls lighting and extinguishing of the lamp 115. That is, the buzzer drive circuit 112 and the lamp lighting control circuit 114 are heavy load circuits. When the buzzer 113 and the lamp 115 are turned on, the current flowing through those loads ranges from several milliamps to over a dozen milliamps, and the voltage drop occurs when the internal resistance of the lithium battery 103 is multiplied by the current. is about 1/2 of the power supply voltage. In the present invention,
During these heavy loads, the OR gate 116 detects the heavy load state and notifies the power supply circuit section 102 of the heavy load state. 119 is a level shifter. Reference numeral 122 denotes an SR latch as a power supply switching circuit that switches between a normal state and a heavy load state. The correspondence with the states is Q=“1”...Heavy load state Q=“0”…Normal state. In the normal state, the Q of 122 is "0", the switching Tr 120 is OFF and the switching Tr 121 is ON, and the power supply circuit uses the Vss ₂ constant voltage source 124 as the reference power source. For example, in the case of Li batteries, the voltage level of Vss ₂ is 2.8 (V) to guarantee battery life.
If the voltage is up to -2.6 (V), then approximately -2.6 (V) is appropriate.
(Therefore, Vss ₁ is about -1.3 (V).) Vss ₂ is generated at a constant voltage of 124, and
117 step-down/
Supplied to the boost circuit. In addition, the step-down/step-up circuit of 117 is the SR of 122.
Functions vary depending on the latch output. That is,

[Table] 117 so that the power generation state shown in the table above is obtained.
works. In other words, under normal conditions, the lithium battery voltage VLi
Since VL ₁ > |Vss ₂ |, |Vss ₂ | is made into a constant voltage, and |Vss ₂ |, which has been made constant voltage, is stepped down by the step-down/step-up circuit 117, and |Vss ₁ | is boosted. Te | Vss ₃ |
form. However, under heavy load conditions caused by driving alarm lamps, etc., as mentioned above, VL ₁ will drop significantly due to the internal resistance of the lithium battery.
It is not possible to make Vss ₂ a constant voltage. Therefore, since VL ₁ > |Vss ₁ |, |Vss ₁ | is made a constant voltage, and |Vss ₁ |, which has been made constant, is boosted by the step-down/boost circuit 117, and |Vss ₂ | is further boosted. Te | Vss ₃ |
form. When a heavy load condition (lamp ON and buzzer ON) is detected by OR gate 116, SR latch 122 is set and its Q output becomes "1". At that time, the switching Tr 120 is turned on, the switching Tr 121 is turned OFF, and the power supply circuit uses the Vss ₁ constant voltage source 125 as a reference power source. The step-down/step-up circuit 117 operates as a step-up circuit, and two power supplies of Vss ₂ and Vss ₃ are generated. On the other hand, in the normal state, the SR latch 122 is reset and its output becomes "1". At that time, the switching Tr 120 is turned OFF, the switching Tr 121 is turned ON, and the power supply circuit uses the Vss ₂ constant voltage source 124 as a reference power source. Then, _{the step-down/step-up circuit 117 steps up Vss 1 and} Vss ₂ , which are steps down from Vss 2.
Two power supplies of Vss ₃ are generated. Further, 123 is a timer circuit which inputs a 1 Hz signal as a clock, and resets the SR latch after counting the time of 1 to 2 seconds. A switching control circuit 118 generates a signal for controlling switching of the capacitance of the step-down/step-up circuit 117 during step-down/step-up operation. The entire system operates as described above, and since a constant voltage is always supplied to the watch electronic circuit,
It is not affected by power fluctuations during heavy loads. FIG. 2 shows the vicinity of the constant voltage circuit in FIG. 1. 200 corresponds to the Vss ₂ constant voltage source 124, and 20
1 corresponds to the Vss ₁ constant voltage source 125. 229,230 N channel MOS/FET is 1
Switching Tr for power supply switching of 21,120
It is. 231 is the SR latch of 122, and 232 is a timer circuit for resetting the SR latches of 122 and 231. Inside 200, there is built-in a differential amplifier made up of 206-210.In 201, there is built-in a differential amplifier made up of 219-223. Under normal conditions, the SR latch 231 is
It is in the reset state due to the output of 229.
N-channel MOS/FET is ON and Vss ₂
is supplied from 200 constant voltage sources. The MOS/FET groups 202 to 205 form a reference voltage to a constant voltage source (both Vss ₁ and Vss ₂ ). In this case, the reference voltage is 204,
The transistors are formed such that the threshold values of the two N-channel MOS/FETs 205 are different. In the differential amplifier circuit formed by MOS/FETs 206 to 210, 206 and 207 are P channel MOS/FETs with exactly the same characteristics and the same size.
9 and 210 also have the same characteristics and the same dimensions. The gate input 206 represents an inverting input, and 207 represents a non-inverting input. Since the reference voltage Vref is input to the gate of 206, so that the potential difference between the gate input potentials of 206 and 207 is "0",
The N-channel MOS/FET 211 operates. Note that 211 is a depletion type N-channel MOS-FET, which, together with resistors 212 and 213, forms an output stage that outputs while shifting the level. Due to the operation of the differential amplifier circuit, a voltage of Vref is always applied to the resistor 212. Therefore
Vss ₂ is determined by the ratio of resistor 212 (resistance value is R ₁ ) and resistor 213 (resistance value is R ₂ ). That is, Vss ₂ =R ₁ +R ₂ /R ₂ ×Vref, and a desired voltage value can be obtained by adjusting the ratio of R ₁ and R ₂ . On the other hand, the Vss ₁ constant voltage source 201 does not operate in the normal state, and constant power consumption is achieved. In the normal state, Q of the SR latch 231 is "0", so the P channel Tr 214 is OFF, the P channel Tr 218 is ON, the P channel Tr 224 is ON, and the N channel Tr 227 is OFF, so that the Vss ₁ constant voltage source 201 is not operated. Moreover, there is no potential floating state inside the power supply. When transitioning from normal state to heavy load state, 231
The SR latch is set and the N-channel Tr230 is
When turned on, Vss ₁ is supplied from the constant voltage source 201. In a heavy load state, the P channel Tr 214 is turned on, the P channel Tr 218 is turned off, the P channel Tr 224 is turned off, and the N channel Tr 227 is turned on, and the Vss ₁ constant voltage source operates. The reference voltage is Vref as in the case of the Vss ₂ constant voltage source 200. In this case as well, the output voltage of Vss ₁ can be determined by the ratio of resistors 215 and 216, as in the normal state. Note that the timer 232 inputs a 1 Hz signal as a clock, and resets the latch 231 after counting 1 to 2 seconds. FIG. 3 shows a timing chart of the transition from the normal state to the heavy load state and the return to the normal state. Next, FIG. 4 shows an example of the step-down/step-up circuit 117 and the switching control circuit 118 in FIG. 40
1 latch, 402, 403 inverter, 40
A group of AND gates 4 to 406 create a signal that controls switching of capacitance during step-down and step-up. AND
The output signals of gates 404-406 are shown as a timing chart in FIG. The "1" level of each signal is not superimposed so that short current does not flow between the power supplies. 40
8,409 is a selector,

[Table] Select the output signal. When the output signal of 404 is at the "1" level, (40
The output signals of 8 and 409 are necessarily “0” level)
All N-channel transistors 416, 419, 420, 421, and 422 are turned off except for the transistors that are turned on, and the capacitor connection form is as shown in FIG. 6a. When the output signal of 408 is "1" level (the output signals of 404 and 409 are necessarily "0" level), the P channel Tr of 412, 417 is ON, and the N channel Tr of 415, 419, 422 is ON.
All transistors other than ON are turned OFF, and the capacitor connection form is as shown in FIG. 6b. When the output signal of 409 is "1" level, (40
(The output signals of 4 and 408 are necessarily at "0" level) The P channel transistors of 414 and 424 are ON The N channel transistors of 411, 413, 416, 418, and 423 are ON The following transistors are all OFF, and the capacitors are connected The form is the 6th
The result is as shown in Figure C. In Figure 4, 413,419 N channel Tr and 414 P
Channel Tr 422, 423 N channel Tr and 424 P
Each Tr group of channel Tr controls the substrate of each N channel Tr of 411 and 418. The capacitor connection configurations (a), (b), and (c) are changed as follows. Under normal conditions, (c)→(b)→(c)→(a)→(c)... Under heavy load, (b)→(c)→(b)→(a)→(b)... Change. In other words, under normal conditions, (a)...Vss ₂ is kept at a constant voltage. Therefore
The voltages across C ₂ , C ₁ , and Cc are Vss ₂ , respectively.
Vss ₂ /2 (=Vss ₁ ) and Vss ₂ /2 (=Vss ₁ ). (b)...Since Cc and C ₁ are connected in parallel, the voltage across them is Vss ₁ . (c)……C ₂ (voltage at both ends is Vss ₂ ) and Cc (voltage at both ends is Vss 2 )
Vss ₁ ) are connected in series. against them
Since C ₃ is connected in parallel, the voltage across C ₃ is
Vss ₃ = Vss ₂ + Vss ₁ . becomes. Also, under heavy load conditions, (a)...Vss ₁ is kept at a constant voltage. Since C ₁ and Cc are connected in parallel, the voltage across them is Vss ₁
It is. (b)...C ₁ and Cc (the voltage across each end is Vss ₁ ) are connected in series. Since C ₂ is connected in parallel to them, the voltage across C ₂ is 2Vss ₁ = Vss ₂
It is. (c)...Same as (c) in normal state. becomes. The above is an example of the step-down/step-up circuit. As understood from the above description, according to the present invention, batteries with large voltage fluctuations under heavy loads (batteries with large internal resistance such as lithium batteries)
It is possible to provide a power supply circuit that does not cause fluctuations in the power supply even when the power supply is used as the power supply. Here, in the present invention, Vss ₂ is made a constant voltage in a normal state and Vss ₁ is made a constant voltage in a heavy load state, but an additional reason is added as to why Vss ₁ is not always made a constant voltage. This will be explained using FIG. In the Vss ₁ system constant voltage source 201 (201 is operating, that is, Tr214 is ON), the voltage I flowing through the resistors 215 and 216 is stabilized by Tr217, which is operating as a constant voltage source. There is. If the voltage of the battery voltage 228 is V _B , then V _B = Vss ₁ + I・(R ₂₁₅・R ₂₁₆ ) Similarly, in the Vss ₂ system constant voltage source, V _B = Vss ₂ + I・(R ₂₁₂ + R ₂₁₃ ). . Now, in the normal state, V _B > Vss ₂ = 2×Vss ₁ . Therefore, I.(R ₂₁₅ +R ₂₁₆ )>I.(R ₂₁₂ +R ₂₁₃ ). In this way, making Vss ₁ a constant voltage in the normal state means that power loss is greater than making Vss ₂ a constant voltage. because,
This is because when Vss ₁ is made a constant voltage, the potential difference becomes larger. Therefore, in normal conditions, the constant voltage Vss ₂ is set to a value close to the battery voltage, and in heavy load driving conditions,
By setting the constant voltage Vss ₁ , which is approximately 1/2 the value of Vss ₂ , a more reliable electronic clock can be realized. In particular, electronic watches equipped with a liquid crystal display driven by multi-digit multiplex drive require a boosted power level from the battery power source as the liquid crystal drive signal, so even small voltage fluctuations in the battery power source can be This causes voltage fluctuations, resulting in a decrease in the contrast of the liquid crystal display. Even in this case, according to the present invention, a constant voltage source is always used as the power source, and a stable liquid crystal display is guaranteed without causing even the slightest fluctuation in the power source. Although this embodiment has been explained using a lithium battery, the present invention is not limited to electronic watches using lithium batteries, but can also be applied to electronic watches using other batteries with relatively high voltage. The invention is applicable.

[Brief explanation of the drawing]

Figure 1: A block diagram showing the configuration of an electronic timepiece according to the present invention, Figure 2: An example of a power supply circuit according to the present invention, Figure 3: In the example of the power supply circuit according to the present invention shown in Figure 2, a heavy load is applied. FIG. 4: An example of a step-down/step-up circuit. FIG. 5: A timing chart of a step-down/step-up control clock. FIG. 6: A connection state diagram of capacitors during step-down/step-up.

Claims (1)

[Claims] 1 Time standard sources such as crystal oscillators, electronic circuits such as frequency dividing circuits and display drive circuits, power batteries with relatively high internal resistance such as lithium batteries, lamps and lamps that are powered by such power batteries and which flow relatively large currents. A heavy load circuit consisting of an alarm etc., a first constant voltage circuit consisting of a MOS/FET that steps down the voltage of the power supply battery to a first constant voltage value Vss ₂ lower than the voltage of the power supply battery, and the first Constant voltage value Vss ₂
a second constant voltage circuit composed of a MOS/FET that steps down the voltage of the power supply battery to a second constant voltage value Vss ₁ lower than the first constant voltage value Vss ₂ ;
a step-down circuit that steps down the voltage of the second constant voltage value Vss ₁ to create a first voltage value lower than the first constant voltage value Vss ₂ ;
A booster circuit that creates a second voltage value higher than Vss ₁ , inputting the output signal from the heavy load circuit,
When the heavy load circuit is not operating, the electronic circuit is operated by the first constant voltage value Vss ₂ based on the first constant voltage circuit and the step-down circuit and the first voltage value, and the heavy load circuit An electronic device comprising: a power supply control circuit that operates the electronic circuit using the second constant voltage value Vss ₁ based on the second constant voltage circuit and the booster circuit and the second voltage value when the electronic circuit is in operation. clock.