JPS5873655U - Reception frequency display device - Google Patents

Reception frequency display device

Info

Publication number
JPS5873655U
JPS5873655U JP16848081U JP16848081U JPS5873655U JP S5873655 U JPS5873655 U JP S5873655U JP 16848081 U JP16848081 U JP 16848081U JP 16848081 U JP16848081 U JP 16848081U JP S5873655 U JPS5873655 U JP S5873655U
Authority
JP
Japan
Prior art keywords
display device
circuit
received frequency
frequency display
reception frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16848081U
Other languages
Japanese (ja)
Inventor
秀次 川崎
増原　正美
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP16848081U priority Critical patent/JPS5873655U/en
Publication of JPS5873655U publication Critical patent/JPS5873655U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案に係る受信周波数表示装置を示す図、第
２図はセグメントを示す図、第３図は動作波形図である
。 １はデジタルシンセサイザチューナー用ＩＣ（第１回路
）、２は表示駆動用ＩＣ（表示駆動回路）、３は表示器
、４は消灯検出回路、５はタイミング付与回路。FIG. 1 is a diagram showing a received frequency display device according to the present invention, FIG. 2 is a diagram showing segments, and FIG. 3 is an operating waveform diagram. 1 is a digital synthesizer tuner IC (first circuit), 2 is a display drive IC (display drive circuit), 3 is a display, 4 is a light-off detection circuit, and 5 is a timing provision circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所定のタイミングで受信周波数データを出力する第１回
路と、この第１回路の出力をラッチし、このラッチ内容
に基いて受信周波数表示データを出力する表示駆動回路
と、この受信周波数表示データに基いて受信周波数を表
示する表示器と、この表示器の消灯を検出する消灯検出
回路と、この消灯検出回路の出力に応答して前記消灯後
一定期間経過後に前記第１回路に対して受信周波数デー
タを出力すべきタイミングを与えるタイミング付与回路
とよりなる受信周波数表示装置。A first circuit that outputs received frequency data at a predetermined timing, a display drive circuit that latches the output of this first circuit and outputs received frequency display data based on the latched contents, and a display drive circuit that outputs received frequency display data based on the received frequency display data. a display device that displays the received frequency when the display device is turned off; a light-off detection circuit that detects when the display device is turned off; A reception frequency display device comprising a timing giving circuit that gives the timing at which the signal should be output.
JP16848081U 1981-11-11 1981-11-11 Reception frequency display device Pending JPS5873655U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16848081U JPS5873655U (en) 1981-11-11 1981-11-11 Reception frequency display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16848081U JPS5873655U (en) 1981-11-11 1981-11-11 Reception frequency display device

Publications (1)

Publication Number Publication Date
JPS5873655U true JPS5873655U (en) 1983-05-18

Family

ID=29960529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16848081U Pending JPS5873655U (en) 1981-11-11 1981-11-11 Reception frequency display device

Country Status (1)

Country Link
JP (1) JPS5873655U (en)

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