JPS587356U - Lead frame for resin-encapsulated semiconductor devices - Google Patents

Lead frame for resin-encapsulated semiconductor devices

Info

Publication number
JPS587356U
JPS587356U JP1981100697U JP10069781U JPS587356U JP S587356 U JPS587356 U JP S587356U JP 1981100697 U JP1981100697 U JP 1981100697U JP 10069781 U JP10069781 U JP 10069781U JP S587356 U JPS587356 U JP S587356U
Authority
JP
Japan
Prior art keywords
resin
hole
lead frame
semiconductor device
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981100697U
Other languages
Japanese (ja)
Inventor
西川　幹雄
博之 藤井
横沢　真覩
立野　健一
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP1981100697U priority Critical patent/JPS587356U/en
Priority to CA000406545A priority patent/CA1195782A/en
Priority to DE198282106033T priority patent/DE69390T1/en
Priority to EP82106033A priority patent/EP0069390B1/en
Priority to DE8282106033T priority patent/DE3277757D1/en
Priority to US06/395,799 priority patent/US4482915A/en
Publication of JPS587356U publication Critical patent/JPS587356U/en
Priority to CA000471714A priority patent/CA1213678A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のリードフレームの形状を示す平面図、第
２図は同リードフレームを用いて形成した樹脂封止形半
導体装置の断面図、第３図は来者　　　案のリードフレ
ーム・の一実施例を示す平面図、第４図は同リードフレ
ームを用いて形成した樹脂封止形半導体装置の構造を示
す断面図、第５図は本考案のリードフレームを用いた場
合の封止金型内の樹脂の流れを説明するための模式図で
ある。 １・・・・・・共通接続細条、２．　３．　４・・・・
・・外部り−ド部、５・−・・・・基板支持部、６・・
・・・・移送ピッチならびに位置決定用の孔、７．１４
・・・・・・貫通孔、８・・・・・・半導体基板、９，
１０・・・・・・金属細線、１２・・・・・・成型樹脂
、１３・・・・・・ねじ止め用の孔、１５．１６・・・
・・・金型、１７・・・・・・ゲート、１８・・・・・
・間隙。Figure 1 is a plan view showing the shape of a conventional lead frame, Figure 2 is a cross-sectional view of a resin-encapsulated semiconductor device formed using the same lead frame, and Figure 3 is a part of the lead frame proposed by the visitor. A plan view showing an embodiment, FIG. 4 is a cross-sectional view showing the structure of a resin-sealed semiconductor device formed using the lead frame, and FIG. 5 is a mold for sealing when using the lead frame of the present invention. FIG. 3 is a schematic diagram for explaining the flow of resin inside the container. 1... Common connection details, 2. 3. 4...
...External lead part, 5... Board support part, 6...
...Transfer pitch and positioning holes, 7.14
...Through hole, 8...Semiconductor substrate, 9,
10... Thin metal wire, 12... Molded resin, 13... Hole for screwing, 15.16...
...Mold, 17...Gate, 18...
·gap.

Claims (4)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）　　共通接続細条から同一方向にのびる複数本の
外部リード部の１本の先端部に繋る基板支持部に、これ
を貫通するねじどめ用の第１の孔が穿□設され、さらに
、前記基板支持部を貫通する第２の孔が穿設されている
巳とを特徴とする樹脂封止形半導体装置用リードフレー
ム。(1) A first hole for screwing is bored through the substrate support part connected to the tip of one of the plurality of external lead parts extending in the same direction from the common connection strip. A resin-sealed lead frame for a semiconductor device, further comprising: a second hole penetrating through the substrate support portion. （２）第２の孔の少くとも１部が基板支持部のほぼ中央
部に位置していることを特徴とする実用新案登録請求の
範囲第１項に記載の樹脂封止形半導体装置用リードフレ
ーム。(2) A lead for a resin-sealed semiconductor device according to claim 1, wherein at least a portion of the second hole is located approximately in the center of the substrate support portion. flame. （３）第２の孔の１部が第１の孔と連繋していることを
特徴とする実用新案登録請求の範囲第１項に記載の樹脂
封止形半導体装置用リードフレーム。(3) The resin-sealed lead frame for a semiconductor device according to claim 1, wherein a portion of the second hole is connected to the first hole. （４）第１の孔と第２の孔が離間していることを特徴と
する実用新案登録請求の範囲第１項に記載の樹脂封止形
半導体装置用リードフレーム。(4) The resin-sealed lead frame for a semiconductor device according to claim 1, wherein the first hole and the second hole are spaced apart from each other.
JP1981100697U 1981-07-06 1981-07-06 Lead frame for resin-encapsulated semiconductor devices Pending JPS587356U (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP1981100697U JPS587356U (en) 1981-07-06 1981-07-06 Lead frame for resin-encapsulated semiconductor devices
CA000406545A CA1195782A (en) 1981-07-06 1982-07-05 Lead frame for plastic encapsulated semiconductor device
DE198282106033T DE69390T1 (en) 1981-07-06 1982-07-06 LADDER FRAME FOR SEMICONDUCTOR ARRANGEMENT IN PLASTIC ENCLOSURE.
EP82106033A EP0069390B1 (en) 1981-07-06 1982-07-06 Lead frame for plastic encapsulated semiconductor device
DE8282106033T DE3277757D1 (en) 1981-07-06 1982-07-06 Lead frame for plastic encapsulated semiconductor device
US06/395,799 US4482915A (en) 1981-07-06 1982-07-06 Lead frame for plastic encapsulated semiconductor device
CA000471714A CA1213678A (en) 1981-07-06 1985-01-08 Lead frame for plastic encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981100697U JPS587356U (en) 1981-07-06 1981-07-06 Lead frame for resin-encapsulated semiconductor devices

Publications (1)

Publication Number Publication Date
JPS587356U true JPS587356U (en) 1983-01-18

Family

ID=29895379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981100697U Pending JPS587356U (en) 1981-07-06 1981-07-06 Lead frame for resin-encapsulated semiconductor devices

Country Status (1)

Country Link
JP (1) JPS587356U (en)

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