JPS5873182A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPS5873182A JPS5873182A JP17180281A JP17180281A JPS5873182A JP S5873182 A JPS5873182 A JP S5873182A JP 17180281 A JP17180281 A JP 17180281A JP 17180281 A JP17180281 A JP 17180281A JP S5873182 A JPS5873182 A JP S5873182A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- land
- conductor land
- lands
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は電子機器1こおいて用いられる7リント配線板
に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a 7-lint wiring board used in electronic equipment 1.
(2)技紺の背景
電子計算機等の電子機器にあっては、半得体集積回路累
子(装置)の高集租化に伴って、より小型化、多様畦化
が図られつつあり、かかる電子機器内に配設され前記半
導体集秋回路装置郷の電子部品が搭載されるプリント配
線板に対しても更に高密度な配線の実現が要求されてい
る。(2) Background of Gikon Electronic devices such as computers are becoming smaller and more diverse as semi-integrated integrated circuit devices (devices) become more densely packed. Printed wiring boards disposed in electronic equipment and on which electronic components of the semiconductor integrated circuit device are mounted are also required to realize higher density wiring.
(3)従来技哲と問題点
かかるプリント配線板において配線の高密度化を図る際
には多層化が行なわれ、内層のプリント配線板に形成さ
れた配線は表面層にプリント配線板に設けられた導体ラ
ンドに電気的に導出される。(3) Conventional technology philosophy and problems In order to increase the density of wiring in such printed wiring boards, multilayering is performed, and the wiring formed on the inner layer of the printed wiring board is provided on the surface layer of the printed wiring board. It is electrically led out to the conductor land.
したがって、かかる多層プリント配線板勢ζこありては
、表面層プリント配線板に配設される導体ランドが非常
に多数となる。Therefore, in such a multilayer printed wiring board system, a large number of conductor lands are provided on the surface layer printed wiring board.
このため、かかる表面層プリント配線板に配設された導
体ランドに対し、電子部品を実装する際あるいはリード
線を接続する際には、接続すべき導体ランドのμ識が困
難となり、前配電子部品の実装あるいはリード線の接続
等の作業性が低下する傾向にあった・
そこで前記導体ランドの座椋位償を示す手段として従来
、第1図に示されるように、絶縁基板11の表面にマト
リックス状に配設される複数個の導体ランド12のうち
の所定箇庖の導体ランドの近傍に、例えばスクリーン印
刷法によりて数字13あるいは記号14を印刷して当該
導体ランドの座標位置を示す方法がとられている。なお
12′はスルーホールである。For this reason, when mounting electronic components or connecting lead wires to the conductor lands arranged on such surface-layer printed wiring boards, it becomes difficult to identify the conductor lands to be connected. The workability of mounting components or connecting lead wires has tended to deteriorate.Therefore, as a means of indicating the level compensation of the conductor land, as shown in FIG. A method of printing a number 13 or a symbol 14 near a predetermined number of conductor lands among a plurality of conductor lands 12 arranged in a matrix by, for example, a screen printing method to indicate the coordinate position of the conductor land. is taken. Note that 12' is a through hole.
しかしながらこのようなインクを用いての印桐法による
座標位置の表示は、導体ランドの形成と座標位置を示す
数字あるいは記号の印刷とが別の工程において行なわれ
るために、工程の増加を来たすうえ、導体ランドと座標
位置を示す数字あるいは記号との位置合わせか困難であ
り、史に前記インクが導体ランドへ付層するかあるいは
該導体ランドに設けられたスルーホール中へ侵して、該
導体ランドへの電子部品あるいはリード線の接続を困難
にする等の問題が存在していた。However, displaying coordinate positions using such ink using the Inkuri method requires an increase in the number of steps because the formation of the conductor land and the printing of numbers or symbols indicating the coordinate positions are performed in separate processes. However, it is difficult to align the conductor land with the numbers or symbols indicating the coordinate position, and the ink may adhere to the conductor land or penetrate into the through hole provided in the conductor land, causing the conductor land to become damaged. There have been problems such as making it difficult to connect electronic components or lead wires to the device.
(4)発明の目的
本発明はこのような従来の芸術の有する欠点を除去し、
プリント配線板上に配設される導体ランドの座標位置を
明示することができる構成を提供しようとするものであ
る。(4) Purpose of the invention The present invention eliminates the drawbacks of the conventional art,
The present invention aims to provide a configuration that can clearly indicate the coordinate position of a conductor land arranged on a printed wiring board.
(5ン 発明の構成
このため本発明によれば、絶縁基板の表面に複数の導体
ランドが配設されてなるプリント配線板において、前記
複数の導体ランドのうち所望の導体ランドは、その形状
が他の導体ランドと異ならしめられるかおよび7才たは
導体ランド内に文字又はI符号が付されて、その位置が
示されてなるプリント配線板が提供されることをamと
する。(5) Structure of the Invention Therefore, according to the present invention, in a printed wiring board in which a plurality of conductor lands are arranged on the surface of an insulating substrate, a desired conductor land among the plurality of conductor lands has a shape that is It is intended that a printed wiring board is provided which is made to be different from other conductor lands and has a letter or I symbol attached within the conductor land to indicate its position.
(6)発明の実施例 以下本発明を実施例をもって評細に説明する。(6) Examples of the invention The present invention will be explained in detail below using examples.
第2図及び第3図は、本発明によるプリント配線板の′
!I4敗を示す◎
図において、21は絶縁基板、22は前記絶縁基板21
の表面に配設された導体ランド、23は前記導体ランド
22内に設けられた層間接続用スルーホールである。2 and 3 show the printed wiring board according to the present invention.
! Indicates I4 failure◎ In the figure, 21 is an insulating substrate, 22 is the insulating substrate 21
A conductor land 23 provided on the surface of the conductor land 22 is a through hole for interlayer connection provided in the conductor land 22.
不発Qi41こよれば、前記導体ランド22の配列にお
いて、遣損された所定位置の導体ランドの形状を他の導
体ランドと異ならしめる(第2図)か、あるいは所定位
置の導体ランド内に文字あるいは記号等を描く(第3図
)。Misfire Qi41 Accordingly, in the arrangement of the conductor lands 22, the shape of the damaged conductor land at a predetermined position is made different from the other conductor lands (Fig. 2), or characters or letters are written in the conductor land at the predetermined position. Draw symbols, etc. (Figure 3).
第2図に示される実施例にあっては、マトリックス状に
配列された導体ランドのうち、X方向及びY方向に3個
置に当該導体ランド24Q)形状を変更せしめた例を示
す。すなわち標準的な導体ランドが円形を有するのに対
し、指標となる導体ランドは矩形あるいは多角形とされ
て、かかる導体ランド配列の座標位置を示す。The embodiment shown in FIG. 2 shows an example in which the shape of the conductor lands 24Q) is changed every three in the X direction and the Y direction among the conductor lands arranged in a matrix. That is, while a standard conductor land has a circular shape, a conductor land serving as an index is rectangular or polygonal and indicates the coordinate position of the conductor land array.
また第3図に示される実施例にあっては、マトリックス
状に配列された導体ランド25のうち、X方向、X方向
に3個置に当該導体ランドに文字例えばアルファベット
を描き込んた例を示す。すなわち標準的な導体ランドが
円形であるのに対し、指標となる導体ラン1°にはA、
B等の文字記号が描かれ、かかる導体ランド配列の座標
位置を示す。Further, in the embodiment shown in FIG. 3, among the conductor lands 25 arranged in a matrix, characters, for example, alphabets, are drawn on the conductor lands at every third position in the X direction. . In other words, while a standard conductor land is circular, the index conductor run 1° has A,
A letter symbol such as B is drawn to indicate the coordinate position of such conductor land array.
このような導体ランドの形状の変更あるいは導体ランド
への文字の賓き込みは、絶縁基板の表面に形成された鋼
箔等の導体層をフォト・エツチングして導体ランドを形
成する際に、フォト・レジスト層に描かれるパターンを
所望形状とすることにより、かかる導体ノくターンの形
成招くことなく、所定の導体ランドに対しその位置を示
すパターンを形成すること、ができる。Changing the shape of the conductor land or adding letters to the conductor land in this way is done when the conductor land is formed by photo-etching a conductor layer such as steel foil formed on the surface of the insulating substrate. - By making the pattern drawn on the resist layer into a desired shape, it is possible to form a pattern indicating the position of a predetermined conductor land without causing the formation of such conductor turns.
なお前記実施例にあっては、導体ランドの形状を変更す
る場合と、導体ランドに文字、記号を付与する場合とを
別々に示したが、本考案はこれに限られるものではなく
、両実施例を組み合わせてもよいことはもちろんである
。In the above embodiment, the case where the shape of the conductor land is changed and the case where characters and symbols are added to the conductor land are shown separately, but the present invention is not limited to this, and both implementations are shown separately. Of course, examples may be combined.
fit<1図は従来のプリント配線板における導体ラン
ドの位[表示w4成を示す平面図、第2図及び第3図は
本発明によるプリント配線板における導体ランドの位置
表示構成を示す平面図である。
図において、11.21・・・絶縁基板12.22・・
導体ランド
12’、23・・・スルーホール
24.25・・・本考案にかかる導体ランド耳 2 図fit<1 Figure is a plan view showing the position of the conductor land on a conventional printed wiring board (display w4 configuration), and Figures 2 and 3 are plan views showing the position display configuration of the conductor land on the printed wiring board according to the present invention. be. In the figure, 11.21...Insulating substrate 12.22...
Conductor lands 12', 23... Through holes 24, 25... Conductor land ears according to the present invention 2 Figure
Claims (1)
リント配線板において、前記複数の導体ランドのうち所
望の導体ランドは、その形状が他の導体ランドと異なら
しめられるかおよび/または導体ランド内Iこ文字又は
4符号が付されて、その位置か示されてなることを特許
とするプリント配線板。In a printed wiring board in which a plurality of conductor lands are arranged on the surface of an insulating substrate, a desired conductor land among the plurality of conductor lands has a shape different from that of other conductor lands and/or a conductor land having a shape different from that of the other conductor lands. A printed wiring board that is patented in that it is marked with an inner I character or a 4 symbol to indicate its position.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17180281A JPS5873182A (en) | 1981-10-27 | 1981-10-27 | Printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17180281A JPS5873182A (en) | 1981-10-27 | 1981-10-27 | Printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5873182A true JPS5873182A (en) | 1983-05-02 |
Family
ID=15929979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17180281A Pending JPS5873182A (en) | 1981-10-27 | 1981-10-27 | Printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5873182A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62170666U (en) * | 1986-04-18 | 1987-10-29 | ||
WO2017094283A1 (en) * | 2015-11-30 | 2017-06-08 | 株式会社村田製作所 | Package board, mother board, electronic component, and acoustic wave device |
-
1981
- 1981-10-27 JP JP17180281A patent/JPS5873182A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62170666U (en) * | 1986-04-18 | 1987-10-29 | ||
WO2017094283A1 (en) * | 2015-11-30 | 2017-06-08 | 株式会社村田製作所 | Package board, mother board, electronic component, and acoustic wave device |
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