JPS5868378A - Defect compensation system for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To compensate defect of a solid-state image pickup element at a high speed by using delay elements and writable memory in combination, and using the mean value of pieces of information before and after the defect for the compensation. CONSTITUTION:Pieces of information on a defective point and defect in a solid- state image pickup element are stored in a memory M. When defect exists, an OR gate 16 outputs (1) and the mean value of the input signal to an input signal and a signal two units delayed behind said input signal appears at an output terminal 4. This means value is used as the output signal of the defective position for compensation, and consequently the simple constitution compensate a solid-state image pickup element with individual defect sufficiently at a high speed and also realizes IC-implementation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for obtaining an output signal by compensating for a defective portion in a solid-state image pickup device.

For example, the solid-state image sensor has a size of 400 in the horizontal direction and 25 in the vertical direction.
It consists of many pixels, such as 0, and is scanned sequentially to extract video information as an analog signal, but even if a manufacturing defect occurs in some of these pixels, this If it can be used while compensating for this, manufacturing performance will be improved.

Conventionally, this defect compensation method uses a one-line delay line,
There was a method of compensating by creating an average value with the next line, but this did not sufficiently compensate for defects.

Another method is to encode the entire screen, store it in memory, and calculate the surrounding areas to compensate for the defect, but this method requires a large device and is not used for images that change rapidly. It was impossible.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method capable of solving these conventional drawbacks and sufficiently compensating for solid-state image sensors having individual defects at high speed with a simple configuration. The defect is complemented by the average value of the information before and after the defect, and it is highly practical as it can be integrated into an IC.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of implementing the method of the present invention, and shows a circuit configuration for compensating for a single point defect in the horizontal direction.

In the figure, 1 is the time-series signal input of the imaging output signal of the solid-state imaging device, and 2, 2/ is the time-series signal input of the imaging output signal of the solid-state imaging device, and 2, 2/ is the time-series signal input of the imaging output signal of the solid-state imaging device. It is a delay element that delays by the amount of

3 and 3' are switch elements, and 4 is an output terminal.

6 is a power supply circuit, 6 is a circuit for setting the amplitude to H, and 6 and 6 together constitute an averaging circuit.

A counter 7 is counted by the clock 8 of the solid-state image sensor and reset by the horizontal blanking signal 9. 10 is a counter that is counted by the vertical clock 11 of the solid-state image sensor and reset by the vertical blanking signal 12.

Output lines 13.13...14 of counter 10
, 14... and read lines 15, 16'...
. . 16" constitutes a memory M as a foods ROM. The read line drives switches 3 and 3' by an OR gate 16 and an inverter 17.

The output of the counter 7.10 represents the address information of the pixels on the imaging surface 1. If the fuse 18 of the fuse RQM is cut off at the address corresponding to the defective location and that information is written, one of the inputs of the OR gate 16 at the defective address becomes 1, and its output changes from ``Q'' to ``1''. becomes.

When the output of the OR gate 16 is "0" (ie, there is no defect), the switch 3 is turned on and the switch 3' is turned off. At this time, the output signal of output terminal 4 is equal to the input signal of input terminal 1.
The signal is delayed by a unit time. (Ignoring other circuit errors) In case of defective address, OR gate 1
The output of 6 becomes "1#", and the average value of the input signal of input terminal 1 and the signal delayed by 2 units from that input signal is applied to output terminal 4.

FIG. 2 illustrates the relationship between these signals, where 19 is the input signal of input terminal 1, 2o is the signal delayed by 1-L units of time, and the signal delayed by 21 units of time.

Now, the signal at the output terminal is delayed by one unit time, so during the time indicated by the dotted line in the figure, the signal (diagonal line in the figure) is missing, but at this time, the average value of AB before and after that time appears at the output terminal.

The above example is a case where the defect is for one pixel, but in reality, there may be cases where the defect is for two pixels.

In this case, as shown in FIG. 3, the input signal from input terminal 1 is delayed by 4 units. Switch 22 is normally 2
The input signal from input terminal 1, which is facing 2', is 2'.
It appears at the output terminal 4 after a delay of unit time. Switches 24 and 23 switch 24' and 23" when the defect is one pixel.
and work as the circuit described earlier. If the defect spans two pixels, information indicating that it spans two pixels is written in the fuse ROM, and when this is detected, the first pixel is 24', and the next pixel is 23'. 24
”.

23".

In FIG. 4, 26 is an input signal, 26, 27, . . . , 29 are signals delayed by 1 to 4 units, respectively, and the shaded areas indicate defective areas. In this case, the output is delayed by 2 units, so if we consider signal 27 as a reference, when the first defective part arrives (i.e., dotted line aO), the output is the average of signal 26, which is delayed by 1 unit, and signal 29, which is delayed by 4 units. If the average value of the input signal 26 and the signal 28 delayed by three units is output in the next one unit time, the defective signal is replaced with the average value of the signals before and after it.

As mentioned above, for example, in the case of 400 x 260 pixels, the outputs of counter 7 and counter 1o are 9 bits each,
It is 8 bits, and 1 bit is sufficient for memory where the defect is 1 pixel or 2 pixels. Therefore, as a ROM to compensate for 16 defective locations, + (9+8)X2+11 X1
6=560 bits is sufficient. Of course, memory other than Who's ROM may be used.

As described above, according to the method of the present invention, it is possible to effectively compensate for defects in a solid-state image sensor at high speed by combining a plurality of delay elements and a writable memory. and set it as ROM (EAflOM
and EX-Of (gate no group 7' combination etc. or fuse RO
It can be easily done by combining M and BBD $ child, etc., and IC
It also has the advantage of being extremely easy to convert.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of a device that implements the defect compensation method for a solid-state image sensor of the present invention, Fig. 2 is a schematic diagram of signals showing its operation, and Fig. 3 shows a continuous defect of two pixels in one line. FIG. 4 is a partial block diagram of the compensation circuit in a certain case, and is a schematic diagram of signals showing its operation. 2.2'...Delay element, 6...Addition circuit, 6...% circuit, 3,3'...
・Switch circuit, 7.10...Counter, M・
·····memory. Name of agent: Patent attorney Toshio Nakao and one other person #I
1 Figure 142 Figure 3 Figure 2

Claims (1)

[Claims] A solid-state imaging device characterized in that a defective location in the solid-state imaging device and information about the defect are stored in a memory, and the average value of signals before and after the defective location is complemented as an output signal at the defective location. Defect compensation method.