JPS6225391A - Image processing method - Google Patents

Abstract

PURPOSE:To accurately detect the defective part of an object to be detected by obtaining an extremal value at a picture element level for each scan line, accumulating it in a memory having the number of picture elements for each scan line, level- discriminating the difference between the extremal value concerned and that right before said value and executing the proper binarization processing. CONSTITUTION:The extremal value at a level for each picture element, which changes in a horizontal scan direction, is selectively updated, and simultaneously a threshold M is detected with the extremal value as a reference, whereby a horizontal floating vinarization circuit 2 introducing a defect signal detects a defect part fluctuating in the horizontal direction. Am extremal value holding memory 17 having the same storage cell as that of the picture element in a horizontal scan line sequentially updates the extremal value at a level for each picture element changing in a vertical scan direction, and simultaneously detects the picture element at a level exceeding a threshold M using the extremal value as a reference. Then a vertical floating binarization circuit 3 introducing the defect detecting signal extracts the defective part fluctuating in the vertical direction corresponding to r-number of picture elements on each vertical scan line.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image processing method for extracting defective portions included in image data obtained by imaging an object to be detected and performing binarization processing.

A conventional image processing method for extracting defective parts appearing on the surface of an object to be detected involves, for example, irradiating the object to be detected with light from a light source, capturing the image with an industrial television camera, and Image data from this industrial television camera is binarized by a binarization circuit with a fixed threshold value and stored in an image memory, and the binarized data stored in the 1W image memory is processed through a processing circuit. The data is then output to an external agent such as a display device to extract defective parts.

In such prior art, the threshold value of the binarization circuit is fixed, and there is a problem in that accurate binarization processing cannot be performed when shading due to uneven illumination or the like exists.

Purpose The purpose of the present invention is to provide an image processing method that solves the above-mentioned technical problem and that can accurately perform binarization processing to reliably extract defective parts of a detected object. It is to be.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The binarization circuit 1 according to the present invention basically consists of horizontal 70-
An analog video signal from an imaging system that performs two-dimensional raster scanning like a television camera, including a 70-digit digital conversion circuit 2, a vertical 70-digit conversion circuit 3, and an analog/digital conversion circuit 4.4a. are converted from analog to digital by analog/digital conversion circuits 4 and 4a, respectively. The analog/digital conversion circuit 4 has a horizontal 70-
The analog/digital conversion circuit 4a is connected to the vertical 70-digital binary conversion circuit 3.

The image data digitized by the analog/digital conversion circuit 4 is transferred to the line! 1.72, no 3°! 4 to an extreme value detection circuit 6, a one-pixel delay circuit 7, an extreme value holding register 8, and a 1-subtraction absolute value calculation circuit 9, respectively. The extreme value detection circuit 6 also has a line! Image data delayed by m pixels from the one-pixel delay circuit 7 is provided via the pixel delay circuit 5.

In the extreme value detection circuit 6, the delay from the 1-pixel delay circuit 7 is detected.

The level of the data is compared with the level of the current image data from the analog/digital conversion circuit 4 provided via the line 1, and when the level difference is zero or a value close to zero, this is determined as an extreme value. Detected as. Here, the term "extreme value" collectively refers to the maximum value and the minimum value of the level of each consecutive pixel on each scanning fin.

The output from the extreme value detection circuit 6 is line! 6 to the subtraction absolute value calculation circuit 10. The subtraction absolute value calculation circuit 10 also includes a line J! 7, the output from the extreme value holding register 8 is applied.

The subtraction absolute value calculation circuit 10 uses the current extreme value from the extreme value detection circuit 6 (hereinafter referred to as the current extreme value) and the extreme value immediately before the current extreme value from the extreme value holding register 8 (hereinafter referred to as the old extreme value). Called value J:)
and the absolute value of the calculation result is applied to one input terminal of the comparator circuit 11 via line 8. Comparison circuit 1
The output from the change value setting circuit 12 is applied to the other input terminal of the input terminal 1 via the line 9. The comparison circuit 11 compares the subtracted absolute value from the subtracted absolute value calculation circuit 1o with a change value preset by the change value setting circuit 12. The way the comparison circuit 11 comes out is the line! 10 to the extreme value holding register 8. When the subtracted absolute value is less than or equal to the change value in the comparison circuit 11, the extreme value holding register 8 updates the old extreme value already held with the current extreme value in response to the output from the comparison circuit 11. , is configured not to update when the absolute value of subtraction exceeds the change value.

The extreme value held in the extreme value holding register 8 is given to the subtraction absolute value calculation circuit 9 via the line node 11. The subtractive absolute value calculation circuit 9 is supplied with digitized image data from the analog/digital conversion circuit 4 via the line 4 as described above. The subtraction absolute value calculation circuit 9 calculates the level difference between the current image data from the line 4 and the extreme value from the extreme value holding register 8 as a reference.
Line the absolute value of that subtraction! 4 to one input terminal of the comparison circuit 13' through 12. The other input terminal of the comparison circuit 13 is connected to the line! It is connected to a threshold setting circuit 14 via 13. In the comparison circuit 13, the subtraction absolute value calculation circuit 9
The absolute value of the subtraction from the threshold value M is compared with the threshold value M preset by the threshold setting circuit 14, and if the absolute value of the subtraction exceeds the threshold value M, a low level signal is sent to the line node 14, for example. (defect detection signal). In this way, the extreme value of the level of each pixel that changes in the horizontal scanning direction is selectively updated, the threshold value M is set based on the extreme value, and the data whose level exceeds the threshold value M is By detecting and deriving a low-level signal (defect detection signal), it becomes possible to detect defective portions that change in the horizontal direction.

The image data digitized by the analog/digital conversion circuit 5 is sent to the vertical 70-digital binarization circuit 3. The configuration of the vertical 70-ting binarization circuit 3 is as follows:
Similar to the configuration of the horizontal 70-ting binarization circuit 2,
Corresponding parts are given the same reference numerals with the suffix "a". This vertical 70-ting binarization circuit 3C includes an n-line delay circuit 16 in place of the one-pixel delay circuit 7. In addition, in place of the extreme value holding register 8, an extreme value holding memory 17, an analog counter 18, and a clock generation circuit 19 are provided. The operating state of the vertical 70-ting binarization circuit 3 will be described below with reference to FIGS. 2 and 3.

In the $2 diagram, a line 20 represents the level of each consecutive pixel in one vertical scanning line. Each extreme value of the level of this line 20 is, for example, a reference frame P1 to
It is represented by P5. Figure 3 (1) and Figure 3 (2) show the array of image data for one horizontal scan of the sensor, and by sequentially reading this image data from left to right, serial An image signal is obtained. Figure 3 (2
) represents image data delayed by n horizontal scanning lines from that in FIG. Vertical 70-ting binarization circuit 3
Then, as shown in Figure 3 (3), 1 pixel is
The device is equipped with an extreme value holding memory 17 having a total of one store cell 61 to G (in this embodiment, r=256). Each store cell G1 to G of the extreme value holding memory 17 is
When updating r, the address counter 18 is counted up by the clock signal from the clock generation circuit 19 to create 7 addresses of the extreme value holding memory 17, and as described later, for example, the Gjth store cell is The stored opening value can be updated with the current extreme value, or the opening value can be maintained as is. Such an address signal will be 8 bits if, for example, one horizontal scanning line is composed of 256 pixels. For example, Plr.
When the Ejtr-th current data shown in FIG. 3 (1) is read out, the Fj-th delayed data shown in FIG. 3 (2) corresponding to the current data is read out. The extreme value holding memory 17 is a random access memory having a capacity corresponding to the current data and the delayed data.

Assume that the extreme value detection circuit 6a compares, for example, the Ej-th current data and the Fj-th delayed data, and detects the extreme value P2 on line 20 in FIG. This current extreme value P2 is given to the subtractive absolute value calculation circuit 10m together with the Gj-th stored opening value P1 in the extreme value holding memory 17. When the absolute value of the difference W12 between the extreme value P2 and the opening value P1 is less than or equal to the change value preset in the change value setting circuit 12a, the opening value P1 of the Gj-th store cell is set.
is updated with the extreme value P2, and the extreme value P2 remains held. If the absolute value of the difference between the extreme value P2 and the current data from the analog/digital conversion circuit 4a is less than or equal to the threshold value M preset in the threshold setting circuit 14a, the line! A high level signal (non-defect detection signal) is derived from 14m.

Next, when the extreme value detection circuit 6a detects the current extreme value P3, the difference W23 between the current extreme value ψ3 and the opening value P2 from the extreme value holding memory 17 determines the change value of the change value setting circuit 12a. If it exceeds the current extreme value P3, the opening value P2 held in the Gj@th store cell of the extreme value holding memory 17 is not updated with the current extreme value P3, and the Ill extreme value P2 remains held.

At this time, the opening value P2 and the analog/dental conversion circuit 4a
When the difference between the current data and the current data exceeds the threshold value M, a low level (g (defect detection signal)) is derived from the line J 14 a.

Next, when the current extreme value P4 is detected in the extreme value detection circuit 6a, the difference W24 between the current extreme value P4 and the opening value P2 from the extreme value holding memory 17 is less than or equal to the change value of the change value setting circuit 12a. Then, the opening value P2 of the Gj-th store cell in the extreme value holding memory 17 is updated with the current extreme value P4. At this time, if the difference between the opening value P2 and the current data from the analog/digital conversion circuit 4a is equal to or less than the threshold value M, the line 1
A high level signal (non-defect detection signal) is derived from 14a and the like.

In this way, ll! of horizontal scanning lines! An extreme value holding memory 17 having the same number of store cells G1 to Gr as I elements,
In this extreme value holding memory 17, the extreme value of the level of each pixel that changes in the vertical scanning direction is updated sequentially, and a threshold value M is set based on the extreme value.
The vertical 70-ting binarization circuit 3 is configured to detect pixels whose level exceeds 100 kHz and derive a defect detection signal for detecting defects that vary in the vertical direction corresponding to r pixels in each vertical scanning line. It becomes possible to extract parts.

The detection signal derived from the line 14 of the horizontal 70-ting binary conversion circuit 2 and the detection signal derived from the line 14a of the vertical 70-ting binary conversion circuit 3 are individually input to each input terminal of the OR date 15. is input. In this way, by using the OR date 15 to take the logical product of changes in extreme values in both the horizontal and vertical directions, the two-dimensional 7
This makes it possible to easily configure the 0-ting binarization circuit.

Therefore, an accurate binary image can be obtained by two-dimensionally extracting the image signal from the image signal in real time.

Effects As described above, according to the present invention, for each scanning line provided with a plurality of pixels, the levels of mutually corresponding pixels are compared to find the extreme value, and the same number of pixels are determined for each scanning line. A memory having a store cell stores the extreme value in the store cell corresponding to the pixel for which the extreme value was found, and stores the previous extreme value in the store cell between the extreme values. By comparing the stored contents of the store cell with the stored contents of the store cell during pixel scanning and level-discriminating the difference, the binarization process is performed accurately and defective parts of the detected object are detected reliably. can do.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a line 20 representing each level of consecutive pixels in the vertical scanning direction.
FIG. 3 is a diagram related to the extreme value holding memory 17.

Claims (1)

[Claims] Each of a plurality of scanning lines is provided with a plurality of individually corresponding pixels, and the levels of mutually corresponding pixels of different scanning lines are compared to find an extreme value, and the A memory having the same number of store cells as pixels is provided, and the extreme value is stored in the store cell corresponding to the pixel for which the extreme value was found, and the immediately preceding extreme value is stored in the store cells between the extreme values. An image processing method characterized in that: the content of the stored cell is kept stored, the stored content of the stored cell is compared with the stored content of the stored cell during pixel scanning, and the difference is level-discriminated.