JPS63261477A - Video signal storage device - Google Patents

Abstract

PURPOSE:To efficiently store video signal data in a general-purpose storage device by storing video signal data in a video signal storage device for storing a TV signal as digital data every scanning line without generating an interval by using an address specifying means. CONSTITUTION:In case of reading out video signal data stored in a memory 100, scanning line numbers are successively counted every frame by a line counter 112, the output of the counter 112 is applied to an address converter 106 and the output of the converter 106 is inputted to an address counter 104. The counter 104 starts the counting of picture element clocks and applies a read- enable signal to the memory 100 and video signal data is read out from a storage position to a register 102. Said operation is repeated thereafter and the scanning line numbers are converted into real addresses in the memory 100 to store video signals in the general storage device without generating gaps.

Description

TECHNICAL FIELD The present invention relates to a storage device, and more particularly to a video signal storage device that stores video signals representing images, such as television signals, in the form of digital data.

BACKGROUND ART To store video signals, many storage devices, such as semiconductor memories, which are optimally applied to information processing devices, have been used. As is well known, such a storage device for information processing has a storage capacity of a power of 2, and is designed to be compatible with other elements of an information processing system.

However, in general, video signals for displaying one screen are not necessarily compatible with such a power-of-two system. For example, if we take a normal television signal, one screen is horizontally displayed as shown in Figure 3. For example, 480 horizontal scanning lines each having 76,868 pixels in the scanning direction are arranged in the vertical scanning direction to form an effective screen. Including the blanking period, one screen consists of 525 horizontal scanning lines of 910 pixels arranged in the vertical scanning direction.

When using video signal data, it is generally preferable to be able to access the data in units of horizontal scanning lines (lines).
However, if video signal data is to be stored in a normal storage device in an easily accessible format, it is required to store the data in units of, for example, 1024 bits in the horizontal scanning direction. If one pixel is represented by one byte of data, then
Eight such memory surfaces are required. If such a storage method is adopted, as shown in FIG. 3, the memory up to 1024 bits exceeding the screen area of 810 bits is not used effectively and is scattered as free space, resulting in a lot of waste.

FIG. 4 shows a conventional example including an addressing circuit for a storage device adopting such a data storage format.

As you will see, video signal data is stored in the power of 2 memory module 10 horizontally (as shown in FIG. 3).
The data is stored in memory locations of addresses in units of powers of 2 for each horizontal scanning line in the X) direction and the vertical (Y) direction.

Therefore, the memory module 10 has a blank space as shown in FIG. Access in the vertical (Y) direction is performed by the relay counter 12 which increments in response to the vertical synchronization signal VD or frame synchronization signal FD, and access in the horizontal (X) direction is incremented in response to the pixel clock. These operations are carried out independently by the H address counter 14.

It is not economical to develop a video memory that can store video signal data in an easily accessible format in units of scanning lines without wasting memory space.

Therefore, in order to eliminate this waste of memory space by using a general-purpose storage device, the data of each horizontal scanning line is stored without gaps in the memory space, and the joint between the horizontal scanning lines is a power of 2 memory module access. Applications of video signal data that do not necessarily correspond to units often require memory writing or reading in units of scan lines, so such data storage formats do not necessarily correspond to units.

For example, it cannot be effectively applied to limited applications such as reading data continuously.

Purpose: The present invention eliminates the drawbacks of the prior art and provides video signal storage in which a general-purpose storage device can be used efficiently and the video signal data can be easily accessed! The purpose is to provide stirrups.

and 11(7) I1 According to the present invention, there is provided a first storage means for storing a video signal representing an image by a scanning line including a plurality of pixels in the form of digital data, and an address of the first storage means is specified. In the video signal storage device, the addressing means has an address conversion means for converting the number of the scanning line into an address of a storage position of the first storage means. , video signal data is accumulated for each scanning line without any interval.

Embodiments of the video signal storage device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, the device includes a memory 100 that stores video signals representing images, such as television signals, in the form of digital data, and which memory 100, such as a semiconductor memory, is most suitable for the information processing system. Applicable. For example, it may be a general-purpose storage device, so its storage capacity is a power of two. The memory 100 has a storage capacity to store video signal data for one screen.

One screen represented by a video signal is, for example, as shown in FIG. 3, which shows an example of sampling of a television screen.
It is formed by 0 lines arranged. If you include the blanking period, one screen is.

It is composed of 525 horizontal scanning lines of 910 pixels arranged in the vertical scanning direction. In this embodiment, the pixel signal of one pixel is represented by 8 bits, that is, 1 byte of data. Therefore, in this device, the memory 100 has eight storage areas 100a to 100h as shown. Therefore, by specifying the address of a storage location in the memory 100, a total of 8 bits from each storage surface 100a to 100h are read out to the read register 102 all at once.

Read and write addresses for memory 100 are designated by address line 108 from address counter 104.

The address counter 104 is a 7-bit counter that receives the pixel clock of the video signal at the clock terminal CK and increments in response to this. Therefore, 512 of memory 100
address can be specified. The initial value of the count can be preset, and in this embodiment, the address translation circuit (ATT)
108 by a preset manual 110, and is preset in synchronization with the horizontal synchronization signal HD of the video signal.

The count value of the counter 104 is reset by the vertical synchronization signal VD or the frame synchronization signal FD. These synchronization signals and pixel clocks are provided, for example, from a synchronization signal generation circuit (not shown) at a television signal rate.

The address conversion circuit 10B takes the form of a table that converts horizontal scanning line numbers into real addresses in the memory 100, and this table is stored in, for example, a ROM. Rather than an RO, it may take the form of other logic elements, such as a programmable logic array.

More specifically, as shown in FIG. 2, the actual address of the memory 100 is stored at the storage location using the horizontal scanning line number, that is, the line number, as a ROM address. These real addresses are addresses of storage locations in the memory 100 where data of the head of the corresponding scanning line, that is, the leftmost pixel on the screen of the video signal is stored, and serve as the preset value of the address counter 104.

In this embodiment, for example, the effective horizontal scanning line consists of 768 pixels, the first pixel of horizontal scanning line 0 is at address 0 of the memory 100, and the first pixel of scanning line $1 is at address 76.
8, the first pixel of scanning line @2 is at address 8153B,
The preset values are stored in the address conversion circuit 10B as a table.

Therefore, as shown in FIG. 1, the memory 100 stores data of pixels subsequent to the scanning line in order from the first pixel.

The scanning line number given to the address conversion circuit 1013 is
The line number is input from the line counter 112 to the line number manual 114 . The line counter 112 is a 7-bit counter that receives a horizontal synchronizing signal at its clock terminal and increments in response to this signal. The count value of the counter 112 is reset by the vertical synchronization signal VD or the frame synchronization signal FD. These address counters 104. Memory 100 by address conversion circuit lO8 and line counter 112
Addressing circuit is configured.

In the video signal storage device of this embodiment configured in this way, as shown in FIG. Data of pixels subsequent to scanning line @0 is accumulated. The first pixel of the scanning line IIl is stored in the memory location M78B next to the memory location @767 where the data of the last pixel of the horizontal scanning line 0, that is, the rightmost pixel of the screen is stored. The data of the subsequent pixels of scanning line @1 are stored in order. Thereafter, in this way, until the final scan line, for example, the final pixel of 479@388839,
Video signal data is accumulated without gaps.

For example, when reading the video signal data stored in this way from the memory 100, the line counter 112 and address counter 104 are supplied with a pixel clock, a horizontal synchronization signal HD, and a vertical synchronization signal or frame synchronization signal as shown in FIG. The signal FD is provided, for example, at a television picture signal rate. Line counter 112 sequentially counts scanning line numbers for each l field or frame, and provides the counted value to address conversion circuit 106 from output 114.

The address conversion circuit 1013 reads out the memory contents using this line count value as an address, and converts the address counter 10
output to the preset input 110 of No. 4. Same counter 10
4, this preset value is set in synchronization with the horizontal synchronization signal HD, and the counter 104 starts counting pixel clocks using this as an initial value. Along with this, memory 10
A read enable signal is applied to 0, and video signal data is read to the read register 102 from the storage location of the address specified by the address counter 104.

Thereafter, as the address counter 104 increments in response to the pixel clock, the address of the subsequent storage location in the memory 100 is designated by the address counter 104, and data of a series of pixels of the scanning line is stored in the register 102 one after another.
is read out. When the video signal data is read out to the last pixel of the scanning line, the line counter 112 is incremented in synchronization with the next horizontal synchronizing signal HD, so that the number indicating the next scanning line is transferred to the address conversion circuit 1013.
is input. The subsequent operations are the same as described above.

For example, the line counter 112 counts the scanning line number 0, and outputs the counted value from the address conversion circuit 114.
Give to 06. The conversion circuit 106 reads out the stored content "0" of the address IQ corresponding to this line count value, and presets this into the address counter 104. The counter 104 uses this as an initial value and advances in synchronization with the pixel clock.
The video signal data is read out in order from the storage location of register 1.
02. Thereafter, as the address counter 104 progresses, pixel data is sequentially read into the register 102, one after another, up to the last pixel, such as the last pixel of that scan line cloud 0, or the last pixel of that field or frame. The same applies when reading out video signal data from a scanning line in the middle of one screen.

Note that the operation of the video signal storage device of this embodiment is described in memory 10.
The explanation has been given using the 0 read operation as an example.

It goes without saying that the write operation to the memory 100 is similar.

As described above, according to this embodiment, the address designation circuit of the memory 100 is provided with the address conversion circuit 108, and by converting the scanning line number into the real address of the memory 100 in the conversion circuit 108, the information processing system for,
That is, video signal data can be stored in a general-purpose storage device without gaps.

As described above, according to the present invention, by providing an address conversion circuit for indexing the real address of the memory where the video signal is stored from the number of the scanning line of the video signal in the address designation circuit of the memory, the video signal can be stored. Video signal data can be efficiently stored in, for example, a general-purpose storage device that has a standard different from that of the standard.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an embodiment of a video signal storage device according to the present invention; FIG. 2 is a diagram showing an example of the configuration of an address conversion table stored in the address conversion circuit of the embodiment shown in FIG. 1; FIG. 3 is a diagram showing an example of data obtained by sampling a video signal of a television screen. FIG. 4 is a functional block diagram showing an example of a video signal storage device according to the prior art. Explanation of symbols of main parts 100. ,,Memory 104, ,Address counter 108, ,Address conversion circuit 112, ,Line counter Patent applicant: Japan Broadcasting Association Fuji Photo Film Co., Ltd. Representative: Takao Katori Takao Maruyama

Claims (1)

[Scope of Claims] 1. A first storage means for storing a video signal representing an image by a scanning line including a plurality of pixels in the form of digital data; and an addressing means for specifying an address of the first storage means. In the video signal storage device, the addressing means has an address conversion means for converting the number of the scanning line into an address of a storage position of the first storage means, whereby the first storage means has the following: A video signal storage device characterized in that data of the video signal is accumulated for each scanning line without any interval. 2. The apparatus according to claim 1, wherein the addressing means includes first counting means for counting the number of the scanning lines in response to a horizontal synchronization signal of the video signal; and the address converting means. a second counting means for specifying an address of a storage location of the first storage means by incrementing the preset value in response to a pixel clock of the video signal; The address converting means receives the counted value of the first counting means and converts the counted value into an address of a storage position of the data of the first pixel of the scanning line in the first storing means. Device. 3. In the apparatus according to claim 1, the address converting means stores in the storage location an address of a storage location in which data of the first pixel of a scanning line in the first storage means is stored; A read-only second counter receives the counted value of the first counting means, uses the counted value as an address, reads out the address of the storage location of the first storage means from the corresponding storage location, and presets it in the second counting means. 1. A video signal storage device comprising storage means.