JPS61228782A - Image pickup device - Google Patents
Image pickup deviceInfo
- Publication number
- JPS61228782A JPS61228782A JP60070202A JP7020285A JPS61228782A JP S61228782 A JPS61228782 A JP S61228782A JP 60070202 A JP60070202 A JP 60070202A JP 7020285 A JP7020285 A JP 7020285A JP S61228782 A JPS61228782 A JP S61228782A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- correction
- output
- element sensor
- picture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は一次元または二次元の多素子センサを備えた撮
像装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device equipped with a one-dimensional or two-dimensional multi-element sensor.
第4図はこの種の撮像装置の従来例のブロック図である
。FIG. 4 is a block diagram of a conventional example of this type of imaging device.
この撮像装置は、多素子センサlと、この多素子センサ
lからの画像信号を増幅する増幅回路2と、増幅回路2
の出力をアナログ/デジタル変換するA/D変換器3と
、A/D変換された画像信号を記憶する記憶回路6と、
A/D変換器3からの画像信号を記憶回路6に記憶する
番地を発生するアドレス発生回路5と、多素子センサl
、A/D変換器53、アドレス発生回路5を駆動するタ
イミング発生回路4と、記憶回路6の画像信号を処理す
る画像処理回路7と、記憶回路6から出力されたデジタ
ル信号をアナログ信号に戻すD/A変換器9と、画像表
示装置lOと、記憶回路6の記憶場所を指示するアドレ
ス発生回路l!と、D/A変換器9、画像表示装置10
およびアドレス発生回路11を駆動するタイミング発生
回路12と、記憶回路6の画像信号の入力と出力の動作
により切換わる切換スイッチ8からなる。This imaging device includes a multi-element sensor l, an amplification circuit 2 that amplifies an image signal from the multi-element sensor l, and an amplification circuit 2.
an A/D converter 3 that converts the output from analog to digital; a storage circuit 6 that stores the A/D converted image signal;
An address generation circuit 5 that generates an address for storing an image signal from the A/D converter 3 in a storage circuit 6, and a multi-element sensor l.
, an A/D converter 53, a timing generation circuit 4 that drives the address generation circuit 5, an image processing circuit 7 that processes the image signal of the storage circuit 6, and a digital signal output from the storage circuit 6 that returns the digital signal to an analog signal. D/A converter 9, image display device lO, and address generation circuit l! for instructing the storage location of memory circuit 6! , D/A converter 9, and image display device 10
It also includes a timing generation circuit 12 that drives the address generation circuit 11, and a changeover switch 8 that is switched depending on the operation of inputting and outputting the image signal of the storage circuit 6.
この従来の撮像装置では、画素の数および画素の漕薄の
階調により異なるが記憶回路6は多くの記憶容量を必要
とする他、これを駆動する回路、これらと別系統の画像
処理回路が必要であり、また、画像を処理した状態で出
力するためには、画像を記憶回路6へ取込む時間、画像
処理回路7で画像を処理する時間、記憶回路6から画像
表示装置10へ出力する時間を要し、従ってリアルタイ
ムに画像を再生することが難しく、リアルタイムに画像
を再生しようとするとさらに多くの回路を必要とする欠
点があった。In this conventional imaging device, the memory circuit 6 requires a large storage capacity, although this differs depending on the number of pixels and the gradation of pixel depth. In addition, in order to output the image in a processed state, it takes time to take the image into the storage circuit 6, time to process the image in the image processing circuit 7, and output from the storage circuit 6 to the image display device 10. It takes time, and therefore it is difficult to reproduce images in real time, and there is a drawback that more circuits are required when attempting to reproduce images in real time.
本発明はこれらの欠点を除去するため、事前に補正を行
う箇所を記憶回路に保持し、その後撮像される信号に対
して即時に補正を行うものである。In order to eliminate these drawbacks, the present invention stores locations to be corrected in advance in a storage circuit, and then immediately performs correction on signals that are imaged.
すなわち、本発明の撮像装置は、補正箇所記憶回路と、
撮像前に多素子センサの補正を行なうべき箇所を検出し
、これを補正箇所記憶手段の対応する位置に記憶する手
段と、撮像時に補正箇所記憶回路の内容により撮像する
画素に対し即時に補正を行う手段とを有することを特徴
とする。That is, the imaging device of the present invention includes a correction point storage circuit;
A means for detecting a point to be corrected in a multi-element sensor before taking an image and storing it in a corresponding position of a correction point storage means, and a means for immediately correcting a pixel to be imaged according to the contents of a correction point storage circuit at the time of taking an image. It is characterized by having a means for performing.
本発明の実施例について図面を参照して説明する。 Embodiments of the present invention will be described with reference to the drawings.
第1図は本発明による撮像装置の一実施例のブロック図
である。FIG. 1 is a block diagram of an embodiment of an imaging device according to the present invention.
本実施例の画像処理装置は、多素子センサ1と、増幅回
路2と、多素子センサ1の補正箇所を検出する出力電圧
比較回路14と、出力電圧比較回路14で検出された多
素子センサ1の補正箇所(キズの画素)を記憶する補正
箇所記憶回路15と、撮像時に画素の出力電圧を保持し
、補正箇所記憶回路15にON” (補正箇所を示す
)が記憶されている画素に対してはその前の画素の出力
電圧を出力するサンプル・ホールド回路16と、撮像前
の補正箇所取得モードでは出力電圧比較回路14に、撮
像時(撮像モード)にはサンプル・ホールド回路1Bに
出力が切換えられる切換スイッチ13と、補正箇所記憶
回路15のアドレスを発生するアドレス発生回路18と
、画像表示装置lOと、多素子センサ1、アドレス発生
回路18、画像表示装置10に同期をかけて駆動するタ
イミング発生回路17とを備えている。The image processing device of this embodiment includes a multi-element sensor 1, an amplifier circuit 2, an output voltage comparison circuit 14 for detecting correction points of the multi-element sensor 1, and a multi-element sensor 1 detected by the output voltage comparison circuit 14. A correction point memory circuit 15 stores correction points (flawed pixels), and a correction point memory circuit 15 stores the pixel output voltage during image capture, and a correction point memory circuit 15 stores pixel output voltages for which "ON" (indicating a correction point) is stored. output voltage is output to a sample-and-hold circuit 16 that outputs the output voltage of the previous pixel, an output voltage comparator circuit 14 in the correction point acquisition mode before imaging, and an output to the sample-and-hold circuit 1B during imaging (imaging mode). The changeover switch 13 to be changed, the address generation circuit 18 that generates the address of the correction point storage circuit 15, the image display device 10, the multi-element sensor 1, the address generation circuit 18, and the image display device 10 are driven in synchronization. The timing generating circuit 17 is also provided with a timing generating circuit 17.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
まず、切換スイッチ13を出力電圧比較回路14に接続
し、多素子センサ1の画素の補正箇所を補正箇所記憶回
路15へ記憶する。例えば、多素子センサlへ入射光が
無いにも拘わらず、出力電圧が現われるような画素のあ
る場所は出力電圧比較回路14において比較結果がON
”となり補正箇所記憶回路15へその情報が記憶される
。多素子センサ1が正常動作を行っている場合は出力電
圧比較回路14の比較結果は”OFF’”として同じく
補正箇所記憶回路15へその番地が記憶される。ここま
でが、補正箇所取得モードである。First, the changeover switch 13 is connected to the output voltage comparison circuit 14, and the correction points of the pixels of the multi-element sensor 1 are stored in the correction point storage circuit 15. For example, at a location where there is a pixel where an output voltage appears even though there is no light incident on the multi-element sensor l, the comparison result is ON in the output voltage comparison circuit 14.
”, and the information is stored in the correction point storage circuit 15. If the multi-element sensor 1 is operating normally, the comparison result of the output voltage comparison circuit 14 is set as “OFF” and the information is also stored in the correction point storage circuit 15. The address is memorized.The steps up to this point are the correction point acquisition mode.
次に、切換スイッチ13をサンプル・ホールド回路16
側へ接続し、タイミング発生回路17からの駆動信号に
従って増幅回路2と切換スイッチ13を経てサンプル・
ホールド回路16へ画像信号が入力される。タイミング
発生回路17からの駆動信号はこれに同期して補正箇所
記憶回路15も動作させ、補正箇所取得モードにおける
情報を再生し、”ON”である番地ではサンプル・ホー
ルド回路16の出力が保持され、前の番地と同じ出力に
なるように画像表示装置10へ出力される。Next, the changeover switch 13 is connected to the sample/hold circuit 16.
The sample signal is connected to the side, and the sample signal is output via the amplifier circuit 2 and the changeover switch 13 according to the drive signal from the timing generation circuit 17.
An image signal is input to the hold circuit 16. The drive signal from the timing generation circuit 17 also operates the correction point storage circuit 15 in synchronization with this to reproduce information in the correction point acquisition mode, and the output of the sample/hold circuit 16 is held at an address that is "ON". , are output to the image display device 10 so as to have the same output as the previous address.
なお、補正は必ずしも前の番地と同じ出力でなくてもよ
く、さらに1つ前の番地と同じ出力、あるいは前の番地
の出力を補間した値でもよい。Note that the correction does not necessarily have to be the same output as the previous address, but may also be the same output as the previous address or a value obtained by interpolating the output of the previous address.
第2図は、多素子センサ1の撮像画面の例をマトリック
スに示した図、第3図はこの撮像画面に対応する補正箇
所記憶回路15の内容を示す図である。FIG. 2 is a diagram showing an example of an imaging screen of the multi-element sensor 1 in a matrix, and FIG. 3 is a diagram showing the contents of the correction point storage circuit 15 corresponding to this imaging screen.
第2図に示した多素子センサlの補正が必要な画素(X
印テ示すEt3. C32、C44、−ハ”ON”と
して、補正の必要がない画素CII + CI2 +
・・・は”OFF”として第3図に示すように補正箇所
記憶回路15に記憶される。次に撮像モードにおいてサ
ンプル・ホールド回路1Bは画素CII + CI2
+・・・において“OFF ” 、画素CI3 *
C32+ C44+・・・で′“ON″となるよう
に動作をするため、画素C12での出力電圧が保持され
、画素CI2と(1”13は同じ出力となる。The pixel (X
Et3. C32, C44, -C Pixels CII + CI2 + that do not require correction as "ON"
... are stored as "OFF" in the correction point storage circuit 15 as shown in FIG. Next, in the imaging mode, the sample/hold circuit 1B selects pixels CII + CI2.
“OFF” at +..., pixel CI3 *
Since it operates so that C32+C44+, .
このように、多素子センサlの補正すべき番地を事前に
記憶することにより、撮像された画像の補正すべき各画
素を瞬時に割り出し、補正を行うことが可能である。ま
た、多素子センサ1は特定の多素子センサである必要は
なく、撮像する前に補正すべき番地を記憶すれば、任意
の多素子センサが使用できる。In this way, by storing in advance the address of the multi-element sensor l to be corrected, it is possible to instantly determine each pixel of the captured image to be corrected and perform the correction. Furthermore, the multi-element sensor 1 does not need to be a specific multi-element sensor, and any multi-element sensor can be used as long as the address to be corrected is memorized before imaging.
以上説明したように本発明は、多素子センサの補正を必
要とする箇所を事前に記憶することにより、撮像しなが
ら補正を即時に行え、また、−次元または二次元、また
画素数に左右されず、補正する番地の記憶される容量を
充分に確保することにより、任意の多素子センサに応用
でき、さらにこの装置は容易にしかも安価に製作できる
利点もある。As explained above, the present invention stores in advance the points that require correction in a multi-element sensor, so that correction can be performed immediately while capturing an image, and it is also possible to perform corrections in -dimensional or two-dimensional, and depending on the number of pixels. First, by ensuring a sufficient capacity for storing the address to be corrected, the present invention can be applied to any multi-element sensor, and this device also has the advantage of being easy and inexpensive to manufacture.
第1図は本発明による撮像装置の一実施例のブロック図
、第2図は多素子センサlの撮像画面の例をマトリック
スに示した図、第3図はこの撮像画面に対応する補正箇
所記憶回路15の内容を示す図、第4図は撮像装置の従
来例のブロック図である。
l:多素子センサ、 2:増幅回路、
10:画像表示装置、 13:切換スイッチ、14:出
力電圧比較回路、
15:補正箇所記憶回路、
18:サンプル・ホールド回路、
17:タイミング発生回路、
18ニアドレス発生回路。Fig. 1 is a block diagram of an embodiment of an imaging device according to the present invention, Fig. 2 is a matrix diagram showing an example of an imaging screen of a multi-element sensor l, and Fig. 3 is a memory of correction points corresponding to this imaging screen. FIG. 4, which is a diagram showing the contents of the circuit 15, is a block diagram of a conventional example of an imaging device. l: multi-element sensor, 2: amplifier circuit, 10: image display device, 13: changeover switch, 14: output voltage comparison circuit, 15: correction point storage circuit, 18: sample/hold circuit, 17: timing generation circuit, 18 Near address generation circuit.
Claims (1)
で撮像を行なう撮像装置において、補正箇所記憶回路と
、撮像前に前記多素子センサの補正を行なうべき箇所を
検出し、これを前記補正箇所記憶回路の対応する位置に
記憶する手段と、撮像時に前記補正箇所記憶回路の内容
により撮像する画素に対し即時に補正を行う手段とを有
することを特徴とする撮像装置。In an imaging device that is equipped with a one-dimensional or two-dimensional multi-element sensor and performs imaging using an electronic scanning method, a correction point storage circuit detects a point to be corrected in the multi-element sensor before image capturing, and performs the correction. An imaging device comprising: means for storing data in a corresponding position of a location storage circuit; and means for immediately correcting pixels to be imaged based on the contents of the correction location storage circuit during imaging.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60070202A JPS61228782A (en) | 1985-04-03 | 1985-04-03 | Image pickup device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60070202A JPS61228782A (en) | 1985-04-03 | 1985-04-03 | Image pickup device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61228782A true JPS61228782A (en) | 1986-10-11 |
Family
ID=13424696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60070202A Pending JPS61228782A (en) | 1985-04-03 | 1985-04-03 | Image pickup device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61228782A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03227185A (en) * | 1990-01-31 | 1991-10-08 | Sony Corp | Picture defect correction device for solid-state image pickup element |
JPH03296375A (en) * | 1990-04-13 | 1991-12-27 | Sony Corp | Blemish correcting circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5644274A (en) * | 1979-09-20 | 1981-04-23 | Matsushita Electric Ind Co Ltd | Defect compensating unit of solid image pickup element |
JPS5754481A (en) * | 1980-09-18 | 1982-03-31 | Matsushita Electric Ind Co Ltd | Deficiency correction circuit |
JPS5868378A (en) * | 1981-10-19 | 1983-04-23 | Matsushita Electric Ind Co Ltd | Defect compensation system for solid-state image pickup element |
-
1985
- 1985-04-03 JP JP60070202A patent/JPS61228782A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5644274A (en) * | 1979-09-20 | 1981-04-23 | Matsushita Electric Ind Co Ltd | Defect compensating unit of solid image pickup element |
JPS5754481A (en) * | 1980-09-18 | 1982-03-31 | Matsushita Electric Ind Co Ltd | Deficiency correction circuit |
JPS5868378A (en) * | 1981-10-19 | 1983-04-23 | Matsushita Electric Ind Co Ltd | Defect compensation system for solid-state image pickup element |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03227185A (en) * | 1990-01-31 | 1991-10-08 | Sony Corp | Picture defect correction device for solid-state image pickup element |
JPH03296375A (en) * | 1990-04-13 | 1991-12-27 | Sony Corp | Blemish correcting circuit |
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