JPS5868340A - Fading generator - Google Patents

Fading generator

Info

Publication number
JPS5868340A
JPS5868340A JP56165658A JP16565881A JPS5868340A JP S5868340 A JPS5868340 A JP S5868340A JP 56165658 A JP56165658 A JP 56165658A JP 16565881 A JP16565881 A JP 16565881A JP S5868340 A JPS5868340 A JP S5868340A
Authority
JP
Japan
Prior art keywords
fading
delay
path
equalizer
paths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56165658A
Other languages
Japanese (ja)
Other versions
JPS6328373B2 (en
Inventor
Shoji Watanabe
渡辺 昇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56165658A priority Critical patent/JPS5868340A/en
Publication of JPS5868340A publication Critical patent/JPS5868340A/en
Publication of JPS6328373B2 publication Critical patent/JPS6328373B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B17/00Monitoring; Testing
    • H04B17/30Monitoring; Testing of propagation channels
    • H04B17/391Modelling the propagation channel
    • H04B17/3911Fading models or fading generators

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Radio Transmission System (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To estimate the amount of delay distortion in a fading generation period, to improve symmetry, and to evaluate equivalent characteristics accurately, by providing a delay equalizer to one of two paths for distributing an input signal. CONSTITUTION:An input signal from an input terminal 1 is distributed into two by a distributor 2 to the path composed of a delay line 3 and the path of a variable phase shifter 4, a variable attenuator 5, a delay equalizer 9, and a delay line 6; and the outputs of both the paths are synthesized by a synthesizer 7, whose output is outputted from an output terminal 8. This delay equalizer 9 is provided on the output side of the variable attenuator 5 to equalize delay distortion generated on a reflecting path, and the attenuation amount of frequency characteristics is made symmetrical on a prescribed frequency, thus evaluating equivalent characteristics accurately.

Description

【発明の詳細な説明】 本発明は2波干渉モデルにもとづくフェージング特性を
発生させるフェージング発生器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fading generator that generates fading characteristics based on a two-wave interference model.

フェージング発生器は2例えば無線伝送で生ずる選択性
フェージングを等化するだめのフェージング等化器の評
価を行なう場合、あるいは伝送路自体の選択性フェージ
ングに対する評価を行なう場合等に使用されるものであ
って、入力信号を2分して2つの径路に分け、1方の径
路で可変移相器を用いて適当な量の移相を与えたあと、
2径路を合成して所望のフェージング特性を得るように
したものである。
A fading generator is used, for example, when evaluating a fading equalizer for equalizing selective fading that occurs in wireless transmission, or when evaluating selective fading of the transmission path itself. Then, after dividing the input signal into two paths and applying an appropriate amount of phase shift using a variable phase shifter on one path,
Two paths are combined to obtain desired fading characteristics.

ところで上記のようなフェージング発生器を実現する場
合、理想的なフェージングモデルを充分擬似できること
が要求されるが、従来のフェージング発生器においては
この要件は必ずしも満たされていなかった。すなわち、
フェージング特性のディップを広帯域且つ連続的に出現
しようとすると2発生したフェージング特性がディップ
周波数を中心として前後に非対称となり、フェージング
のモデルと一致しなくなる欠点があったのである。
By the way, when realizing the above fading generator, it is required to be able to sufficiently simulate an ideal fading model, but this requirement has not always been met in conventional fading generators. That is,
If an attempt was made to make the dip in the fading characteristic appear continuously over a wide band, the resulting fading characteristic would become asymmetrical around the dip frequency and would not match the fading model.

したがって本発明の目的は、フェノングディッゾの周波
数に対して対称性が良好で2波干渉によるフェージング
モデルと一致するフェージング発生器を提供することに
ある。
Therefore, an object of the present invention is to provide a fading generator that has good symmetry with respect to the Fenong Dizzo frequency and matches the fading model based on two-wave interference.

本発明によるフェージング発生器は、前述のフェージン
グ特性のディップ周波数を中心として前後に非対称にな
る原因が、主として一方の径路に配置する可変移相器が
一般的に狭帯域であって遅延歪を発生することにあると
考えられるところから、この遅延歪を発生する径路にそ
の遅延歪を等化する遅延等化器を設けたことを特徴とす
るものである。
In the fading generator according to the present invention, the cause of the aforementioned asymmetry in the fading characteristics back and forth around the dip frequency is that the variable phase shifter disposed on one path is generally narrow-band, which causes delay distortion. Because it is believed that this is the case, the present invention is characterized in that a delay equalizer for equalizing the delay distortion is provided in the path that generates this delay distortion.

以下9図面を参照してより詳しく説明する。A more detailed explanation will be given below with reference to nine drawings.

第1図は従来のフェージング発生器の構成図である。図
において入力端子1からの入力信号は分配器2により2
分され、遅延線路3からなる径路(以後直接径路と称す
る。)と、可変移相器4゜可変減衰器5及び遅延線路6
よりなる径路(以後反射径路と称する。)とに分かれる
。この直接径路と反射径路を合成器7により合成するこ
とにより、2波干渉モデルにもとづく選択性フェージン
グ特性を得て出力端子8よ多出力している。そして所望
のフェージング特性を得るために、可変移相器4の移相
量、可変減衰器5の減衰量及び遅延線路の電気長の調整
がなされている。
FIG. 1 is a block diagram of a conventional fading generator. In the figure, the input signal from input terminal 1 is passed through divider 2 to 2
a path consisting of a delay line 3 (hereinafter referred to as a direct path), a variable phase shifter 4, a variable attenuator 5, and a delay line 6.
(hereinafter referred to as the reflection path). By combining the direct path and the reflected path by the combiner 7, a selective fading characteristic based on a two-wave interference model is obtained, and multiple outputs are outputted from the output terminal 8. In order to obtain desired fading characteristics, the phase shift amount of the variable phase shifter 4, the attenuation amount of the variable attenuator 5, and the electrical length of the delay line are adjusted.

上記の第1図の構成のフェージング発生器においては、
先に簡単に説明したが、フェー・ソング特性のディツノ
が広帯域かつ連続的に出現できるよう実現した場合、直
接径路および反射径路の振幅特性が各々平坦でもあるに
もかかわらず2発生したフェージング特性がディツノ周
波数を中心として前後で非対称となり、フェージングの
モデルと一致しなくなり、理想的なフェージングの評価
に即さないという欠点が生じたのである。そこではじめ
に選択性フェージング発生の原理を説明した上で、上記
の欠点の原因となっている主として可変移相器の発す2
遅延歪によるフェージング特性の非対称との関連につい
て説明する。なお上記のフェージング特性の具体的な一
例は、あとに説明するf本発明により得られるフェージ
ング特性と並べて図示しである。
In the fading generator configured as shown in FIG. 1 above,
As I briefly explained earlier, if the fading characteristics of the Fa-Song characteristic are realized in a wide band and continuous manner, the fading characteristics that occur even though the amplitude characteristics of the direct path and the reflected path are both flat. The problem was that it became asymmetrical around the Ditsuno frequency, which caused it to no longer match the fading model, making it incompatible with ideal fading evaluations. First, I will explain the principle of selective fading, and then explain that the two factors that cause the above drawbacks are mainly the
The relationship with the asymmetry of fading characteristics due to delay distortion will be explained. Note that a specific example of the above-mentioned fading characteristics is illustrated along with the fading characteristics obtained by the present invention, which will be explained later.

第2図は2波干渉による選択性フェージング発生の原理
を示す図である。フェージングは直接波(A−B)と0
点によって反射された反射波(A〜C−B)との合成に
より発生し、その振幅特性X←)は、直接波の振幅を1
とすると。
FIG. 2 is a diagram showing the principle of selective fading caused by two-wave interference. Fading is a direct wave (A-B) and 0
It is generated by combining with the reflected waves (A to C-B) reflected by the point, and its amplitude characteristic X←) is the amplitude of the direct wave by 1
If so.

X(P)=[:1+r2+2rom(Δτω十θ)〕2
−〔1+r2+2r部(Δτ(ω−ω0)+π)〕2・
・・(1)で表される。ここにrは反射波の振幅、Δτ
は直接波と反射波の到達時間差、θは直接波と反射波の
位相差、ω0はディ、プの生ずる角周波数をそれぞれ表
している。
X(P)=[:1+r2+2rom(Δτω+θ)]2
−[1+r2+2r part (Δτ(ω-ω0)+π)]2・
...Represented by (1). Here r is the amplitude of the reflected wave, Δτ
represents the arrival time difference between the direct wave and the reflected wave, θ represents the phase difference between the direct wave and the reflected wave, and ω0 represents the angular frequency at which the dip occurs, respectively.

(1)式はディツノの角周波数ω0に関して偶関数であ
るから、振幅特性はωGに対してその前後で対称である
。ところで第1図の構成に含まれる可変移相器4は一般
にインダクタンスLと容量Cで構成されており、広帯域
でみると必ず遅延歪が発生する。結果として従来のフェ
ージング発生器では、(1)式のΔτがωの高次関数と
なり、それが奇数次の場合はX←)のω0に関する偶対
称がくずれてソング特性が(1)式のモデルと一致しな
くなる〇第3図は上記欠点を除去した本発明によるフェ
ージング発生器の一実施例を示す構成図である。
Since equation (1) is an even function with respect to Ditsuno's angular frequency ω0, the amplitude characteristics are symmetrical with respect to ωG. By the way, the variable phase shifter 4 included in the configuration of FIG. 1 is generally composed of an inductance L and a capacitance C, and when viewed over a wide band, delay distortion always occurs. As a result, in conventional fading generators, Δτ in equation (1) becomes a higher order function of ω, and if it is an odd order, the even symmetry with respect to ω0 of Fig. 3 is a block diagram showing an embodiment of a fading generator according to the present invention that eliminates the above-mentioned drawbacks.

図において2反射径路にはこの径路で発生する遅延歪(
主として可変移相器により発生する。)を等化する遅延
等化器9が設けられており、他の第1図と同符号の回路
は第1図と同じである。
In the figure, the two reflection paths include the delay distortion (
Mainly generated by the variable phase shifter. ) is provided, and other circuits with the same symbols as in FIG. 1 are the same as in FIG.

ここで遅延等化器9の効果を明らかにするために2反射
径路で発生する遅延歪について考える。
Here, in order to clarify the effect of the delay equalizer 9, let us consider the delay distortion generated in the two reflection paths.

このときの遅延特性τ←)を次式で表わしたとする。Suppose that the delay characteristic τ←) at this time is expressed by the following equation.

一方直接径路では遅延歪が無いとすると、即ち直接径路
の遅延時間τ←)が周波数に関係なく一定とすると2反
射径路が(2)式の遅延特性を有するときのフェージン
グの振幅特性は次式となる。
On the other hand, assuming that there is no delay distortion in the direct path, that is, the delay time τ←) of the direct path is constant regardless of the frequency, the amplitude characteristic of fading when the two reflection paths have the delay characteristic of equation (2) is as follows. becomes.

X←)= (1+r2+2−Δτ(ω−056)+π9
(ω−ωo)2+?(ω−ωo)’+−))”・・・(
3) 次に、第3図のように(2)式と逆特性、即ちQl19
2の符号が(2)式と逆となるような遅延等化器を挿入
した場合を考える。この場合はτ←)=constとな
り、フェージング特性は(1)式に帰着し、理想的なフ
エージング特性が得られる。以上が本発明によるフェー
ジング発生器の原理である。
X←)= (1+r2+2-Δτ(ω-056)+π9
(ω-ωo)2+? (ω-ωo)'+-))"...(
3) Next, as shown in Figure 3, the inverse characteristic of equation (2), that is, Ql19
Consider the case where a delay equalizer is inserted such that the sign of 2 is opposite to that of equation (2). In this case, τ←)=const, the fading characteristic is reduced to equation (1), and an ideal fading characteristic is obtained. The above is the principle of the fading generator according to the present invention.

第4図は第3図の本発明によるフェージング発生器の振
幅特性を、フェージングディッゾ周波数f6− 丁−1
40MHz 、 r=0.97 eΔT = 1.67
 n5ecのときの一例と、先に第1図で説明した従来
のフェージング発生器の振幅特性の一例を併せ示した図
である。図において、破p、Intoは従来のフェージ
ング発生器の特性例で1反射径路に1nsec/40M
1(zの1次の遅延歪が生じている場合を示している。
FIG. 4 shows the amplitude characteristics of the fading generator according to the present invention shown in FIG.
40MHz, r=0.97 eΔT=1.67
2 is a diagram illustrating an example of the amplitude characteristic of the n5ec and an example of the amplitude characteristic of the conventional fading generator previously explained in FIG. 1. FIG. In the figure, failure p, Into is an example of the characteristics of a conventional fading generator, which is 1 nsec/40M per reflection path.
1 (indicates a case where first-order delay distortion of z occurs).

これに対し実線11が本発明によるフェージング発生器
の特性例で、遅延等化器により 1nsee/40MH
zの1次の遅延歪を等化するようにした場合である。こ
の図から分るように、従来のフェージング3生器では1
40 MHz±25 MHz離れた点における非対称性
が約1.5 dBであったのに対して。
On the other hand, the solid line 11 is an example of the characteristics of the fading generator according to the present invention, and the delay equalizer produces 1nsee/40MH.
This is a case where the first-order delay distortion of z is equalized. As can be seen from this figure, in the conventional fading 3 generator, 1
Whereas the asymmetry at points 40 MHz ± 25 MHz apart was approximately 1.5 dB.

本発明によるフェージング発生器では非対称が生じてい
ない。なお具体例で示した反射径路の1次の遅延歪1 
n5ec/40MHzの数値は−140MHz帯で可変
移相器を実現した場合、ごくふつうに発生する量である
No asymmetry occurs in the fading generator according to the invention. In addition, the first-order delay distortion 1 of the reflection path shown in the specific example
The value n5ec/40MHz is an amount that occurs quite commonly when a variable phase shifter is implemented in the -140MHz band.

以上説明したように1本発明によれば対称性の良好なフ
ェージング等化器が提供できるので、フェージング等化
器の等化特性の評価等に際してより正確な評価が可能と
なる。また、遅延等(L器として連続可変形のものを使
用して、実際に起きたフェージングの形を本発明による
フェージング発生器により実現すれば、フェージング発
生区間における遅延歪の量を推定することもできる。
As explained above, according to the present invention, it is possible to provide a fading equalizer with good symmetry, and therefore, it is possible to more accurately evaluate the equalization characteristics of the fading equalizer. In addition, if a continuously variable type L generator is used as the delay etc., and the fading shape that actually occurs is realized by the fading generator according to the present invention, it is possible to estimate the amount of delay distortion in the fading interval. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフェージング発生器の構成図。 第2図はフェージング発生の原理図、第3図は本発明の
一実施例の構成図、第4図は従来のフェージング発生器
と本発明によるフェージング発生器の特性を比較して示
した図であるO 記号の説明=1は入力端子、2は分配器、3は遅延線路
、4は可変移相器、5は可変減衰器、6は遅延線路、7
は合成器、8は出力端子、9は遅延等化器をそれぞれあ
られしている。
FIG. 1 is a block diagram of a conventional fading generator. Fig. 2 is a diagram showing the principle of fading generation, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a diagram comparing the characteristics of a conventional fading generator and a fading generator according to the present invention. A certain O Symbol explanation = 1 is an input terminal, 2 is a distributor, 3 is a delay line, 4 is a variable phase shifter, 5 is a variable attenuator, 6 is a delay line, 7
8 is a synthesizer, 8 is an output terminal, and 9 is a delay equalizer.

Claims (1)

【特許請求の範囲】[Claims] 1)2波干渉モデルに基づいて構成され、入力信号を一
方に可変移相器を含む2つの径路に分配したあと合成し
てフェージングを生じるようにしたフェージング発生器
において、前記一方の径路に遅延等化器を設けて成るこ
とを特徴とするフェージング発生器。
1) In a fading generator configured based on a two-wave interference model, in which an input signal is distributed to two paths, one of which includes a variable phase shifter, and then combined to cause fading, a delay is added to one of the paths. A fading generator comprising an equalizer.
JP56165658A 1981-10-19 1981-10-19 Fading generator Granted JPS5868340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56165658A JPS5868340A (en) 1981-10-19 1981-10-19 Fading generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56165658A JPS5868340A (en) 1981-10-19 1981-10-19 Fading generator

Publications (2)

Publication Number Publication Date
JPS5868340A true JPS5868340A (en) 1983-04-23
JPS6328373B2 JPS6328373B2 (en) 1988-06-08

Family

ID=15816542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56165658A Granted JPS5868340A (en) 1981-10-19 1981-10-19 Fading generator

Country Status (1)

Country Link
JP (1) JPS5868340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245326A (en) * 1984-05-21 1985-12-05 Hitachi Ltd Pseudo transmission delay signal generating circuit of communication testing device
US4679248A (en) * 1984-04-04 1987-07-07 British Telecommunications Public Limited Company Test equipment for simulating multipath interference

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5714228A (en) * 1980-06-30 1982-01-25 Fujitsu Ltd Simulator for phasing state

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5714228A (en) * 1980-06-30 1982-01-25 Fujitsu Ltd Simulator for phasing state

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679248A (en) * 1984-04-04 1987-07-07 British Telecommunications Public Limited Company Test equipment for simulating multipath interference
EP0304625A2 (en) * 1984-04-04 1989-03-01 BRITISH TELECOMMUNICATIONS public limited company Test equipment for simulating multipath interference
JPS60245326A (en) * 1984-05-21 1985-12-05 Hitachi Ltd Pseudo transmission delay signal generating circuit of communication testing device

Also Published As

Publication number Publication date
JPS6328373B2 (en) 1988-06-08

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