JPH0446317Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a chorus sound field generator suitable for use in, for example, karaoke, etc., and in particular, stereo transmits a chorus signal obtained by converting the pitch of the original sound such as a user's singing, and an original sound signal, This allows a chorus effect to be obtained spatially as well.

Hereinafter, an embodiment of the chorus sound field generating device of the present invention will be described with reference to FIG.

In FIG. 1, reference numeral 1 denotes a microphone. This microphone 1 converts the user's singing voice into an original sound signal, and converts the user's singing voice into an original sound signal. The signal is supplied to a conversion circuit (hereinafter referred to as a bass reduction circuit) 4 and a delay line 5. 6 is a fixed oscillator, 7 and 8 are variable frequency oscillators, and among these,
The output of the fixed oscillator 6 is supplied to the treble enhancement circuit 3, the bass reduction circuit 4, and the delay line 5, respectively, and the output of one variable oscillator 7 is supplied to the treble enhancement circuit 3, and the output of the other variable oscillator 8 is supplied to the bass reduction circuit. 4 respectively. Reference numeral 9 denotes a frequency divider, which divides the frequency of the output of the fixed oscillator 6 and supplies switching pulses of positive phase and negative phase to the treble-enhancing circuit 3.

The treble-enhancing circuit 3 basically consists of two sets of circuits connected in parallel. In the first set of the treble-enhancing circuit 3, 10 and 11 each indicate a shift register (hereinafter referred to as SR) using, for example, a bucket brigade device, and the original sound signal from the amplifier 2 is transferred to these SRs 10 and 11. Supply each. Reference numeral 12 indicates a control circuit, and this control circuit 12 alternately supplies the outputs of the fixed oscillator 6 and one of the variable oscillators 7 to the SRs 10 and 11.
13 indicates an electronic changeover switch, and this switch 1
3 is an SR 10 which is in a read state after receiving the drive pulse of the flip-flop 14 together with the control circuit 12.
Alternatively, the output of 11 is supplied to the multiplier 15.

The second set from the SRs 16 and 17 to the multiplier 21 has exactly the same configuration as the first set described above, so a description thereof will be omitted.

Both flip-flops 14 and 20 and both multipliers 15 and 21 receive positive-phase and anti-phase switching pulses from frequency divider 9 as described above, and both multipliers 15 and 21 send their outputs to adder 22. supply

In the bass reduction circuit 4, 23 and 24 indicate the same SR as the above-mentioned SR10 and 11, respectively,
The original sound signal from the amplifier 2 is supplied to these SRs 23 and 24. Reference numeral 25 indicates a control circuit, and this control circuit 25 alternately supplies the output of the fixed oscillator 6 and the output of the other variable oscillator 8 to the SRs 23 and 24. The outputs of these SRs 23 and 24 are supplied to electronic changeover switches 26, respectively. Note that the control circuit 25 and switch 26 are supplied with the outputs of the flip-flop 20, respectively.

Reference numerals 27, 28, and 29 each indicate variable attenuators, in which the output of the adder 22 of the treble-enhancing circuit 3 is supplied to the adder 30 via the variable attenuator 27, and the output of the switch 26 of the bass-enhancing circuit 4 is variable attenuated. The output of the delay line 5 is supplied via a variable attenuator 29 to both adders 30 and 31, respectively. 32L and 32R indicate left and right amplifiers of a two-channel stereo system, respectively, and the adder 3 is connected to the adder 3 via these amplifiers 32L and 32R.
The outputs of 0 and 31 are sent to the left and right speakers 33, respectively.
Supplied to L and 33R.

A time chart of this example is shown in FIG. In this Figure 2, t ₀ , t ₁ ... t ₈ are times at every 1/2 frame period (T/2), and Figure 2 A, B, C, and D are write times of SR10, 11, 16, and 17, respectively. and read timing.

The first and second sets of the treble-enhancing circuits 3 perform writing and reading with a difference of T/2, respectively. The frequency divider circuit 9 divides the write clock _W to generate positive-phase and negative-phase switching pulses as shown in FIG. 2E and F, respectively.
and is supplied to the multiplier 21. Both flip-flops 14 and 20 divide these switching pulses by 1/2,
Drive pulses shifted by T/2 as shown in FIG. 2G and H are generated to drive the control circuit 12 and electronic switch 13, and the control circuit 18 and electronic switch 19, respectively.

On the other hand, the fixed oscillator 6 outputs the write clock _W ,
One variable oscillator 7 has a readout clock _RH (>
_W ) are supplied to both control circuits 12 and 18, respectively, and these control circuits 12 and 18 supply a write clock _W and a read clock _RH to the two sets of SRs 10 and 11 and 16 and 17 by the above-mentioned drive pulses. As shown in FIG. 2G and H, the supply is alternately switched.

Therefore, SR10 starts writing at time t ₀ ,
SR16 starts writing at time t ₁ with a delay of T/2,
Further delayed by T/2, at time t ₂ , SR10 starts reading, and SR11 starts writing, and time
At t ₃ , SR16 starts reading and SR17
starts writing, at time t ₄ SR10 starts writing and SR11 starts reading, at time t ₅ SR17 starts reading and SR1
6 starts writing, and the same operation is repeated from time t ₆ onwards. In FIG. 2, W represents writing and R represents reading. A switch 13 switches the readout outputs of SRs 10 and 11, and a multiplier 15 multiplies the output of the switch 13 by one output of the frequency divider 9 shown in FIG. 2E.
,...obtain discontinuous signals. Similarly, switch 19 switches the readout outputs of SR16 and SR17,
The output of this switch 19 is multiplied by a multiplier 21 as shown in FIG.
Multiplying the other output of the frequency divider 9 shown in FIG.
At 6 and 17, we obtain discontinuous signals. These discontinuous signals are added by an adder 22 to obtain a high-pitched chorus signal without blanks.

In the bass reduction circuit 4, a control circuit 25 and an electronic switch 26 are supplied with a drive pulse from the flip-flop 20 as shown in FIG. 2H. Further, the control circuit 25 is supplied with the write clock _W from the fixed oscillator 6 and the read clock _RL (< _W ) from the other variable oscillator 8, and the control circuit 25 receives the write clock W by the above-mentioned drive pulse. _RL and read clock _RL to SR
23 and 24 alternately. Therefore, the SRs 23 and 24 alternately perform writing and reading, and the output of the switch 26 becomes a low-pitched chorus signal without blanks.

The pitch conversion ratio of the high-pitched and low-pitched chorus signals is determined by the frequency ratio of the write clock _W and both read clocks _RH and _RL , so
For example, the time constants of both variable oscillators 7 and 8, which are non-stable multivibrators, are varied by operating variable resistors to select the frequency of the readout clock. In this case, for example, as shown in Figure 3, both variable resistors are trimmed so that the ratio between the oscillation frequency of both variable oscillators and the oscillation frequency of the fixed oscillator becomes _RH / _W = _W / _RL . If it is adjustable, a chorus signal can be obtained with the same pitch difference above and below the original sound signal.

Alternatively, a keyboard-like switch (not shown) may be provided, and the resistance values of the time constant circuits of both variable oscillators 7 and 8 may be changed by operating this switch. In this case, the frequencies of both variable oscillators 7 and 8 can be changed independently of each other.

The high-pitched chorus signal and low-pitched chorus signal thus obtained are supplied to adders 30 and 31 via attenuators 27 and 28, respectively.

On the other hand, since both chorus signals are delayed due to signal processing in the treble-enhancing circuit 3 and the bass-enhancing circuit 4, the original sound signal is routed through a delay line 5, which is a shift register with an appropriate number of stages, to match the delay times, and then passed through an attenuator 29. The signal is supplied to both adders 30 and 31, and added to the high-pitched chorus signal and the low-pitched chorus signal, respectively.

The outputs of both adders 30 and 31 are connected to two-channel stereo left and right amplifiers 32L and 3, respectively.
2R, and the sound is emitted from left and right speakers 33L and 33R. In the reproduced sound field obtained in this way, the user's singing voice corresponding to the original sound signal is localized in the center, the high-pitched chorus voice corresponding to the high-pitched chorus signal is localized to the left, and the low-pitched chorus voice corresponding to the low-pitched chorus signal is localized to the center. The chorus sounds are localized to the right side, forming a trio that is extended both in pitch and space, creating an excellent chorus effect. Attenuator 2
7, 28 and 29 can be adjusted to obtain the desired chorus sound quality.

In place of these attenuators 27 to 29 and adders 30 and 31, the main parts of another embodiment are shown in FIG. 4, in which both high and low chorus signals and original sound signals are sent out either mixed or singly. . In FIG. 4, 3A, 4A, and 5A indicate terminals to which the high-pitched chorus signal, the low-pitched chorus signal, and the original sound signal are supplied, respectively, and the terminal 3A is fixed to the switch 34L via resistors _r2 and _r4 . It is connected to contacts a and c, and further connected to fixed contact c of switch 34R via resistor _r9 . Terminal 4A is connected to fixed contact d of switch 34L via resistor _r5 , and resistor _r7
and _r10 to fixed contacts a and d of switch 34R. Terminal 5A is connected to fixed contacts a and b of switch 34L via resistors _r1 and _r3 , and to fixed contacts a and c of switch 34R via resistors _r6 and _r8 . Connect the common contacts of switches 34L and 34R to terminals 30A and 31, respectively.
Connect to A.

The switches 34L and 34R are interlocked as shown in Fig. 4, and when they are set to contact a, the high-pitched chorus signal is sent to the left channel terminal 30A, and the low-pitched chorus signal is sent to the left channel terminal 30A. The chorus signal is supplied to the right channel terminal 31A, and the original sound signal is supplied to both left and right channel terminals 30A and 31A. At the position of the contact b, only the original sound signal is supplied, at the position of the contact c, only the high-pitched chorus signal is supplied, and at the position of the contact d, only the low-pitched chorus signal is supplied to both terminals 30A and 31A, respectively. Resistor
r ₁ to r ₁₀ are selected so that each signal is mixed at an appropriate level. In this way, each reproduction mode can be easily selected by the switches 34L and 34R.

FIG. 5 shows the main part of another embodiment in which high and low chorus sounds and original singing sounds are freely localized between the left and right speakers in the reproduced sound field. In FIG. 5, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant explanation will be omitted. In Figure 5, 3
B, 4B and 5B each indicate a buffer amplifier,
Via these buffer amplifiers 3B, 4B, and 5B, the high-pitched chorus signal, low-pitched chorus signal, and original sound signal from terminals 3A, 4A, and 5A are supplied to the sliding terminals of variable resistors 35, 36, and 37, respectively. do. Both ends of these variable resistors are connected to terminals 30A and 31A, respectively, so by adjusting the position of each sliding terminal, each sound image in the reproduced sound field can be freely moved between the left and right speakers and localized. can be done.

By the way, charge transfer elements such as the bucket brick device (hereinafter referred to as BBD) used in the shift register 5 etc. described above generate transfer noise due to the transfer clock, thermal noise, and noise due to instability of the element surface level. , which degraded the quality of the transmitted signal.

FIG. 6 shows the main part of yet another embodiment in which noise due to BBD is reduced. In this Figure 6, 38
indicates an input terminal, and the original sound signal from this input terminal 38 is supplied in parallel to the BBDs 39 ₁ , 39 ₂ . . . 39 _o . Reference numeral 40 indicates a clock pulse generator, and this clock pulse generator 40 generates a clock for each transfer.
Supplied in parallel to BBD39 ₁ to 39 _o . Each BBD3
The outputs of 9 ₁ to 39 _o are supplied to an output terminal 42 via an adder 41 . Reference numeral 43 denotes a differentiating circuit for canceling transfer noise; a clock pulse is supplied to this differentiating circuit 43, and the output of the differentiating circuit 43 is supplied to an adder 41.

Since each BBD 39 ₁ to 39 _o is driven by the same clock and there is no phase shift between the BBDs, the addition rule is established. Since thermal noise and noise caused by surface states are random in each BBD, the output voltage E ₀ of the adder 41 is as follows.

E ₀ =E _i1 +E _i2 +…+E _io +√ _N1 ² + _N2 ² +…+
E _No ² However, E _N1 ~ E _No is the noise voltage of each BBD.As can be seen from this equation, the S/N of the output of the adder 41 increases as the number of BBDs connected in parallel doubles.
increases by 3 dB.

The main cause of BBD transfer noise is that the charge transfer has transition characteristics due to the time constant of the storage capacitor and the dynamic resistance of the switching element. Transfer noise varies depending on each _BBD391 to _39o ,
This variation is averaged out by the parallel connection. Therefore, it is possible to differentiate the clock from the clock pulse generator 40 in the differentiating circuit 43 and supply its positive polarity output to the adder 41 at an appropriate level to compensate for the above-mentioned transition characteristics and reduce transfer noise as a whole. can.

If the configuration shown in FIG. 6 (excluding the clock pulse generator 40) is used in place of each shift register shown in FIG. can generate a chorus sound field.

As detailed above, according to the chorus sound field generator of the present invention, multiple chorus signals with a predetermined pitch difference are generated above and below the original audio signal, and these signals are transmitted in stereo. You can also enjoy an extended chorus effect.

In addition, although the example described the singing voice,
It goes without saying that the present invention can also be applied to the sound of a musical instrument.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the chorus sound field generating device of the present invention, FIGS. 2 and 3 are diagrams for explaining the present invention, and FIGS. 4 and 5 are diagrams showing other embodiments of the present invention. A wiring diagram showing the main parts of the embodiment, and FIG. 6 is a block diagram showing the main parts of still another embodiment of the present invention. 3 is a treble-enhancing circuit, 4 is a bass-enhancing circuit, 5, 10,
11, 16, 17, 23 and 24 are shift registers, 7 and 8 are variable frequency oscillators, 9 is a frequency divider,
12, 18 and 25 are control circuits, 15 and 21 are multipliers, 22, 30, 31 and 41 are adders, 4
3 is a differential circuit.

Claims (1)

[Claims for Utility Model Registration] A pitch variable circuit that changes the pitch of an original sound signal, a circuit that mixes the original sound signal and the pitch-changed signal to obtain a plurality of output signals, and a circuit that reproduces each of the plurality of output signals. A chorus sound field generating device is characterized in that it is equipped with a plurality of speakers, and is configured to mix an original sound signal and a signal with a different pitch at different mixing ratios and emit the sound.