JPH06104855A - Fading simulator - Google Patents

Abstract

PURPOSE:To attain ease of adjustment by devising the simulator to hardly receive the effect of temperature fluctuation without need of a high frequency balanced modulator and a high frequency phase shifter. CONSTITUTION:In the case f fading simulation, two transmission codes thetaA(t), thetaB(t) are obtained from same shift stages of a code delay means 72 or a delay is slightly shifted while the two codes keep correlation. Doppler shifts fa, fb in 1st and 2nd radio wave paths are given to synthesizers 93, 94 respectively and the phase difference of the two radio wave paths is decided by the setting phases thetaa, thetab, Rayleigh noise is given as A(t), B(t) and the attenuation is changed by attenuators 117, 119. In order to obtain an interference signal between adjacent channels, the difference from the delay is increased so that no correlation is in existence between the two signals thetaA(t), thetaB(t) outputted from a code delay means 72, and parts fa, fb of the setting frequency of a synthesizer are sufficiently parted to obtain an inter-channel frequency difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used to evaluate the receiving performance of a digital mobile communication system and the like, and is similar to a signal in the state of being subjected to Rayleigh scattering, Doppler shift or fading. It relates to a fading simulator that generates in real time.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional fading simulator. The in-phase signal I (t) and the quadrature signal Q (t) are applied to the quadrature modulator 11, and the modulation output thereof is converted (divided) into its real part and imaginary part in the coordinate converter 12 for converting polar coordinates to rectangular coordinates. ) Will be done. The converted real part and imaginary part are supplied to the multiplying DA converters 15 and 16 through the digital low-pass filters 13 and 14, respectively. The output voltage of the variable DC power supply 17 is applied to the reference voltage sources of the DA converters 15 and 16, and the DC voltage V _A is multiplied.

The outputs of these DA converters 15 and 16 are supplied to multipliers 18 and 19, respectively, and a sine wave oscillator 21 is supplied.
The carrier wave output of the frequency f _A from is directly applied to the multiplier 18
Is also supplied to the multiplier 19 through the 90-degree phase shift circuit 22, the outputs of the multipliers 18 and 19 are added by the adder 23, and the addition output, that is, the quadrature modulation output, is randomized by the multiplier 24. Noise generator 25
The noise from the noise A is adjusted to an appropriate level by the attenuator 26.
It is multiplied by (t). The signal multiplied by this noise is attenuated by G _{A in the} attenuator 27, and the attenuated output is delayed by t _{A in the} variable delay means 28 and is multiplied by the multiplier 29.
Is also supplied to the multiplier 32 through the phase shifter 31. A signal of frequency f ₁ is supplied from the sine oscillator 33 to the multiplier 29 and is also supplied to the multiplier 32 through the 90 ° phase shifter 34. The outputs of the multipliers 29 and 32 are added by the adder 35.

On the other hand, the output of the adder 23 is branched and passed through the fixed contact F side of the changeover switch 36 to the multiplier 37.
Will also be supplied. The noise from the noise generator 25 is given to the multiplier 37 through the attenuator 38 as noise B (t). The output of the multiplier 37 is attenuated by G _B by the attenuator 39, and the attenuated output is delayed by t _B by the variable delay means 41 and supplied to the multiplier 42. The output of the oscillator 43 that generates a sine wave of frequency f ₂ is supplied to the multiplier 42 and the multiplier 45 through the 90-degree phase shifter 44, and the output of the delay means 41 is also supplied to the multiplier 45 through the phase shifter 46. Supplied.
The outputs of the multipliers 42 and 45 are added by the adder 47. The outputs of the adders 35 and 47 are added by the adder 48, and the added output is attenuated by G _{C in the} attenuator 49 and output to the output terminal 51.

Further, the in-phase signal I '(t) and the quadrature signal Q' (t) quadrature-modulate the carrier wave in the quadrature modulator 52, and the modulated output is converted into the real part and the imaginary part in the coordinate converter 53. Then, the real part and the imaginary part are supplied to the multiplication type DA converters 56 and 57 through the digital low-pass filters 54 and 55, respectively. DA converter 5
The voltage V _B is applied to the reference power source terminals from the variable power source 58 and multiplied by V _B. DA converters 56, 5
7 outputs are supplied to multipliers 59 and 61,
The carrier wave of the frequency f _B from the oscillator 62 is supplied to the multiplier 59, and the multiplier 6 is supplied through the 90-degree phase shifter 63.
1 is supplied. The outputs of the multipliers 59 and 61 are the adder 6
4 is added, and the added output is supplied to the multiplier 37 through the fixed contact I side of the changeover switch 36.

In communication between a mobile station and a fixed station or a mobile station, a direct wave and a reflected wave are received at the same time, and the level and phase of the reflected wave change, or a plurality of reflected waves are mainly received. For this reason, the received signal has a changed level and phase. Further, the reception frequency fluctuates due to the so-called Doppler shift due to the relative movement between the mobile station and the fixed station. In order to carry out a simulation (fading simulation) of these fluctuation states, the changeover switch 36 is connected to the fixed contact F side. The output signal obtained at the output terminal 51 at this time is expressed by the following equation.

G _C · [G _A · A (t) · cos {2π
(F _A + f ₁ ) · (t−t _A ) + θ _A (t)} · V _A +
_{G B · B (t) ·} cos {2π (f A + f 2) · (t-
t _B ) + θ _A (t)} · V _A ] where A (t) is Rayleigh scattering in the first passage of the radio wave, and B (t) is equivalent to Rayleigh scattering in the second passage of the radio wave. The attenuation amounts G _A and G _B are the attenuation amounts of the first and second passages, respectively. f _A is the carrier frequency and f ₁ , f
₂ is the Doppler shift frequency in the first and second passages, respectively. Further, θ _A (t) is transmission information. Furthermore, t _A and t _B are the time delays of the first and second passages, respectively. Therefore, the attenuation amount of each of these parts or the delay means 2
By changing the delay amounts t _A and t _{B of} 8, 41 and the frequencies f ₁ and f ₂ , it is possible to simulate various states, that is, the states in which fading is actually performed.

On the other hand, the interference between adjacent channels is simulated.
To do this, connect the selector switch 36 to the fixed contact I side.
It The output of the output terminal 51 in this state is expressed by the following equation.
Be done. G_C・ [G_A・ A (t) ・ cos {2π (f_A+ F₁)
* (T-t_A) + Θ_A(T)} · V_A+ G_B・ B (t)
・ Cos {2π (f_B+ F₂) ・ (T-t_B) + Θ
_B(T)} · V_B] Where θ_B(T) is transmission information on the channel B side. f
_BIs the carrier frequency on the channel B side. Adjacent in this case
Carrier frequency f between channels_A+ F ₁And f_B
+ F₂Between them and their time or phase is delayed.
It is adjusted by the extending means 28 and 41, and the frequency difference is f
₁, F₂, F_A, F_BChanged by the level
G_A, G_BWill be changed in.

[0009]

Conventionally, the variable delay means 28 and 41 are used to change the difference between the two paths, but in order to obtain the delay times t _A and t _B , the so-called line is usually used. Since the delay time of the cable is used, the delay time changes according to the temperature change, and the delay distortion occurs depending on the frequency, so that it is difficult to change the delay time with a wide range with high resolution.

A number of high frequency balanced modulators or multipliers 18, 19, 24, 29, 32, 37, 42, 4 are also provided.
5, 59, 61 are used, and more high-frequency phase shifters are used, so it is difficult to adjust the frequency. Moreover, two systems were used and the configuration was complicated.

[0011]

According to the present invention, the transmission code is stepwise delayed from the code delay means, and
For each sign of the one delayed output, the first real part and the first imaginary part, the second real part and the second imaginary part are converted by the first and second coordinate exchange means, and these first real part and first imaginary part are The cosine wave output and the sine wave output from the first digital synthesizer are respectively multiplied by the first and second multiplying means, and the outputs of these first and second multiplying means are respectively obtained by the first and second multiplying DA converting means. It is converted into an analog signal while being noisy. On the other hand, in the second real part and the second imaginary part, the cosine wave output and the sine wave output from the second digital synthesizer are respectively multiplied by the third and fourth multiplication means, and the third and fourth multiplication calculation powers are the third and fourth multiplication powers, respectively. The noise different from the above is multiplied and converted into an analog signal by the quadruple multiplication DA converter. The outputs of the first and third DA conversion means are added by the first addition means, and the second, third, and fourth DAs are added.
The outputs of the converting means are added by the second adding means, and the outputs of these first and second adding means are quadrature-modulated by the quadrature modulating means.

[0012]

FIG. 1 shows an embodiment of the present invention. The transmission information θ (t) from the quadrature modulator 71 is supplied to the code delay means 72 and its code unit, that is, stepwise delay is performed.
The code delay means 72 is, for example, a shift register or a FIFO.
A memory or the like is used. In the quadrature modulator 71, the data generation clock from the data generation clock generator 73 is frequency-divided by the frequency divider 74 to 1/2, and the frequency division output is counted by the address counter 75, and the address counter 75 is generated. In-phase memory 7 using the count value of
6. The quadrature memory 77 is read out and the in-phase signal I (t) and the quadrature signal Q (t) are output. Both of these outputs are supplied to a modulator 81 through changeover switches 78 and 79, respectively, and a carrier wavelength, for example, π / 4DQPSK.
Modulate. The switches 78 and 79 are switched when an in-phase signal and a quadrature signal from the outside are input.

The code delay means 72 outputs signals to which different delays have been given in the respective code units or the same delay has been given. When the code delay means 72 is, for example, a shift register, outputs from different taps (shift stages) or outputs from the same tap (shift stages) are taken out as code transmission information θ _A (t) and θ _B (t), respectively. , Coordinate conversion means 82 and 83. The input code is converted into polar coordinates and Cartesian coordinates in the coordinate conversion means 82 and 83, and the real part and the imaginary part are output. The real part and the imaginary part from the coordinate conversion means 82 are respectively FIR digital low pass filter 8 as required.
It is supplied to multipliers 86 and 87 through 4,85. The real part and the imaginary part from the coordinate conversion means 83 are supplied to the multipliers 91 and 92 through FIR type digital low pass filters 88 and 89 as needed.

On the other hand, digital synthesizers 93 and 94 are provided. The digital synthesizers 93 and 94 are capable of changing the phase and frequency, and are configured as shown in FIG. 2A, for example. That is, the output of the adder 97 is latched in the latch circuit 96 by one output from the toggle type flip-flop 95 whose frequency f _R is halved. The adder 97 adds the output of the latch circuit 96 and the frequency data k _f. The output of the latch circuit 96 is added to the phase data kθ by the adder circuit 98, and the output thereof is given a phase of 0 degree or a phase shift of 90 degrees in the phase shift circuit 99, and is read out to the sine wave memory 101 as a read address. Supplied. The sine wave memory 101 stores the level of each sine waveform sample point, and the read digital sine wave signal is stored in the latch circuit 26.
Is latched by the latch circuit 102 in response to the latch command for, and latched by the latch circuit 103 by a signal whose phase is shifted by 180 degrees with respect to this latch command. The output of the latch circuit 102 becomes a digital sine wave output, and the output of the latch circuit 103 is latched by the latch circuit 104 at the same time as the latch for the latch circuit 26.
A digital cosine wave output is obtained from 4. Since the frequency data k _f is cumulatively added for each of the frequency f _R / 2 clock, the frequency becomes higher as the frequency data k _f is large, the frequency becomes lower as the frequency data k _f is small.
Since the phase shift circuit 99 outputs as it is or outputs with a 90-degree phase shift, as shown in FIG. 2B, the most significant bit and the next bit of the input data are passed as they are, or they are excluded. It is only necessary to switch whether to output the logically ORed bit as the most significant bit, and invert the second most significant bit as the second most significant bit. In this way, the frequency is f _R × kf ÷
A sine wave output and a cosine wave output having 2 ^{L + 1} and a phase θ of 2π × kθ ÷ 2 ^L are obtained. f _R is the frequency of the clock that drives the flip-flop 95.

Returning to the description of FIG. 1, the synthesizer 93
For frequency f₁+ Fa is set and phase θa is set
Then, the cosine wave output cos {2π (f₁+ F
a) t + θa} is output and supplied to the multiplier 86,
Sinusoidal output sin {2π (f ₁+ Fa) · t + θa}
Is output and supplied to the multiplier 87. Meanwhile synthesizer
Frequency 94₁+ Fb is set, phase
θb is output, and its cosine wave output cos {2π (f₁+
fb) · t + θb} is supplied to the multiplier 91, and a sine wave is output.
Force sin {2π (f₁+ Fb) · t + θb} is the multiplier 9
2 is supplied. The outputs of the multipliers 86 and 87 are respectively
It is supplied to the multiplication DA converters 105 and 106, and multiplication
The outputs of the converters 91 and 92 are respectively the multiplication type DA converter 10
7, 108. On the other hand, the random noise generator 10
Random noise is generated from 9, and the noise is
After being attenuated by the attenuator 111, the variable DC power source 112
Is added by the addition circuit 113 and the addition
The output of the circuit 113 is a multiplication type as Rayleigh noise A (t).
It is supplied to each reference power supply terminal of the DA converters 105 and 106.
The input digital signal is multiplied by
The digital signal is converted to an analog signal. Similarly noise
The noise from the generator 109 passes through the attenuator 114 and the adder 1
15 and the output DC voltage of the variable DC power supply 116
Is added, and the output from the adder 115 is Rayleigh noise B.
As (t), the reference voltage of the multiplier DA converters 107 and 108 is set.
Source terminal and is applied to its input digital signal.
Is calculated and the digital signal is converted to an analog signal.
Will be replaced.

[0016] Each output of the DA converter 105 is attenuated by Ga, respectively, in each attenuator 117, 118, and each output of from DA converter 107, 108 are attenuated by the respective G _B In the attenuator 119, 121 It The outputs of the attenuators 117 and 119 are added by the adder 122 and supplied to the multiplier 123.
The outputs of 18 and 121 are added by the adder 124 and supplied to the multiplier 125.

The signal from the reference signal generator 126 has a frequency f _R and is supplied as a clock to the synthesizers 93 and 94, and its output is a frequency divider 127.
Is supplied to the data generation clock generator 27 after being divided by an integer, and is supplied as a shift clock to the code delay means 72 and is supplied to each unit as a clock for other digital processing. Further, the output of the reference signal generator 126 is a phase locked loop (PL
L) 128 is supplied as a reference signal to the PLL 12
8 carrier frequency f ₀ -f ₁ is set input to, the frequency f ₀ -f ₁ synchronized with the reference signal signal cos {2π (f
_0- f ₁ ) · t} is output, which is supplied to the multiplier 123 as a carrier signal and also to the multiplier 125 through the 90-degree phase shifter 129. Multipliers 123, 12
The output of No. 5 is added by the adder 131, and the added output is attenuated by the attenuator 132 and output to the output terminal 133. Multipliers 123, 125, phase shifter 129, adder 13
Reference numeral 1 constitutes a quadrature modulation circuit 134. PLL1
In order to set the output carrier frequency of 28 to f ₀ −f ₁ , it is necessary to increase or decrease the carrier frequency f ₀ of the output signal of the output terminal 133, that is, a negative frequency can be generated in the synthesizers 93 and 94. F ₁
As high frequency, positive and negative frequencies f
It is possible to freely select a and fb, whereby the frequency of the output carrier wave in the quadrature modulation circuit 13 can be changed positively and negatively by fa and fb with respect to the center f ₀ .

In this configuration, when a shift register is used as the code delay means 72, the shift frequency is f _d, and the shift stages from which the output is taken are na and nb, they are supplied to the coordinate conversion means 82 and 83. The code information is θ _A (t) = θ (t−na / fd), θ _B (t), respectively.
=? (T-nb / fd). Therefore, the signal output from the terminal 133 is as follows.

Gc · [Ga · A (t) · cos {2π
(F ₀ + fa) · t + θa + θ (t-na / fd)} +
Gb · B (t) · cos {2π (f ₀ + fb) · t + θ
b + θ (t-nb / fd)}] In the case of fading simulation, the code selecting means 7
From the same shift stage in 2, two transmission codes θ
Obtain _A (t) and θ _B (t), or transmit code θ
_{A (t), θ B (} t) is shifted slightly delay amount in a state to maintain the correlation. Rayleigh scattering on the two radio wave paths is given as A (t) and B (t), and each Doppler shift in the first radio wave path and the second radio wave path is f.
Small values are given as a and fb. Part 2
The phase difference between the two radio wave paths is the digital synthesizer 93,
The Rayleigh noise is determined by the set phases θa and θb at 94, given by A (t) and B (t), and the attenuation amount is changed by the attenuators 117 and 119. The delay time of the first radio wave path is {(na / fd) -θa / 2π (f ₀
+ Fa)}, and the time delay of the second radio wave path is given by {(nb / fd) −θb / 2π (f ₀ + fb)}. By doing so, it is possible to control each unit and obtain a signal having a fading effect as in the conventional technique.

In the case of obtaining an interference signal between adjacent channels, the two signals θ _A (t) and θ _B (t) output from the code delay means 27 are mutually delayed so that there is no correlation. In order to obtain a large frequency difference between channels in that state, the synthesizer 93,
Part of the set frequency of 94, fa and fb, are separated from each other. Also in this case, interference signals between adjacent channels can be simulated as in the conventional case.

In the above description, the coordinate conversion means 82, the filters 84 and 85, the multipliers 86 and 87, and the DA converter 10 are used.
5, 106, attenuator 111, adder 113, attenuator 11
By providing a plurality of sets of 7, 118 and a power supply 112, it is possible to perform multipath fading simulation and interference simulation between many channels. Further, in the above description, the fading simulation is performed on the π / 4DQPSK modulated signal, but by changing the modulator 71, fading to other communication systems and interference between adjacent channels can be simulated.

[0022]

As described above, according to the present invention, the difference between the two paths and the difference between the signal paths of the adjacent channel interference are determined by the difference between the delay in the code delay means 72 and the set phase in the frequency synthesizers 93 and 94. Since it is made digitally using the difference, etc., it does not use the delay line as in the past, so it is not affected by fluctuations in the ambient temperature and is stable against temperature and frequency changes over a continuous and wide range. It is possible to perform distortion-free transmission delay simulation. Also, because the Rayleigh scattering and the Doppler shift processing are realized digitally at a relatively low frequency,
A balanced modulator and a phase shifter at a high frequency need only have the quadrature modulation circuit 134 at the final stage, and therefore adjustment to the frequency is easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a digital synthesizer, and B is a block diagram showing a phase shift circuit 99 thereof.

FIG. 3 is a block diagram showing a conventional fading simulator.

Claims (1)

[Claims] 1. A code delay means for realizing a step delay of a transmission code, first and second digital synthesizers with variable phase and frequency, and a first real part for each of two code outputs from the code delay means. A second real part of the first imaginary part, first and second coordinate conversion means for obtaining a second imaginary part, respectively, a cosine wave output of the first synthesizer, a sine First and second multiplication means for respectively multiplying the wave output, and third and fourth multiplication means for respectively multiplying the second real part and the second imaginary part by the cosine wave output and the sine wave output of the second synthesizer, respectively. , The first and second DA for multiplying the outputs of the first and second multiplying means by noise and converting the output into an analog signal
A conversion means, the third and fourth multiplication means are respectively multiplied by noise different from the noise, and at the same time converted into an analog signal,
Fourth DA converting means, first adding means for adding the respective outputs of the first and third DA converting means, second adding means for adding the respective outputs of the second and fourth DA converting means, A fading simulator comprising: a modulator that quadrature modulates the outputs of the first adder and the second adder.