JPS5868297A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent malfunction due to an abnormal current and deterioration and a breakdown of an element, by providing a means of setting the source potential of a writing load transistor (TR) for writing data in a floating gate MOS memory to a prescribed level. CONSTITUTION:At a memory part 11, plural memory cells MC each consisting of an MOSFETTF of floating gate structure are arrayed in a matrix. This memory is equipped with a row decoder 12, a column decoder 13, a column direction selecting circuit 14, inverters I1-I3 for successively inverting a data input signal DIN, a writing load FETT1, and a writing control FETTW1, and the source of the FETT1 and the common output terminal of the column direction selecting circuit 14 are connected to a sense amplifier. Through the potential setting part 15 consisting of a writing control FETTW2, a potential setting FETT2, and a switch FETT3, the source potential of the FETT1 is set to a prescribed potential prior to data writing to a memory cell MC, preventing the generation of an abnormal current.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory constituted by memory cells having MOB (insulated gate field effect) transistors having a floating gate structure. Gate voltage vcs(v)i-Drain voltage VD as parameter
8 (V) vs. drain current ID (mA) characteristic of 0. As can be seen from this characteristic curve, the drain breakdown voltage at the intermediate value is lower than at the low and high gate voltage regions. This is because this part is exactly in the saturation region, and part of the holes among the electron and hole pairs generated by impact ionization that occurs near the drain flows to the substrate, and the substrate potential changes to the source potential. The energy consumption also increases, resulting in a kind of pibo-transistor operation, which exhibits breakdown/characteristics at lower drain voltages. And is this negative resistance operation as shown in Figure 1? However, once it enters this breakdown region, the flow of abnormal current does not stop even if the drain voltage is lowered to some extent. Therefore, this abnormal current may destroy the element or accelerate its deterioration.

In a transistor (MOS), the drain voltage vDSt-
Figure 2 shows the so-called load characteristics of the current measured by keeping the source voltage constant (for example, 18V) and varying the source voltage. In this case as well, at a certain gate potential an abnormal current as explained in FIG.

time, gate voltage VGS-20V, source voltage V8 s,
3 shows a general nonvolatile semiconductor memory, and when write data 10# is given by the data input signal DIN,
Only the write cell becomes conductive, and writing is performed in the memory cell selected by the row decoder and column decoder. On the other hand, when the signal DIN is "1", the gate of the transistor T1 is @031, the transistor T is not turned on, and writing to the memory cell is not performed. In this way, data of 10" and '1" is normally written into the memory cell.

By the way, when the write load transistor T1 enters a conductive state when the signal DIN is 10'', its gate becomes OV.
to Vp (for example, 20v). At this time, the source potential also rises from Ov to a value determined by the conduction resistance of the memory cell and the load transistor T. However, in this case, for a certain period of time, the vehicle passes through an area where an abnormal current flows as shown in FIG. For this reason, an abnormal current flows through the transistor T, which may accelerate the deterioration of the transistor T1 even if it does not lead to destruction. In addition, at this time, the substrate potential near the transistor T increases, causing an increase in leakage current, which may cause malfunction of the circuit, and the increase in substrate potential may induce bipolar operation of other circuit elements. However, there is a danger that the device may be destroyed.

The present invention has been made in view of the above circumstances, and when writing data to a plurality of memory cells composed of floating gate structure MOS transistors, the sources of the write load transistors to which these memory cells are connected in common. By providing a potential setting means for setting the potential to a predetermined potential level in advance, the load transistor can be used without passing through an abnormal current region, thereby preventing malfunctions and element deterioration due to abnormal current. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows the non-volatile semiconductor memory metal of the present invention, 1
1 has a floating gate structure 7jMO8) transistor Tr
12 is a memory section configured with a memory section in which a plurality of MCs are arranged in a matrix;
a row decoder 13 for specifying the row direction address of the memory section 11; a column decoder 13 for specifying the column direction address of the memory section 11;
14 is a column direction selection circuit which selects the corresponding memory section 11'lf in response to the decoded output from the column decoder 13; X1 to (3) are inverters that sequentially invert the data input signal DIN'li; The load transistor %T''l is a write load transistor driven by the write control signal W1. Furthermore, in the present invention, prior to writing data into the memory cell MC of the memory section 11, the source potential of the write load transistor i is set to a predetermined potential. A potential setting section 15 is provided.This potential setting section 15 is connected to the output of the inverter I, that is, the inverter I that inverts the data input signal DIN, and the power terminal of this inverter Iρ, Write control signal W2 becomes @0'' level at a timing earlier than signal DIN and write control signal W1.
a write control transistor TW2 driven by the inverter; a transistor T for determining the source potential of the load transistor TI; and a transistor T connected between the source of this transistor T and the source of the load transistor TI, ! In the figure, Vp is a high voltage power supply (for example, 25V) f, ve.
is a general high-level power supply (e.g. 5 V) f
, Vs is a general low level power supply (e.g. 0V)
In the above circuit, before data is written to the memory cell MC, the north potential vsst of the load transistor T is raised to 1, and then the gate potential of the load transistor Ti is raised. The load transistor T.

For example, the source potential is set to the above source potential VS8f4V, and then the load transistor Ts'lr is made conductive. In other words, it does not pass through areas where abnormal current flows. This makes it possible to prevent deterioration and destruction of the element due to abnormal current.

By the way, when the memory cell MC is turned on during data writing, the transistor T cannot raise the source of the load transistor T1 to a predetermined potential unless it has a sufficiently large current supply capability. However, transistor T
If , is large, a large capacitance load occurs when reading data, and the read speed becomes slow. So, this transistor T! By raising the gate of the load transistor Tsk to the potential of the high voltage power supply Vp through the switching transistor Tsk, the load transistor T! The source potential of the device is increased. In this case, no matter how large the transistor T is, the switching transistor T
, does not have a large load capacity because of the cutoff. Therefore, high-speed reading is possible as before. By the way, here is a transistor! The drain of is Vp
Although it is connected to Vc, it may also be connected to Vc.

FIG. 5 shows a circuit suitable for an inverter using a high voltage power supply Vp. In this circuit, a resistor "le" is connected in series between the high voltage power supply Vp and the power supply Vs! An inverter consisting of transistors T4yT6 using a high voltage power supply Vpk to create a predetermined set potential level. This predetermined potential level is fully input to the gate of the transistor TI through the transistor T between the transistors T4 and To of the transistors T, and the control input is applied to the gate of the transistor T.
Make sure that high voltage is not applied directly to the drain of the capacitor.

FIG. 6 shows a different embodiment circuit of the potential setting section 15 of the present invention. This circuit uses the circuit shown in FIG. 5 in place of the inverter I shown in FIG. 4, and uses the inverter 1.1 as its control input. to output 1! ! ,)? The drain potential of the transistor T is all led to the gate of the transistor T1, and furthermore, the drain potential of the transistor T is connected to the gate of the transistor T1 in FIG.
~T? -5t- They are sequentially connected to a high voltage power supply vp and are controlled so that a predetermined potential level is output from this power supply Vp.

In other words, the threshold voltage v of transistors T, -8 to T, -3
Since the predetermined potential level of the source of the load transistor T is set by th, any number of the transistors T7-1 to T, -3 may be connected to the set potential level. The potential setting section 15 shown in FIG. 6 also exhibits the effect similar to that of the above-mentioned embodiment.

As described above, according to the present invention, the write load transistor 1 can be used without passing through the breakdown region, so it is possible to prevent element O deterioration or destruction due to abnormal current, and to provide a highly reliable non-volatile transistor. It can be made of semiconductor material.

As explained above, according to the present invention, when all data is written to a double-layered memory cell composed of nine Mog transistors having a floating gate structure, the source potential of the write load transistor to which these memory cells are connected in common is Providing a potential setting means for setting the potential level to a predetermined potential level in advance,
Since the load transistor can be used without passing through the abnormal current region due to breakdown, it is possible to provide a highly reliable nonvolatile semiconductor memory by preventing malfunctions, element deterioration, and destruction caused by this abnormal current. .

[Brief explanation of drawings]

Figure 1 is a drain voltage vs. drain current characteristic diagram of a MOS transistor, Figure 2 is a load characteristic diagram of a MOS transistor, and Figure 3 is a circuit configuration diagram of a conventional nonvolatile semiconductor memory.
Figure 4 is a circuit configuration diagram of a non-volatile semiconductor memory according to an embodiment of the present invention, and Figure 5 is an impeller using a high voltage power supply.
FIG. 6 is a diagram showing a circuit configuration suitable for another embodiment of the potential setting section of FIG. 4. 1.. Memory section, 12.. Row decoder, 13..
- Column decoder, 14... Column direction drive circuit, 15...
Electric! , T*eT4-T7...transistor, T3...
-Switching transistor, 11~■,...Inverter, TWl, TW,...Writing control transistor, R1@R2...Resistor, Vp...High voltage power supply. Applicant's representative Patent attorney Takehiko Suzue Figure 1 VL) S (V) Figure 2

Claims (2)

[Claims] (1) MOS with floating gate structure) In a non-volatile semiconductor memory in which all memory cells are arranged in a matrix formed by transistors, writing is performed to write data to the memory cell when writing data to the memory cell. 1. A nonvolatile semiconductor memory characterized in that a potential setting means for presetting a source potential of a load transistor to a predetermined potential level has a gold film. (2) The potential setting means is gated to a high voltage power supply. a transistor whose drain is connected to determine the level of the source potential of the load transistor; and a transistor that is connected between the source of this transistor and the source of the load transistor, and that corresponds to the write data when writing data to the memory cell. Claim 1, further comprising: a switching transistor which is Geswitching-controlled and sets the source of the load transistor to a predetermined potential level for the transistor.
Non-volatile semiconductor memory as described in Section.