JPS5858626B2 - phase detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for detecting the phase of the center of a pulse when the pulse width varies.

For example, when producing a rectangular waveform output based on a sine waveform input, such as the output of a photo-isolator, it is inevitable that the width of the output pulse will fluctuate due to various causes.

In this case, the method of extracting a signal based on the rise or fall of a pulse of an output wave has the drawback that the phase of the signal changes due to a change in pulse width.

Therefore, such an output cannot be used for, for example, phase difference counting.

However, even in the above rectangular wave output, the center point of each pulse coincides with the center of the input regardless of pulse width fluctuations.

Therefore, the purpose of this device is to provide an output having a phase having a predetermined relationship with the center point of a signal such as a photo-isolator.

This device is equipped with a phase correction section that is operated by pulses such as the output of a photo-isolator, so that it is possible to always obtain an output that has a predetermined phase angle relationship with the center point of the pulse, regardless of fluctuations in the pulse width. It is something.

In the embodiment, an output signal is provided that rises at the center of the pulse.

The invention will be explained below with reference to the embodiment shown in FIG.

For example, the frequency f from a pulse signal source such as a photo isolator PHI outside the device that receives a sinusoidal input signal at its terminal IN.

Hz signal is input to the AND gate A1. A2 and a frequency multiplier PLL using a known phase-locked loop or the like.

The frequency multiplier PLL outputs the frequency of nfQ increased by n times as a clock signal to, for example, a delay circuit DL outside the device, and a part of this output is passed through a line 8 to an AND gate A3. A4 and the input terminal of a known phase shifter PS.

ANDGATE A3. A4 is the AND gate Al.

The outputs of A2 are respectively used as the other inputs, and each output is provided as the ab and down inputs of the ab down counter UDC.

The carry output and borrow output of the ab-down counter UDC are given to the phase shifter PS as left shift and right shift command signals, respectively.

The nfo hertz output that has undergone phase control from the phase shifter is -
is input to the frequency divider FD.

f from frequency divider FD. The Hertz output is applied directly to the second input terminal of AND gate A2 and through an inverter N to the second input terminal of AND gate AI.

Furthermore, the 21 o hertz output of the frequency divider FD and f.

Hertz outputs are provided to the clock input terminal and D input signal terminal of the D flip-flop DFF, respectively.

The Q output or Q output of the D flip-flop DFF is the final output, and this output signal is applied to line 1.

It has a predetermined phase angle with respect to the center point of the Hertzian input signal.

The operation of the above-mentioned circuit will be explained below using the waveform diagrams shown in FIGS. 2 and 3.

AND gates A1 and A2 are f shown in FIG. 2 PLL from input line 1.

The hertz input pulse signal and the hertz output of double period n10 shown in the PLL in FIG. f shown in FD
.

Hertz signal and its inverted signal shown in FIG. 2N are compared and the AND gate A1. Figure 2 AI, A to the output terminal of A2.
Obtain each output of the waveform shown in 2.

The output pulse of the AND gate A1 changes in pulse width to become thinner or thicker depending on the phase advance or delay of the rising point of the output signal of the frequency divider circuit FD (FD in FIG. 2).
The output pulse of changes in the opposite direction.

Therefore, these ant gates A1. AND gate A3. which is formed by gating the nfo hertz signal on line 8 by the duration of the output pulse of A2. Similarly, the number of pulses of the output of A4 decreases and increases, and increases and decreases, respectively, depending on the advance and delay of the rising point.

ANDGATE A3. The pulse outputs of A4 are respectively given to ab down counters UDC.

This counter has a frequency division function of a predetermined ratio, and
-A3. It is determined which pulse number of A4 is larger, and a right shift or left shift command signal is given to the phase shifter PS.

In the example shown in FIG. 2, the number m of output pulses of AND gate A4 is greater than the number n of output pulses of AND gate A3, and in this case, ab-down counter UDC provides a borrow output as a right shift command signal.

The output of phase shifter PS therefore operates to shift the output to the right, ie to retard the phase.

This phase shifting operation continues until the center point of the input pulse to line 1 and the rising time of the output pulse of frequency divider FD coincide as shown in the waveforms of FIG. 3.

Each waveform in FIG. 3 corresponds to each waveform in FIG. 2 with the same reference numeral.

Due to the above coincidence, the phase shifter P is transferred from the ab-down counter UDC to the phase shifter P.
Since there is no longer a command signal to S, the output pulses of the frequency divider stop at the phase shown in FIG.

If for some reason the phase of the output of the frequency divider FD deviates from the matching state shown in Figure 3, the ab-down counter UDC outputs an output to the phase shifter PS again as described above to correctly correct the phase. .

Finally, f of the branching device FD.

By giving the Hertz output and the 21o Hertz output to the D flip-flop circuit DFF, the output is an output that is 90 degrees out of phase with the output of the frequency divider FD shown in FIG. 3 FD, as shown in FIG. 3 DFF. It can be obtained at terminal Q or Q.

This output pulse is phase controlled so that it rises at the midpoint of the input pulse to line 1.

Therefore, with this output pulse, it is possible to detect the phase of the center point of the wave of the input signal to line 1, and furthermore to the input signal to the preceding stage, for example, a photo-isolator.

[Brief explanation of the drawings] Fig. 1 is a block diagram showing the configuration of the embodiment, and Fig. 2 is a block diagram showing the configuration of the embodiment.
FIG. 3 is a voltage waveform diagram of each part in a state in which phase difference correction has not been completed in the example shown in the figure, and FIG. 3 is a voltage waveform diagram in each part in a state in which phase correction has been completed in the example shown in FIG. In the figure, UDC...About down counter,
A1. A2, A3, A4...And gate, N
...Inverter, DFF...D flip-flop.

Claims (1)

[Scope of Claims] 1. Pulse generating means for generating an output pulse signal having the same frequency as the human pulse signal, the output pulse signal of the pulse generating means, and its polarity inverted pulse signal are each compared with the input pulse signal to generate a pair of pulse signals. a first pair of AND gates that provide an AND output; a pair of AND gates that gate a lock pulse by the first pair of AND outputs; A second pair of AND gates for providing a pulse train, means for providing a pulse number difference signal of the l pairs of pulse trains, and a phase shifter for controlling the phase of the output pulse signal by the pulse number difference signal. Characteristic phase detection device. 2. A frequency multiplier that multiplies a human input signal to provide the clock pulse, and a frequency divider that outputs a signal obtained by controlling the phase of the clock pulse using the phase shifter and provides the output pulse signal. A phase detection device according to claim 1. 3. An ab-down counter that uses each output of the second pair of AND gates as an ab input and a down input and provides a carry output and a borrow output as a left/right or right/left shift signal to the phase shifter as a means for providing the pulse number difference signal. A phase detection device according to claim 1.